INTEGRATED GaN-BASED LOGIC LEVEL TRANSLATOR

Abstract

A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.

Claims

1. An integrated GaN based logic-level shifter, comprising: a GaN differential comparator having first and second inputs and corresponding positive and negative outputs; and a resistive network comprising a plurality of resistors, the resistive network including a first voltage divider for receiving an input signal and outputting a level shifted and scaled input signal, and a second voltage divider for generating a trip voltage, the second voltage divider including a resistive hysteresis circuit; wherein the level shifted and scaled input signal from the first voltage divider is connected to the first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive and negative outputs of the GaN differential comparator comprise complementary bipolar level shifted signals corresponding to the input signal.

2. The integrated GaN based logic-level shifter according to claim 1, wherein the first voltage divider comprises a first resistor, a scale resistor, and an offset resistor disposed in series between a voltage supply and a lower voltage.

3. The integrated GaN based logic-level shifter according to claim 2, wherein the input signal is connected between the scale resistor and the offset resistor, and the first input of the GaN differential comparator is connected between the first resistor and the scale resistor.

4. The integrated GaN based logic-level shifter according to claim 2, wherein the values of the first resistor and the offset resistor are set such that the level shifted and scaled input signal to the first input of the comparator hovers around an optimal bias point of the comparator.

5. The integrated GaN based logic-level shifted according to claim 4, wherein the second voltage divider generates a trip voltage which hovers around the optimal bias point of the comparator.

6. The integrated GaN based logic-level shifter according to claim 2, wherein the GaN differential comparator is configured to control the hysteresis circuit by outputting a signal to a gate of a FET connected across the hysteresis circuit.

7. An integrated GaN based logic-level shifter for a differential input having first and second input signals, comprising: a GaN differential comparator having first and second inputs, and corresponding positive and negative outputs; and a resistive network comprising a plurality of resistors, the resistive network including: a first voltage divider for receiving the first input signal and outputting a first level shifted and scaled input signal, and a second voltage divider for receiving the second input signal and outputting a second level shifted and scaled input signal; wherein the first level shifted and scaled input signal from the first voltage divider of the GaN differential comparator is connected to the first input of the GaN differential comparator, and the second level shifted and scaled input signal from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive and negative outputs of the GaN differential comparator comprise complementary bipolar level shifted signals corresponding to the first and second input signals.

8. The integrated GaN based logic-level shifter according to claim 7, wherein the first voltage divider and the second voltage divider each comprise a first resistor, a scale resistor, and an offset resistor disposed in series between a voltage supply and a lower voltage.

9. The integrated GaN based logic-level shifter according to claim 8, wherein the first and second input signals are connected, respectively, between the scale resistor and the offset resistor of the first and second voltage dividers, respectively, and the first and second inputs of the GaN differential comparator are connected between the first resistor and the scale resistor of the first and second voltage dividers, respectively.

10. The integrated GaN based logic-level shifter according to claim 8, wherein the values of the first resistor and the offset resistor of the first and second voltage dividers are set such that the level shifted and scaled input signals at the first and second inputs of the comparator hover around the optimal bias point of the comparator.

11. The integrated GaN based logic-level shifter according to claim 7, wherein the first and second voltage dividers each further comprise a respective resistive hysteresis circuit.

12. The integrated GaN based logic-level shifter according to claim 7, further comprising first and second input resistors for reducing the voltage levels of the first and second input signals, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To further clarify the above and other advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0018] FIG. 1 is a conventional logic-level shifter circuit;

[0019] FIG. 2 is a conventional differential latch-based logic-level shifter;

[0020] FIG. 3 is a conventional common-gate based logic-level shifter;

[0021] FIG. 4 is a prior art voltage divider level-shifter circuit design;

[0022] FIG. 5 shows the resistive network-based logic-level shifter circuit of the present invention with a single-ended input;

[0023] FIG. 6 shows the resistive network-based logic-level shifter circuit of the present invention with a differential input; and

[0024] FIG. 7 shows the resistive network-based logic level shifter circuit of the present invention with a differential input and with series input resistors to accommodate large input signals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] It is to be understood that the figures and descriptions of the present invention may have been simplified to illustrate only elements that are relevant for a clear understanding of the present embodiments. Those of ordinary skill in the art will recognize that other elements may be desirable and/or required in order to implement the present embodiments. It is also to be understood that the drawings included herewith only provide diagrammatic representations of the presently preferred embodiments of the present invention. Reference will now be made to the drawings wherein like structures are provided with like reference designations.

[0026] FIG. 5 shows the resistive-network based logic-level shifter of the present invention, designed to level shift a low voltage input signal (e.g., a CMOS level signal) to a voltage level above the maximum threshold voltage V.sub.th of a GaN transistors integrated in a GaN IC. Level shifter circuit 500 includes a resistive network 502, a GaN differential comparator 520, a single-ended input signal In, and an input Off (to pull the input signal low), as well as power supply sources Vdd and Vss. GaN differential comparator 520, connected to power supply sources Vdd and Vss, receives input signals InP and Vtrip from resistive network 502 and produces level shifted output signals OutP and OutN of opposite phase (complementary bipolar). Vtrip is the level that the input signal In must exceed as a minimum V.sub.inHi_Low level for output OutP to go high.

[0027] More specifically, as shown in FIG. 5, input signal In is connected to a voltage divider between Vdd and Vss which includes a resistor 504, a scale resistor 506, and an offset resistor 508, connected in series and forming a voltage divider for level shifting and scaling the input In to input InP. The values of resistor 504 and scale resistor 506 are set such that InP hovers around the optimal bias point of GaN comparator 520, thereby improving the speed of the comparator. Offset resistor 508 ensures that if the input In is floating, the output OutP stays low and output OutN stays high. The value of offset resistor 508 is dependent upon the amount of maximum input offset expected at comparator 520.

[0028] The voltage of the Vtrip input to GaN comparator 520 is determined by the values of resistors 510 and 512, which form a voltage divider to set the voltage at the Vtrip input to the comparator 520. In a similar manner to the voltage divider for the input signal, resistors 510 and 512 are set so that Vtrip hovers around the optimal bias point for the input of comparator 520. Vtrip is also determined by hysteresis circuit H formed of by resistor 516 and FET 518, which is controlled by one of the positive outputs of the comparator 520, similar to the output OutP. Hysteresis circuit H ensures that any noise voltage within a range around the trip point of the comparator 520 does not reset the output of the comparator 520. This is accomplished by increasing (or decreasing) the reference voltage by a scaled amount that exceeds the noise level expected once the comparator 520 has made a first trip. Since the hysteresis is set by a resistor divider, it is insensitive to process or temperature variations, similar to the rest of the resistive network 502.

[0029] Level shifter circuit 500 produces both a positive level shifted output signal OutP and a negative level shifted output signal OutN based upon the single ended input signal. Level shifter circuit 500 can be turned off by applying a logic high signal to Off terminal, which turns on FET 514, shorting input InP to Vss (ground), bringing OutP low and OutN high.

[0030] FIG. 6 shows a resistive network 602 designed for a differential signal input, rather than the single-ended input of FIG. 5. In the differential input embodiment of FIG. 6, both input branches of resistive network 602 follow the topology of the In branch of FIG. 5. Thus, in FIG. 6, differential signal inputs InP and InM are each connected to a corresponding resistive voltage divider between Vdd and Vss. The voltage divider for positive input InP includes a resistor 604, a scale resistor 606, and an offset resistor 608 connected in series. Similarly, the voltage divider for input InM includes a resistor 624, a scale resistor 626, and an offset resistor 628 connected in series. Although not shown, the signals from the voltage divider, Pos and Neg, are connected, respectively, as inputs to the non-inverting and inverting terminals of a GaN differential comparator, similar to the connection of InP and Vtrip to GaN comparator 520 shown in FIG. 5. Also, similar to FET 514 of FIG. 5, FET 614 is provided to short Pos to Vss (ground), bringing OutP low and OutN high, if the input signal Off is set to a logic high. Although not shown, a hysteresis circuit, such as that depicted in FIG. 5 and described above, may be connected to the negative resistor branches to produce hysteresis for the corresponding logic translators.

[0031] The value of offset resistor 628 for the InM input is made slightly higher than the value of offset resistor 608 for the InP input to ensure that, if the input signals InP and InM are floating, the output stays low. The difference in the value of offset resistors 608 and 628 depends on the amount of maximum input offset expected at the GaN comparator to which voltage divider outputs Pos and Neg are connected. The values of the offset resistors 608 and 628 can also be set to allow for level-shifting of low-voltage differential signals (LVDS). A typical LVDS common-mode voltage is approximately 1.3V, which is well below threshold voltage V.sub.th values of GaN FETs.

[0032] FIG. 7 shows a resistive network-based logic-level shifter circuit of the present invention with a differential input similar to that of FIG. 6, but with series input resistors to accommodate large input signals. Specifically, logic-level shifter circuit 700 includes series resistors 716 and 718 at inputs InP and InM, respectively, to reduce large input signal voltages to lower levels. In FIG. 7, a hysteresis circuit, such as that depicted in FIG. 5, may be connected to the negative resistor branches to produce hysteresis for the corresponding logic translators. The logic-level shifter of FIG. 7, with resistive network 700, thus achieves both the input attenuation and level-shifting needed to interface with a GaN FET, while ensuring that the maximum input voltage swing does not damage the input GaN FET.

[0033] In summary, the present invention, in the various embodiments described above, advantageously provides a circuit topology that can be used as a single-ended or differential level shifting interface for GaN ICs that allows the ICs to be controlled with standard low-voltage CMOS-level inputs. The level shift circuitry of the present invention is based on a resistive network, and is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network of the level shifter of the present invention includes offset resistive circuitry, such that the inputs to a GaN comparator can be set to hover around the optimal bias point of the comparator. The circuitry of the present invention includes hysteresis, which is also set by a resistive circuit and is thus also independent of process and temperature variations. Input resistors can be provided to scale down high voltage input signals prevalent in older analog control systems to avoid damage to the input GaN FETs.

[0034] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.