NITRIDE BASED ULTRAVIOLET LIGHT EMITTING DIODE WITH AN ULTRAVIOLET TRANSPARENT CONTACT

Abstract

A nitride-based ultraviolet light emitting diode (UVLED) with an ultraviolet transparent contact (UVTC). The nitride-based UVLED is an alloy composition of (Ga, Al, In, B)N semiconductors, and the UVTC is composed of an oxide with a bandgap larger than that emitted in an active region of the nitride-based UVLED, wherein the oxide is an alloy composition of (Ga, Al, In, B, Mg, Fe, Si, Sn)O semiconductors, such as Ga.sub.2O.sub.3.

Claims

1. An optoelectronic device, comprising: a substrate, an n-type region formed on or above the substrate, an active region formed on or above the n-type region, a p-type region formed on or above the active region, and at least one ultraviolet transparent contact (UVTC) formed on or above the p-type region, wherein the active region emits ultraviolet (UV) light, and the n-type region, the p-type region and the ultraviolet transparent contact are transparent to the UV light.

2. The device of claim 1, wherein the first n-type region, active region, and p-type region, are comprised of Al.sub.xIn.sub.yGa.sub.1-x-yN, where 0x1, 0y1.

3. The device of claim 1, wherein the ultraviolet transparent contact is comprised of an alloy composition having a formula Ga.sub.nAl.sub.sIn.sub.tB.sub.uMg.sub.vFe.sub.wSi.sub.xSn.sub.yO.sub.z where:
0n1,0x1,0y1,0z1,and n+s+t+u+v+w+x+y+z=1.

4. The device of claim 3, wherein the ultraviolet transparent contact is comprised of an alpha, beta, gamma, delta, and epsilon phase of Ga.sub.2O.sub.3.

5. The device of claim 4, wherein the ultraviolet transparent contact is comprised of a (201), (001), or (010) crystal orientation of Ga.sub.2O.sub.3.

6. The device of claim 1, wherein the ultraviolet transparent contact is deposited by hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, atomic layer deposition (ALD), electron beam deposition (EBD), or other deposition technique, on or above the p-type region.

7. The device of claim 1, wherein the ultraviolet transparent contact is bonded on or above the p-type layer.

8. The device of claim 1, wherein the n-type region, the p-type region and the ultraviolet transparent contact each has a bandgap larger than the active region.

9. The device of claim 1, wherein the n-type region is a first n-type region, a second n-type region is formed on or above the p-type region, and the ultraviolet transparent contact is formed on or above the second n-type region, wherein the second n-type region is transparent to the UV light.

10. The device of claim 9, wherein the second n-type region forms a tunnel junction with the p-type region.

11. The device of claim 9, wherein the second n-type region has a larger bandgap than the active region.

12. The device of claim 9, wherein the ultraviolet transparent contact is at least partially etched in order to access the second n-type region, and at least a portion of the ultraviolet transparent contact is left intact and not etched

13. The device of claim 12, wherein the second n-type region is at least partially etched in order to access the p-type region.

14. The device of claim 9, wherein the second n-type region is comprised of Al.sub.xIn.sub.yGa.sub.1-x-yN, where 0x1, 0y1.

15. A method of fabricating an optoelectronic device, comprising: forming at least one first n-type region on a substrate; forming at least one active region on or above the n-type region; forming at least one p-type region on or above the active region; and forming at least one ultraviolet transparent contact (UVTC) on or above the p-type region; wherein the active region emits ultraviolet (UV) light, and the n-type region, the p-type region and the ultraviolet transparent contact are transparent to the UV light.

16. The method of claim 15, wherein the first n-type region, active region, and p-type region, are comprised of Al.sub.xIn.sub.yGa.sub.1-x-yN, where 0x1, 0y1.

17. The method of claim 15, wherein the ultraviolet transparent contact is comprised of an alloy composition having a formula Ga.sub.nAl.sub.sIn.sub.tB.sub.uMg.sub.vFe.sub.wSi.sub.xSn.sub.yO.sub.z where:
0n1,0x1,0y1,0z1,and n+s+t++u+v+w+x+y+z=1.

18. The method of claim 17, wherein the ultraviolet transparent contact is comprised of an alpha, beta, gamma, delta, and epsilon phase of Ga.sub.2O.sub.3.

19. The method of claim 18, wherein the ultraviolet transparent contact is comprised of a (201), (001), or (010) crystal orientation of Ga.sub.2O.sub.3.

20. The method of claim 15, wherein the ultraviolet transparent contact is bonded on or above the p-type layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Referring now to the drawings in which like reference numbers represent corresponding parts throughout.

[0026] FIG. 1A is a cross-sectional schematic of a first nitride-based semiconductor device of the present invention, comprising of a substrate, an n-type region, an active region, a p-type region, and a UVTC region, and FIG. 1B is an enlarged view of a portion of the active region of FIG. 1A.

[0027] FIG. 2A is a cross-sectional schematic of a second nitride-based semiconductor device of the present invention, comprising a substrate, a first n-type region, an active region, a p-type region, a second n-type region, and a UVTC region, and FIG. 2B is an enlarged view of a portion of the active region of FIG. 2A.

[0028] FIG. 3 is a flowchart that describes a method for fabricating an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0029] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0030] Overview

[0031] The present invention describes nitride-based light emitting device structures incorporating a UVTC region on or above a p-type region. The present invention also describes nitride-based light emitting device structures incorporating a tunnel junction comprised of a second n-type region on or above the p-type region, with a UVTC region on or above the second n-type region. The use of the UVTC region offers a means of improving nitride-based light emitting device performance by greatly enhancing device output power at a constant current.

TECHNICAL DESCRIPTION

First Embodiment

[0032] FIG. 1A is a schematic sectional view showing the structure of a first nitride-based semiconductor device (an LED device) according to a first embodiment of the present invention. This LED comprises a substrate 100; an n-type region 101 composed of Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1 and 0y1) doped with silicon; an active region 102 comprised of a multiple quantum well structure composed of Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1 and 0y1), which includes alternating layers of well regions 103A and barrier regions 103B as shown in the enlarged view of FIG. 1B; a p-type region 104 composed of Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1 and 0y1) doped with magnesium; a UVTC region 105 composed of Ga.sub.2O.sub.3; and electrodes 106 and 107.

[0033] The substrate 100 may contain some silicon, gallium, indium, germanium, oxygen, or aluminum. The substrate 100 may be oriented in various crystal orientations such as polar, semipolar, or nonpolar. Additionally, the substrate 100 may be a patterned substrate 100. The substrate 100 may be subsequently removed, so that the device can be flip-chip mounted to a carrier or other substrate. An exposed region resulting from the removing of the substrate 100 may be patterned. The carrier may be separated into singulated portions to form light emitting devices separated from one another, with each of the light emitting devices mounted to a respective portion of the carrier.

[0034] The III-nitride n-type region 101 has a larger bandgap than the active region 102. This allows for the n-type region 101 to not absorb any of the light emitted from the active region 102.

[0035] The III-nitride p-type region 104 also has a larger bandgap than the active region 102. This allows for the p-type region 104 to not absorb any of the light emitted from the active region 102.

[0036] In addition, the UVTC region 105 has a larger bandgap than the active region 102. This allows for the UVTC region 105 to not absorb any of the light emitted from the active region 102. The UVTC region 105 may be doped with tin or other dopants such as magnesium, boron, silicon, carbon, zinc, iron, or silicon.

Second Embodiment

[0037] FIG. 2A is a schematic sectional view showing the structure of a second nitride-based semiconductor device (an LED device) according to a second embodiment of the present invention. This LED is comprised of a substrate 100; a first n-type region 101 composed of Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1 and 0y1) doped with silicon; an active region 102 comprised of a multiple quantum well structure composed of Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1 and 0y1), which includes alternating layers of well regions 103A and barrier regions 103B as shown in the enlarged view of FIG. 2B; a p-type region 104 composed of Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1 and 0y1) doped with magnesium; a second n-type region 200 composed of Al.sub.xIn.sub.yGa.sub.1-x-yN (0x1 and 0y1); a UVTC region 105 composed of Ga.sub.2O.sub.3; and electrodes 106 and 107.

[0038] The substrate 100 may contain some silicon, gallium, indium, germanium, oxygen, or aluminum. The substrate 100 may be oriented in various crystal orientations such as polar, semipolar, or nonpolar. Additionally, the substrate 100 may be a patterned substrate 100. The substrate 100 may be subsequently removed, so that the device can be flip-chip mounted to a carrier or other substrate. An exposed region resulting from the removing of the substrate 100 may be patterned. The carrier may be separated into singulated portions to form light emitting devices separated from one another, with each of the light emitting devices mounted to a respective portion of the carrier.

[0039] In this embodiment, the second n-type region 200 forms a tunnel junction with the p-type region 104. In addition, the second n-type region 200 has a larger bandgap than the active region 102, which allows for the second n-type region 200 to not absorb any of the light emitted from the active region 102.

[0040] In this embodiment, a pattern can be formed by properly masking the second n-type region 200 with a periodic pattern comprised of stripes, circles, hexagons, or other patterns, such that subsequent deposited regions, such as the UVTC region 200, preferentially form on the unmasked regions of the second n-type region 200. Masking materials can be composed of silicon dioxide, for example.

[0041] The UVTC region 105 may be located on or above the second n-type region 200, wherein the second n-type region 200 is completely covered by the UVTC region 105. Further steps may then be performed, such as etching, in order to expose the second n-type region 200. These steps may include properly masking the UVTC region 105, followed by reactive ion etching (RIE) to remove a portion of the UVTC region 106 in order to expose the second n-type region 200. Further, the UVTC region 105 may be formed by etching periodic patterns into the UVTC region 105, which are comprised of stripes, circles, hexagons, or another pattern.

[0042] Process Steps

[0043] FIG. 3 is a flowchart that describes a method for fabricating an embodiment of the present invention.

[0044] In Block 300, the substrate 100 is loaded in a metal organic vapor phase epitaxy (MOVPE) reactor and cleaned. For example, a sapphire (Al.sub.2O.sub.3) substrate 100 is set in the MOVPE reactor and the temperature of the substrate 100 is increased to 1200 C. with hydrogen flow to clean the substrate 100. Instead of a sapphire substrate, the substrate 100 may be a patterned substrate or a substrate having its principal surface represented by an R-face or A-face, an insulating substrate of, for example, spinel (MgAl.sub.2O.sub.4), or a semiconductor substrate of, for example, silicon carbide (SiC) (including 6H, 4H, or 3C), silicon (Si), zinc oxide (ZnO), gallium arsenide (GaAs), gallium oxide (Ga.sub.2O.sub.3), or gallium nitride (GaN).

[0045] In Block 301, the temperature is increased to 1250 C. and a first buffer region made of aluminum nitride (AlN), which has a thickness of about 800 nm, is formed by growth on or above the substrate 100, using hydrogen as a carrier gas, and ammonia and trimethylaluminum (TMAl) as material gases. Such a buffer region may be omitted, depending on the kind of the substrate, the growing method, etc.

[0046] In Block 302, after growing the buffer region, only TMAl is stopped and the temperature is decreased to 1175 C., wherein the first n-type region 101, comprised of In.sub.xAl.sub.yGa.sub.1-x-yN, where 0x1, 0y1, is formed on or above the substrate 100. In one embodiment, the first n-type region 101, composed of Al.sub.xGa.sub.1-xN, where x=0.5, doped with silicon (Si) to 110.sup.19/cm.sup.3, and having a thickness of 300 nm, is grown using ammonia and TMAl as material gases in the same way as in the previous step, and disilane gas as an impurity gas. The composition is not specifically limited to that composition. In such a case, the II-nitride semiconductor region having a minimized crystal defect can easily be obtained.

[0047] The thickness of the n-type region 101 is not specifically limited to any thickness. Moreover, the n-type impurity may be desirably doped in with a high concentration to the degree that the crystal quality of the III-nitride semiconductor is not deteriorated and preferably in the concentration between 110.sup.18/cm.sup.3 and 510.sup.21/cm.sup.3.

[0048] Next, in Block 303, an active region 102, comprised of In.sub.xAl.sub.yGa.sub.1-x-yN, where 0x1, 0y1, is formed on or above the n-type region 101. In one embodiment, the active region 102, with a multiple quantum well structure having a total thickness of 30 nm, is grown by laminating alternately five barrier regions 103B and three well regions 103A in the order of barrier region 103B, well region 103A, barrier region 103B, etc., and finishing on a barrier region 103B. The quantum barrier regions 103B, composed of undoped Al.sub.xGa.sub.1-xN, with x=0.5, having a thickness of 8 nm, are grown at 1175 C., and the quantum well regions 103A, composed of undoped Al.sub.xGa.sub.1-xN, with x=0.6, having a thickness of 2.5 nm, are grown using trimethylgallium (TMG), TMAl and ammonia.

[0049] In this embodiment, the active region 102 is grown by laminating the barrier region 103B first, but may be grown by laminating the well region 103A first and also last or the order may begin with the barrier region 103B and end with the well region 103A. Thus, the order of depositing the barrier regions 103B and well regions 103A is not specifically limited to a particular order.

[0050] The well regions 103A are set to have a thickness of not greater than 10 nm, preferably not greater than 7 nm, and more preferably not greater than 5 nm. A thickness of greater than 10 nm may make it difficult to increase the output of the device. On the other hand, the barrier regions 103B are set to have a thickness of not greater than 30 nm, preferably not greater than 25 nm, and most preferably not greater than 20 nm.

[0051] Subsequently, in Block 304, the p-type region 104, comprised of In.sub.xAl.sub.yGa.sub.1-x-yN, where 0x1, 0y1, is formed on or above the active region 102. In one embodiment, the p-type region 104, composed of p-type Al.sub.xGa.sub.1-xN, with x=0.5, doped with Mg to 110.sup.20/cm.sup.3, is grown at 1075 C., using TMG, TMAl, ammonia, and Bis(cyclopentadienyl)magnesium (Cp.sub.2Mg), to a thickness of 100 nm. In such a case, a III-nitride semiconductor region having minimized crystal defects can be obtained.

[0052] Once the reactor has cooled, the epitaxial structure is removed and annealed in a hydrogen deficient atmosphere for 3 minutes at a temperature of 900 C. in order to activate the p-type region 104.

[0053] After annealing the p-type region 104, Block 305 is the optional step of forming the second n-type region 200, composed of In.sub.xAl.sub.yGaN (0x, 0y, x+y<1), on or above the p-type region 104. In one embodiment, the second n-type region 200 is grown in a manner similar to the first n-type region 101 and has a similar composition. Like the first n-type region 101, the second n-type region 200 may not be specifically limited to that composition. In one embodiment, the second n-type region 200 forms a tunnel junction with the p-type region 104.

[0054] Subsequently, in Block 306, the epitaxial structure is loaded into a bonding system along with the UVTC material, and the UVTC region 105 is formed on or above either the p-type region 104 or the second n-type region 200, wherein the temperature of the epitaxial structure and the UVTC material is heated to 700 C., so as to bond the UVTC region 105 into contact with either the p-type region 104 or the second n-type region 200. Once the bonding system has cooled, the resulting structure is removed.

[0055] In one embodiment, the UVTC material is comprised of an alloy composition of the (Ga, Al, In, B, Mg, Fe, Si, Sn)O semiconductors having the formula Ga.sub.nAl.sub.sIn.sub.rB.sub.uMg.sub.vFe.sub.wSi.sub.xSn.sub.yO.sub.z where:

0n1,0s1,0t1,0u1,0v1,0w1,0x1,0y1, 0z1, and n+s+t+u+v+w+x+y+z=1

[0056] The UVTC material may comprise one or multiple layers or regions having varying or graded (Ga, Al, In, B, Mg, Fe, Si, Sn)O compositions, or one or more layers or regions of similar (Al, Ga, In, B, Mg, Fe, Si, Sn)O compositions, or a heterostructure comprising layers or regions of dissimilar (Ga, Al, In, B, Mg, Fe, Si, Sn)O compositions.

[0057] In one embodiment, the UVTC material may be composed of Ga.sub.2O.sub.3, as well as different structures and/or phases of Ga.sub.2O.sub.3, such as an alpha, beta, gamma, delta, and epsilon phase of Ga.sub.2O.sub.3. Further, the UVTC material may be comprised of a (201), (001), or (010) crystal orientation of Ga.sub.2O.sub.3.

[0058] The UVTC material may be deposited by hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, atomic layer deposition (ALD), electron beam deposition (EBD), or another deposition technique, on or above the p-type region 104 or the second n-type region 200.

[0059] In one embodiment, the n-type region 101, the p-type region 103, the second n-type region 200, and the UVTC region 105 are all transparent to the UV light emitted from the active region 104. Moreover, the n-type region 101, the p-type region 103, the second n-type region 200, and the UVTC region 105, each has a bandgap larger than the active region 104.

[0060] Subsequently, in Block 307, an etch is performed on the regions 101, 102, 103, 104, 105, and 200, in order to expose the n-type region 101. The UVTC region 105 is at least partially etched in order to access the second n-type region 200, wherein at least a portion of the UVTC region 105 is left intact and not etched. In addition, the second n-type region 200 may be at least partially etched in order to access the p-type region 103. This etch can be performed preferably by known methods of mesa etching or by mechanical sawing, laser cutting, and water-jet cutting.

[0061] In Block 308, electrodes 106 and 107 are then deposited, wherein the electrodes 106 and 107 can be composed of metals such as gold, nickel, titanium, aluminum, or silver, or a combination thereof.

[0062] In Block 309, the structure can then be divided into individual devices on the substrate 100, preferably by known methods of mesa etching or by mechanical sawing, laser cutting, and water-jet cutting, all of which cut through the deposited layers while not cutting through the substrate 100. The individual devices can have different sizes with the suitable range of sizes being 250-300 microns square. In alternative embodiments according to the present invention, the regions 101, 102, 103, 104, 105, and 200 can be left on the substrate 100 as continuous layers, and then divided into individual devices.

[0063] In addition, the substrate 100 with its devices can be inverted and flip-chip mounted on a lateral surface of a carrier, and in a preferred embodiment, the devices are bonded in place. The carrier can then be singulated into portions to form light emitting devices separated from one another, with each of the light emitting devices mounted to a respective portion of the carrier.

[0064] Subsequently, in Block 310, the substrate 100 can then be removed, wherein the n-type region 101 is exposed by removing the substrate 100 and subsequently can be patterned. The patterns can be comprised of circles, stripes, hexagons, or other patterns.

[0065] Finally, Block 311 represents the resulting device(s).

CONCLUSION

[0066] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.