Electronic circuit and electronic apparatus

Abstract

an electronic circuit according to an embodiment includes: a generation circuit generating a first clocksignal and a second clocksignal delayed from the first clocksignal; a first coupler transmitting one of the first and the second clocksignals by electromagnetic coupling; a first converter driven by the transmitted clocksignal and converting a first input signal into a first signal of a frequency corresponding to the transmitted clocksignal; a second coupler transmitting the first signal by electromagnetic coupling; a second converter converting the first signal into a second signal of a frequency corresponding to the first input signal with the other of the first and the second clocksignals; an output device outputting the second signal; and a protection circuit connected to a line through which the one of the first and the second clocksignals is transmitted between the first coupler and the first converter.

Claims

1. An electronic circuit comprising: a generation circuit configured to generate a first clock signal and a second clock signal delayed from the first clock signal; a first electromagnetic field coupler configured to transmit one of the first clock signal and the second clock signal by electromagnetic field coupling; a first frequency converter driven by the one of the first clock signal and the second clock signal, and configured to convert a first input signal into a first signal of a frequency corresponding to one of the first clock signal and the second clock signal; a second electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second frequency converter configured to convert the first signal into a second signal of a frequency corresponding to the first input signal, by using the other of the first clock signal and the second clock signal; an output terminal configured to output the second signal; and a first protection circuit connected to a first line through which the one of the first clock signal and the second clock signal is transmitted between the first electromagnetic field coupler and the first frequency converter.

2. The electronic circuit according to claim 1, wherein the first protection circuit operates based on at least one of variation of an intermediate potential of the first input signal and variation of a reference potential of the electronic circuit.

3. The electronic circuit according to claim 2, wherein the first protection circuit does not operate by variation of a voltage of the first clock signal, variation of a voltage of the second clock signal, and variation of a differential voltage of the first input signal.

4. The electronic circuit according to claim 1, wherein the first protection circuit includes a first transistor and a second transistor connected in parallel with the first transistor, the first transistor including a first gate terminal and a first drain terminal connected to each other, the second transistor including a second gate terminal and a first source terminal connected to each other.

5. The electronic circuit according to claim 4, wherein the first protection circuit further includes a third transistor connected in series with the first transistor, and a fourth transistor connected in series with the second transistor, the third transistor including a third gate terminal and a second drain terminal connected to each other, the fourth transistor including a fourth gate terminal and a second source terminal connected to each other.

6. The electronic circuit according to claim 1, wherein the first protection circuit includes a first transistor and a second transistor, the first transistor including a first gate terminal and a first drain terminal, the second transistor including a second gate terminal connected to the first drain terminal, and a second drain terminal connected to the first gate terminal.

7. The electronic circuit according to claim 6, wherein the first protection circuit further includes a third transistor connected in series with the first transistor, and a fourth transistor connected in series with the second transistor, the third transistor including a third gate terminal connected to the first gate terminal and the second drain terminal, the fourth transistor including a fourth gate terminal connected to the second gate terminal and the first drain terminal.

8. The electronic circuit according to claim 1, further comprising a second protection circuit connected to a second line through which the first signal is transmitted between the first frequency converter and the second electromagnetic field coupler.

9. The electronic circuit according to claim 1, further comprising: an input terminal receiving the first input signal; and a third protection circuit connected to a third line through which the first input signal is transmitted between the input terminal and the first frequency converter.

10. The electronic circuit according to claim 1, further comprising a control circuit configured to determine a delay amount of the first clock signal based on an amplitude of the second signal.

11. The electronic circuit according to claim 10, wherein the control circuit determines the delay amount of the first clock signal based on a maximum value of the amplitude of the second signal.

12. The electronic circuit according to claim 1, wherein each of the first electromagnetic field coupler and the second electromagnetic field coupler includes at least one of a capacitor and a transformer, and each of the first electromagnetic field coupler and the second electromagnetic field coupler performs electromagnetic field coupling through an isolation barrier electrically isolated.

13. The electronic circuit according to claim 1, wherein the electronic circuit includes a first chip and a second chip, the first chip includes the first electromagnetic field coupler, the second electromagnetic field coupler, and the first frequency converter, and the second chip includes the second frequency converter.

14. The electronic circuit according to claim 1, wherein the electronic circuit includes at least a first chip and a second chip, the first chip includes the first electromagnetic field coupler, the second electromagnetic field coupler, and the second frequency converter, and the second chip includes the first frequency converter.

15. The electronic circuit according to claim 1, further comprising: a third electromagnetic field coupler connected to the first electromagnetic field coupler and configured to transmit the one of the first clock signal and the second clock signal by electromagnetic field coupling; and a fourth electromagnetic field coupler connected to the second electromagnetic field coupler and configured to transmit the first signal by electromagnetic field coupling, wherein the electronic circuit includes at least a first chip and a second chip, the first chip includes the first electromagnetic field coupler and the second electromagnetic field coupler, and the second chip includes the third electromagnetic field coupler and the fourth electromagnetic field coupler.

16. An electronic apparatus comprising: the electronic circuit according to claim 1; and a first resistor configured to convert an input current or an output current of an electronic apparatus or an electric apparatus into a voltage, wherein the input signal includes a first voltage signal representing a voltage at a first end of the first resistor and a second voltage signal representing a voltage at a second end of the first resistor, and the second signal includes a signal representing the input current or the output current.

17. An electronic apparatus comprising: the electronic circuit according to claim 1; and a second resistor and a third resistor configured to divide an input voltage of an electronic apparatus or an electric apparatus, wherein the input signal includes a third voltage signal representing a voltage at a first end of the third resistor connected to the second resistor and a fourth voltage signal representing a voltage at a second end of the third resistor, and the second signal includes a signal representing the input voltage.

18. An electronic apparatus comprising: the electronic apparatus according to claim 16, configured to measure the input current; the electronic apparatus according to claim 17; a switching device configured to generate a direct current; a gate driver configured to generate a current supplied to the switching device; and a controller configured to determine the current generated by the gate driver based on a signal representing a value of the input current and a signal representing a value of the input voltage.

19. An electronic apparatus comprising: a plurality of the electronic apparatus according to claim 16, each configured to measure the output current; the electronic apparatus according to claim 17; a plurality of switching devices configured to generate the output current; a plurality of gate drivers provided corresponding to the plurality of switching devices and each configured to generate a current supplied to the corresponding switching device; and a controller configured to determine the output currents generated by the respective gate drivers based on a signal representing a value of the output current and a signal representing a value of the input voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a configuration diagram of an electronic circuit 100 according to a first embodiment;

(2) FIG. 2 is a diagram illustrating detail of the electronic circuit 100;

(3) FIG. 3 is a configuration diagram of an electronic circuit 10 according to a comparative example;

(4) FIG. 4 is a diagram illustrating variation of a potential V.sub.CLKA1 based on a slew rate of an input common mode potential V.sub.CM in the electronic circuit 10 and the electronic circuit 100;

(5) FIG. 5 is a configuration diagram of an electronic circuit 100 applicable to the first embodiment;

(6) FIG. 6 is a configuration diagram of an electronic circuit 100 applicable to the first embodiment;

(7) FIGS. 7A to 7C are diagrams illustrating various configurations of protection circuits 170a and 170b;

(8) FIGS. 8A to 8C are diagrams each illustrating an example in which the circuits in FIGS. 7A to 7C are connected in multiple stages;

(9) FIG. 9 is a configuration diagram of an electronic circuit 180 applicable to the first embodiment;

(10) FIG. 10 is a configuration diagram of an electronic circuit 180 applicable to the first embodiment;

(11) FIG. 11 is a configuration diagram of an electronic circuit 100T applicable to the first embodiment;

(12) FIG. 12 is a configuration diagram of an electronic circuit 100A applicable to the first embodiment;

(13) FIG. 13 is a configuration diagram of an electronic circuit 100B applicable to the first embodiment;

(14) FIG. 14 is a configuration diagram of an electronic circuit 100C applicable to the first embodiment;

(15) FIG. 15 is a configuration diagram of an electronic circuit 100D applicable to the first embodiment;

(16) FIG. 16 is a configuration diagram of a power converter 200 according to a second embodiment; and

(17) FIG. 17 is a configuration diagram of an inverter 300 according to a third embodiment.

DETAILED DESCRIPTION

(18) Issues to be solved by embodiments of the present invention are to provide an electronic circuit and an electronic apparatus each adaptive to variation of a potential of an input signal and a reference potential.

(19) To solve the above-described issues, an electronic circuit according to an embodiment includes: a generation circuit configured to generate a first clock signal and a second clock signal delayed from the first clock signal; a first electromagnetic field coupler configured to transmit one of the first clock signal and the second clock signal by electromagnetic field coupling; a first frequency converter driven by the one of the first clock signal and the second clock signal, and configured to convert a first input signal into a first signal of a frequency corresponding to one of the first clock signal and the second clock signal; a second electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second frequency converter configured to convert the first signal into a second signal of a frequency corresponding to the first input signal, by using the other of the first clock signal and the second clock signal; an output device configured to output the second signal; and a first protection circuit connected to a first line through which the one of the first clock signal and the second clock signal is transmitted between the first electromagnetic field coupler and the first frequency converter.

(20) Some embodiments of the present invention are described below with reference to drawings. The disclosure is merely illustrative, and the invention is not limited by contents described in the following embodiments. Modifications easily conceivable by those skilled in the art are included in the scope of the disclosure as a matter of course. To make the description clearer, sizes, shapes, and the like of parts may be changed from those in actual implementation and schematically illustrated in drawings. In the plurality of drawings, corresponding elements are denoted by the same reference numerals, and detailed descriptions of the corresponding elements may be omitted.

First Embodiment

(21) FIG. 1 is a configuration diagram of an electronic circuit 100 according to a first embodiment. The electronic circuit 100 includes an isolation barrier 101 (illustrated as Isolation Barrier in drawing), and transmits an analog signal through the isolation barrier 101. The electronic circuit 100 is also referred to as an isolation amplifier. In the drawing, the electronic circuit 100 is illustrated as Isolation Amplifier.

(22) In the electronic circuit 100, an input side including input terminals INA and INB and an output side including output terminals OUTP and OUTN are electrically isolated from each other by the isolation barrier 101. The electronic circuit 100 includes, on the input side, a modulation circuit 130 (illustrated as Modulation Circuit in drawing), ESD (Electro-Static Discharge) circuits 160a and 160b, protection circuits 170a and 170b, and a part of each of electromagnetic field couplers 120 and 140. The electronic circuit 100 includes, on the output side, a control circuit 110 (illustrated as Control Circuit in drawing), a de-modulation circuit 150 (illustrated as De-modulation Circuit in drawing), ESD circuits 160c, 160d, and 160e, and a part of each of the electromagnetic field couplers 120 and 140. Further, the input side and the output side are electromagnetic-field coupled by the electromagnetic field coupler 120 and the electromagnetic field coupler 140.

(23) Electric isolation is not limited to complete isolation, and it is sufficient to block electricity at a degree regarded as isolation. In the electronic circuit 100, power is supplied to the output side from a power supply VDD2, whereas power is not supplied to the input side. In other words, the control circuit 110 and the de-modulation circuit 150 are driven by receiving power from the power supply VDD2, whereas the modulation circuit 130 is driven without receiving power. Further, in the electronic circuit 100, the input side and the output side may be different in reference potential because of electric isolation. In this example, the reference potential on the input side is referred to as a reference potential GND1, and the reference potential on the output side is referred to as a reference potential GND2.

(24) Note that the modulation circuit 130 is also referred to as a frequency converter 130 (illustrated as Passive Mixer in drawing).

(25) The control circuit 110 includes a logic circuit 111 (illustrated as Logic in drawing) and a clock circuit 112 (illustrated as Clock Circuit in drawing).

(26) The logic circuit 111 is a circuit transmitting an instruction to each of components of the electronic circuit 100. For example, the logic circuit 111 instructs the clock circuit 112 to generate clock signals CLKA0 and CLKB0, and instructs a frequency to be filtered to a filter circuit 153. The logic circuit 111 determines delay amounts of clock signals CLKA2 and CLKB2 based on amplitudes of signals de-modulated by the de-modulation circuit 150 described below. More specifically, the logic circuit 111 determines the delay amounts of the clock signals CLKA2 and CLKB2 based on the maximum values of the amplitudes of the signals de-modulated by the de-modulation circuit 150. The logic circuit 111 instructs the clock circuit 112 to generate the clock signal CLKA2 that is obtained by delaying a phase of the clock signal CLKA0 by the determined delay amount and the clock signal CLKB2 that is obtained by delaying a phase of the clock signal CLKB0 by the determined delay amount.

(27) The clock circuit 112 generates the clock signals CLKA0 and CLKB0 and the clock signals CLKA2 and CLKB2 that are delayed in phase by the determined delay amounts, in response to the instruction from the logic circuit 111. The clock signal CLKA0 is transmitted to the electromagnetic field coupler 120 through a line L.sub.CLKA0, and the clock signal CLKB0 is transmitted to the electromagnetic field coupler 120 through a line L.sub.CLKB0. The clock signals CLKA2 and CLKB2 delayed by the determined delay amounts are transmitted to a frequency converter 151 of the de-modulation circuit 150, and are used for de-modulation of signals.

(28) The electromagnetic field coupler 120 is electromagnetic-field coupled through the isolation barrier 101, and transmits the clock signals CLKA0 and CLKB0 transmitted from the clock circuit 112 to the input side by the electromagnetic field coupling. The clock signals CLKA0 and CLKB0 are shifted in phase in a process of being transmitted by the electromagnetic field coupler 120, and become clock signals CLKA1 and CLKB1. The clock signal CLKA1 is transmitted to the frequency converter 130 through a line L.sub.CLKA1, and the clock signal CLKB1 is transmitted to the frequency converter 130 through a line L.sub.CLKB1. The electromagnetic field coupler 120 is realized by, for example, capacitors or transformers facing each other, and the isolation barrier 101 is positioned between the capacitors or the transformers facing each other.

(29) An analog signal is input to each of the input terminals INA and INB. In the following, the analog signal input to the input terminal INA is also referred to as an input signal S.sub.INA, and the analog signal input to the input terminal INB is also referred to as an input signal S.sub.INB. The input signal S.sub.INA is transmitted to the frequency converter 130 through a line L.sub.A0, and the input signal S.sub.INB is transmitted to the frequency converter 130 through a line L.sub.B0.

(30) The frequency converter 130 is driven by the clock signals CLKA1 and CLKB1 transmitted from the electromagnetic field coupler 120, converts frequencies of the input signals S.sub.INA and S.sub.INB to generate high-frequency signals S.sub.A1 and S.sub.B1. The frequency converter 130 converts the input signal S.sub.INA into the high-frequency signal S.sub.A1, and converts the input signal S.sub.INB into the high-frequency signal S.sub.B1. Since the frequency converter 130 is driven by the clock signals CLKA1 and CLKB1, the frequency converter 130 does not receive supply of power. Such a frequency converter is also referred to as a passive mixer. The high-frequency signal S.sub.A1 is transmitted to the electromagnetic field coupler 140 through a line L.sub.A1, and the high-frequency signal S.sub.B1 is transmitted to the electromagnetic field coupler 140 through a line L.sub.B1.

(31) The electromagnetic field coupler 140 is electromagnetic-field coupled through the isolation barrier 101, and transmits the high-frequency signals S.sub.A1 and S.sub.B1 transmitted from the frequency converter 130 by the electromagnetic field coupling. The high-frequency signals S.sub.A1 and S.sub.B1 are shifted in phase in a process of being transmitted by the electromagnetic field coupler 140, and become high-frequency signals S.sub.A2 and S.sub.B2. The high-frequency signal S.sub.A2 is transmitted to the de-modulation circuit 150 through a line L.sub.A2, and the high-frequency signal S.sub.B2 is transmitted to the de-modulation circuit 150 through a line L.sub.B2. The electromagnetic field coupler 140 is realized by, for example, capacitors or transformers facing each other, and the isolation barrier 101 is positioned between the capacitors or the transformers facing each other.

(32) The de-modulation circuit 150 includes the frequency converter 151 (illustrated as Mixer in drawing), an amplifier 152 (illustrated as Amp. in drawing), a filter circuit 153 (illustrated as LPF in drawing), and a buffer circuit 154 (illustrated as Buffer in drawing).

(33) The frequency converter 151 de-modulates the high-frequency signals S.sub.A2 and S.sub.B2 by using the clock signals CLKA2 and CLKB2 transmitted from the clock circuit 112, to generate restoration signals S.sub.A3 and S.sub.B3. The restoration signals S.sub.A3 and S.sub.B3 are analog signals, frequencies of which are respectively restored to frequencies equivalent to the frequencies of the input signals S.sub.INA and S.sub.INB. The amplifier 152 amplifies the restoration signals S.sub.A3 and S.sub.B3 transmitted from the frequency converter 151, and outputs the amplified signals. The filter circuit 153 performs filtering on the restoration signals S.sub.A3 and S.sub.B3 transmitted from the amplifier 152. In the present embodiment, as an example, the filter circuit 153 is a low-pass filter. The buffer circuit 154 adjusts signals transmitted from the filter circuit 153.

(34) The restoration signal S.sub.A3 is output from the output terminal OUTP through a line L.sub.A3, and the restoration signal S.sub.B3 is output from the output terminal OUTN through a line L.sub.B3. Further, the restoration signals S.sub.A3 and S.sub.B3 are also transmitted to the logic circuit 111. The restoration signals S.sub.A3 and S.sub.B3 are used in the logic circuit 111 to determine delay amounts of the clock signals CLKA0 and CLKB0. More specifically, since the high-frequency signals S.sub.A2 and S.sub.B2 as the origins of the restoration signals S.sub.A3 and S.sub.B3 each include phase shift, amplitudes of the restoration signals S.sub.A3 and S.sub.B3 may be decreased depending on the delay amounts added to the clock signals CLKA2 and CLKB2. The logic circuit 111 determines the delay amounts not decreasing the amplitudes (correcting phase shift of high-frequency signals S.sub.A2 and S.sub.B2) based on the maximum values of the amplitudes of the restoration signals S.sub.A3 and S.sub.B3.

(35) The ESD circuits 160a to 160e are circuits protecting the internal circuit of the electronic circuit 100 from voltage variation of static electricity or the like. The ESD circuit 160a is connected to the line L.sub.A0 and the reference potential GND1. The ESD circuit 160b is connected to the line L.sub.B0 and the reference potential GND1. The ESD circuit 160c is connected to the line L.sub.A3, the power supply VDD2, and the reference potential GND2. The ESD circuit 160d is connected to the line L.sub.B3, the power supply VDD2, and the reference potential GND2. The ESD circuit 160e is connected to the power supply VDD2 and the reference potential GND2. Although the detail is described below, on the input side not receiving supply of power in the electronic circuit 100, the internal circuit of the electronic circuit 100 may not be protected from variation of the voltages of the input signals S.sub.INA and S.sub.INB and the reference potential GND1.

(36) The protection circuits 170a and 170b are circuits protecting the internal circuit on the input side of the electronic circuit 100 from voltage variation. The protection circuit 170a is connected to the line L.sub.CLKA1 that connects the electromagnetic field coupler 120 and the frequency converter 130, and the reference potential GND1. The protection circuit 170b is connected to the line L.sub.CLKB1 that connects the electromagnetic field coupler 120 and the frequency converter 130, and the reference potential GND1. Although the detail is described below, the protection circuits 170a and 170b can protect the internal circuit of the electronic circuit 100 even from variation of the voltages of the input signals S.sub.INA and S.sub.INB and the reference potential GND1 that may not be protected by the ESD circuits 160a and 160b.

(37) The configuration of the electronic circuit 100 has been described above. The electronic circuit 100 may be implemented by an IC (Integrated Circuit) or an LSI (Large Scale Integration). The electronic circuit 100 may be collectively implemented on one chip or a part of the electronic circuit 100 may be implemented on a different chip. Further, the function of the control circuit 110 may be realized by a processing device such as a processor.

(38) In the following, the electromagnetic field couplers 120 and 140, the frequency converter 130, and the protection circuits 170a and 170b according to the present embodiment are described in detail. FIG. 2 is a detailed diagram of the electronic circuit 100 including the details of the electromagnetic field couplers 120 and 140, the frequency converter 130, and the protection circuits 170a and 170b. In FIG. 2, illustration of the ESD circuits 160a to 160e illustrated in FIG. 1 is omitted.

(39) In the present embodiment, the electromagnetic field couplers 120 and 140 each include capacitors. The electromagnetic field coupler 120 includes capacitors C.sub.CLK1 and C.sub.CLK2, and the electromagnetic field coupler 140 includes capacitors C.sub.SIG1 and C.sub.SIG2. The capacitors C.sub.CLK1, C.sub.CLK2, C.sub.SIG1, and C.sub.SIG2 each perform electromagnetic field coupling. One of flat plates of the capacitor C.sub.CLK1 is connected to the line L.sub.CLKA0, and the other flat plate is connected to the line L.sub.CLKA1. One of flat plates of the capacitor C.sub.CLK2 is connected to the line L.sub.CLKB0, and the other flat plate is connected to the line L.sub.CLKB1. One of flat plates of the capacitor C.sub.SIG1 is connected to the line L.sub.A1, and the other flat plate is connected to the line L.sub.A2. One of flat plates of the capacitor C.sub.SIG2 is connected to the line L.sub.B1, and the other flat plate is connected to the line L.sub.B2. The isolation barrier 101 is positioned between the flat plates of each of the capacitors. In the present embodiment, the capacitors are used as each of the electromagnetic field couplers 120 and 140; however, at least one capacitor may be replaced with a transformer.

(40) In the present embodiment, the frequency converter 130 includes four NMOS transistors M.sub.1, M.sub.2, M.sub.3, and M.sub.4 (hereinafter, also simply referred to as transistors M.sub.1, M.sub.2, M.sub.3, and M.sub.4). Each of the transistors M.sub.1 and M.sub.2 is driven when the clock signal CLKB1 transmitted through the line L.sub.CLKB1 is input to a gate terminal. Each of the transistors M.sub.3 and M.sub.4 is driven when the clock signal CLKA1 transmitted through the line L.sub.CLKA1 is input to a gate terminal. When the transistors M.sub.1 to M.sub.4 are driven, the input signals S.sub.INA and S.sub.INB are converted into the high-frequency signals S.sub.A1 and S.sub.B1.

(41) Each of the protection circuits 170a and 170b includes a plurality of diodes that are connected in parallel and are different in a current flowing direction. For example, the protection circuit 170a includes diodes D.sub.1a and D.sub.2a, and the protection circuit 170b includes diodes D.sub.1b and D.sub.2b. The diodes D.sub.1a and D.sub.2a are connected to the line L.sub.CLKA1 and the reference potential GND1. The diodes D.sub.1b and D.sub.2b are connected to the line L.sub.CLKB1 and the reference potential GND1. When variation of the voltages of the input signals S.sub.INA and S.sub.INB and the reference potential GND1 becomes equal to or more than a predetermined prescribed value, these diodes are turned on, and move electric charges between the lines L.sub.CLKA1 and L.sub.CLKB1 and the reference potential GND1, thereby suppressing potential difference between the lines L.sub.CLKA1 and L.sub.CLKB1 and the reference potential GND1 within a range not destroying the internal circuit of the electronic circuit 100.

(42) Note that, in the present embodiment, the lines L.sub.CLKA1 and L.sub.CLKB1 are connected through resistors R.sub.1 and R.sub.2 that are connected in series. The reference potential GND1 is connected between the resistors R.sub.1 and R.sub.2. As a result, operation points of the lines L.sub.CLKA1 and L.sub.CLKB1 are based on the reference potential GND1.

(43) The detail of the electronic circuit 100 has been described above. In the following, a case where the voltages of the input signals S.sub.INA and S.sub.INB and the reference potential GND1 are varied in each of a case where the protection circuits 170a and 170b are provided and a case where the protection circuits 170a and 170b are not provided is described. For description, FIG. 3 illustrates an electronic circuit 10 not including the protection circuits 170a and 170b, as a comparative example of the electronic circuit 100. A configuration of the electronic circuit 10 is the same as the configuration of the electronic circuit 100 except that the electronic circuit 10 does not include the protection circuits 170a and 170b. Therefore, components of the electronic circuit 10 are denoted by the same reference numerals as the components of the electronic circuit 100, and descriptions of such components are omitted.

(44) FIG. 4 illustrates cases where variation of the voltages of the input signals S.sub.INA and S.sub.INB and the reference potential GND1 is large and small in each of the electronic circuits 10 and 100. To simplify the description, it is assumed that the input terminals INA and INB and the reference potential GND1 are short-circuited or are connected through a resistor having a sufficiently small resistance value (for example, resistor having resistance value of 1 or less), outside each of the electronic circuits 10 and 100. In the following, the potential of the input terminal INA is referred to as a potential V.sub.INA, the potential of the input terminal INB is referred to as a potential V.sub.INB, a potential of the reference potential GND1 is referred to as a reference potential V.sub.GND1, a potential of the line L.sub.CLKA1 is referred to as a potential V.sub.CLKA1, and a potential of the line L.sub.CLKB1 is referred to as a potential V.sub.CLKB1. For description, an intermediate potential of the input terminals INA and INB is referred to as an input common mode potential V.sub.CM. In other words, the input common mode potential V.sub.CM, the potential V.sub.INA, and the potential V.sub.INB have relationship of an expression (1).

(45) [Expression 1]

(46) Further, in this case, the potential difference between each of the input terminals INA and INB and the reference potential GND1 is sufficiently small. This is expressed by an expression (2)

(47) [Expression 2]

(48) The expression (2) represents that, in a case where the potentials V.sub.INA and V.sub.INB and the reference potential V.sub.GND1 are varied, the input common mode potential V.sub.CM is also varied. In the following, the case where the input common mode potential V.sub.CM is varied indicates the case where at least any of the potentials V.sub.INA and V.sub.INB and the reference potential V.sub.GND1 is varied.

(49) In the present embodiment, as an example, the potential V.sub.CLKA1 in the case where the input common mode potential V.sub.CM is varied is described. The line L.sub.CLKA1 has a capacitance based on a parasitic capacitance of the line L.sub.CLKA1 itself, and a capacitance of the capacitor C.sub.CLK1 and an input capacitance of the frequency converter 130 connected to the line L.sub.CLKA1. Hereinafter, the capacitance is also referred to as a capacitance C.sub.1. The line L.sub.CLKA1 is connected to the reference potential GND1 through the resistor R.sub.1. Therefore, in the case where the input common mode potential V.sub.CM is varied, the electric charges move between the capacitance C.sub.1 and the reference potential GND1. As a result, in the case where the input common mode potential V.sub.CM is varied, the potential V.sub.CLKA1 is also varied following variation of the input common mode potential V.sub.CM. Further, since the line L.sub.CLKA1 and the reference potential GND1 are connected through the resistor R.sub.1, a low-pass filter is formed between the line L.sub.CLKA1 and the reference potential GND1. The low-pass filter limits variation speed of the potential V.sub.CLKA1 (hereinafter, variation speed of potential is also referred to as slew rate). At this time, as expressed in an expression (3), a difference between the input common mode potential V.sub.CM and the potential V.sub.CLKA1 is defined as a potential difference V.

(50) [Expression 3]

(51) As an example of the present embodiment, when the potential difference V is 5 V, an upper limit of the variation speed of the potential V.sub.CLKA1 is expressed by an expression (4) with the capacitance C.sub.1 (capacitance value is also referred to as C.sub.1 and is, for example, 100 fF), the resistor R.sub.1 (resistance value is also referred to as R.sub.1 and is, for example, 100 k), and the potential difference V.

(52) [Expression 4]

(53) In other words, in the present embodiment, in the case where the protection circuit 170a is not provided, the potential V.sub.LCKA1 can be varied following the input common mode potential V.sub.CM when the slew rate of the input common mode potential V.sub.CM is up to 500 V/s. Therefore, as illustrated in an upper part of FIG. 4, in the case where the slew rate of the input common mode potential V.sub.CM is relatively low (for example, 50 V/s), the potential V.sub.CLKA1 in each of the electronic circuits 10 and 100 is varied following the input common mode potential V.sub.CM, and the potential difference V maintains a certain level.

(54) In contrast, in a case where the slew rate of the input common mode potential V.sub.CM exceeds 500 V/s, the potential V.sub.CLKA1 cannot be varied following variation of the input common mode potential V.sub.CM in the electronic circuit 10. For example, in a case where the slew rate of the input common mode potential V.sub.CM is high (for example, 50 kV/s) as illustrated in a lower part in FIG. 4, movement of the electric charges between the capacitor C.sub.1 and the reference potential GND1 cannot catch up with variation of the input common mode potential V.sub.CM, and variation of the potential V.sub.CLKA1 is delayed. In this case, the potential difference V does not maintain the certain level and is increased, and the internal circuit on the input side of the electronic circuit 100 may be destroyed by the large potential difference V. For example, the transistors included in the frequency converter 130 may be destroyed. In a case of the circuit receiving supply of power, the electric charges can move through the ESD circuit connected to the power supply, which makes it possible to prevent the internal circuit from being destroyed by the potential difference V. However, since the input side in the present embodiment does not receive supply of power, the above-described issue occurs. Further, in the present embodiment, the line L.sub.CLKA1 is connected to the gate terminal of each of the transistors M.sub.3 and M.sub.4, and the line L.sub.CLKB1 is connected to the gate terminal of each of the transistors M.sub.1 and M.sub.2. Movement of the electric charges between the line L.sub.CLKA1 and the reference potential GND1 through the gate terminals of the transistors M.sub.1 to M.sub.4 hardly occurs. This causes the above-described issue.

(55) In contrast, in the electronic circuit 100, when the potential difference V exceeds a predetermined specific value, the protection circuit 170a is turned on. In the example of FIG. 4, the diode D.sub.1a is turned on to charge the electric charges to the capacitance C.sub.1. Charge of the electric charges through the diode D.sub.1a is less influenced by the low-pass filter of the resistor R.sub.1. Therefore, as compared with the case where the charge is performed through the resistor R.sub.1, the electric charges can move at high speed. Even in the case where the slew rate of the input common mode potential V.sub.CM is high, the potential V.sub.CLKA1 can be varied following variation of the input common mode potential V.sub.CM by virtue of the protection circuit 170a, and the potential difference V maintains the certain level. As a result, even in the case where the potentials of the input signals S.sub.INA and S.sub.INB and the reference potential GND1 are steeply varied, it is possible to protect the internal circuit of the electronic circuit 100. Even in the case where the potentials of the input signals S.sub.INA and S.sub.INB and the reference potential GND1 are steeply varied, the electronic circuit 100 can output the input signals S.sub.INA and S.sub.INB as the restoration signals S.sub.A3 and S.sub.B3. In other words, the electronic circuit 100 can have high CMTI (Common Mode Transient Immunity) characteristics.

(56) Although, in the example of FIG. 4, the diode D.sub.1a is turned on to charge the electric charges to the capacitance C.sub.1, in a case where inclination of the input common mode potential V.sub.CM is negative, a diode D.sub.2a is turned on to discharge the electric charges from the capacitance C.sub.1.

(57) As an example of the present embodiment, the potential V.sub.CLKA1 in the case where the input common mode potential V.sub.CM is varied has been described. The same is true of the potential V.sub.CLKB1. The line L.sub.CLKB1 has a capacitance based on a parasitic capacitance of the line L.sub.CLKB1 itself, and a capacitance of the capacitor C.sub.CLK2 and an input capacitance of the frequency converter 130 connected to the line L.sub.CLKB1. In the following, the capacitance is also referred to as a capacitance C.sub.2. The line L.sub.CLKB1 is connected to the reference potential GND1 through the resistor R.sub.2. Therefore, in the case where the input common mode potential V.sub.CM is varied, the electric charges move between the capacitance C.sub.2 and the reference potential GND1. As a result, in the case where the input common mode potential V.sub.CM is varied, the potential V.sub.CLKB1 is also varied following variation of the input common mode potential V.sub.CM. Further, since the line L.sub.CLKB1 and the reference potential GND1 are connected through the resistor R.sub.2, a low-pass filter is formed between the line L.sub.CLKB1 and the reference potential GND1. The low-pass filter limits slew rate of the potential V.sub.CLKB1. In a case where the protection circuit 170b is not provided, a potential difference V2 between the input common mode potential V.sub.CM and the potential V.sub.CLKB1 cannot maintain the certain level depending on the slew rate, which causes destruction of the internal circuit of the electronic circuit 100.

(58) In contrast, in the electronic circuit 100, when the potential difference V2 exceeds a predetermined specific value, the protection circuit 170b is turned on. In the example of FIG. 4, the diode D.sub.1b is turned on to charge the electric charges to the capacitor C.sub.2. Charge of the electric charges through the diode D.sub.1b is less influenced by the low-pass filter of the resistor R.sub.2. Therefore, as compared with the case where the charge is performed through the resistor R.sub.2, the electric charges can move at high speed. Even in the case where the slew rate of the input common mode potential V.sub.CM is high, the potential V.sub.CLKB1 can be varied following variation of the input common mode potential V.sub.CM by virtue of the protection circuit 170b, and the potential difference V2 maintains the certain level. As a result, even in the case where the potentials of the input signals S.sub.INA and S.sub.INB and the reference potential GND1 are steeply varied, it is possible to protect the internal circuit of the electronic circuit 100, and the electronic circuit 100 can have high CMTI characteristics.

(59) Although the present embodiment has been described above, modifications can be variously implemented and embodied. For example, in the present embodiment, the restoration signals S.sub.A3 and S.sub.B3 output from the buffer circuit 154 are transmitted to the logic circuit 111 as an example. Alternatively, the restoration signals S.sub.A3 and S.sub.B3 may be transmitted from the frequency converter 151, the amplifier 152, or the filter circuit 153 to the logic circuit 111. In the following, modifications of the configuration and the operation of the present embodiment are described.

(60) (Modification 1)

(61) FIG. 5 is a configuration diagram of an electronic circuit 100 in which a potential level of the input terminal INB is equivalent to the level of the reference potential GND1. Making the potential level of the input terminal equivalent to the level of the reference potential GND1 allows for omission of the ESD circuit 160b and reduction in the number of terminals on the input side. This makes it possible to reduce the circuit scale, the mounting area, and the cost.

(62) (Modification 2)

(63) FIG. 6 is a configuration diagram of an electronic circuit 100 in which output destinations of the clock signals CLKA0 and CLKB0 output from the clock circuit 112 are exchanged with output destinations of the clock signals CLKA2 and CLKB2. In the present embodiment, the phase shift added to the high-frequency signals S.sub.A2 and S.sub.B2 by transmission by the electromagnetic field coupler 140 is corrected by the clock signals CLKA2 and CLKB2. In the present modification, at a stage of conversion into the high-frequency signals by the frequency converter 130, the phase shift added to the high-frequency signals by transmission by the electromagnetic field coupler 140 is corrected.

(64) The clock circuit 112 transmits the clock signals CLKA2 and CLKB2 to the electromagnetic field coupler 120, and transmits the clock signals CLKA0 and CLKB0 to the frequency converter 151. The clock signals CLKA2 and CLKB2 are shifted in phase by transmission by the electromagnetic field coupler 120, and become clock signals CLKA3 and CLKB3. The clock signals CLKA3 and CLKB3 are transmitted to the frequency converter 130. The frequency converter 130 is driven by the clock signals CLKA3 and CLKB3, and converts the input signals S.sub.INA and S.sub.INB into high-frequency signals S.sub.A1 and S.sub.B1. The high-frequency signals S.sub.A1 and S.sub.B1 are shifted in phase by transmission by the electromagnetic field coupler 140, and become high-frequency signals S.sub.A2 and S.sub.B2. The high-frequency signals S.sub.A2 and S.sub.B2 are transmitted to the frequency converter 151. The frequency converter 151 converts frequencies of the high-frequency signals S.sub.A2 and S.sub.B2 into frequencies similar to the frequencies of the input signals S.sub.INA and S.sub.INB by using the clock signals CLKA0 and CLKB0, and generate the restoration signals S.sub.A3 and S.sub.B3. The restoration signals S.sub.A3 and S.sub.B3 are output to the output terminal OUTP and the output terminal OUTN through the amplifier 152, the filter circuit 153, and the buffer circuit 154.

(65) When the present embodiment and the present modification are combined, the electromagnetic field coupler 120 transmits one of a set of the clock signals CLKA0 and CLKB0 and a set of the clock signals CLKA2 and CLKB2 by electromagnetic field coupling. The frequency converter 130 is driven by one of a set of the clock signals CLKA1 and CLKB1 that are obtained by shifting the phases of the clock signals CLKA0 and CLKB0, and a set of the clock signals CLKA3 and CLKB3 that are obtained by shifting the phases of the clock signals CLKA2 and CLKB2, and converts a set of the input signals S.sub.INA and S.sub.INB into a set of the high-frequency signals S.sub.A1 and S.sub.B1 or a set of the high-frequency signals S.sub.A1 and S.sub.B1. The set of the high-frequency signals S.sub.A1 and S.sub.B1 or the set of the high-frequency signals S.sub.A1 and S.sub.B1 is converted into a set of the high-frequency signals S.sub.A2 and S.sub.B2 or a set of the high-frequency signals S.sub.A2 and S.sub.B2 by the electromagnetic field coupler 140. The frequency converter 151 converts the set of the high-frequency signals S.sub.A1 and S.sub.B1 or the set of the high-frequency signals S.sub.A1 and S.sub.B1 into a set of the restoration signals S.sub.A3 and S.sub.B3 by using the other of the set of the clock signals CLKA0 and CLKB0 and the set of the clock signals CLKA2 and CLKB2.

(66) As described above, the output destinations of the clock signals CLKA0 and CLKB0 may be exchanged with the output destinations of the clock signals CLKA2 and CLKB2. Based on the characteristics of the phase shift by transmission by the electromagnetic field couplers 120 and 140, the characteristics of the frequency converter 151, the characteristics of the electronic devices installed in the lines L.sub.CLKA0, L.sub.CLKA1, L.sub.CLKB0, and L.sub.CLKB1, or the like, the clock signals CLKA0 and CLKB0 may be adjusted to clock signals CLKA0 and CLKB0. In this case, the clock signals CLKA2 and CLKB2 may be adjusted to clock signals CLKA2 and CLKB2.

(67) (Modification 3)

(68) FIGS. 7A to 7C are diagrams illustrating various configurations of the protection circuits 170a and 170b. FIG. 7A illustrates the protection circuits each including the diodes described in the present embodiment. The protection circuit 170a includes the diodes D.sub.1a and D.sub.2a, and the protection circuit 170b includes the diodes D.sub.1b and D.sub.2b.

(69) FIG. 7B is a configuration diagram of protection circuits 170a and 170b each using MOS transistors. The protection circuit 170a includes transistors M.sub.1a and M.sub.2a that are connected in parallel with the line L.sub.CLKA1. A gate terminal of the transistor M.sub.1a is connected to a drain terminal, and a source terminal is connected to the reference potential GND1. A gate terminal of the transistor M.sub.2a is connected to a source terminal, and the source terminal is connected to the reference potential GND1. When the electric charges are discharged, the transistor M.sub.1a is turned on and causes a current to flow therethrough. When the electric charges are charged, the transistor M.sub.2a is turned on and causes a current to flow therethrough. The protection circuit 170b includes transistors M.sub.1b and M.sub.2b. The transistor M.sub.1b has a configuration similar to the described configuration of the transistor M.sub.1a, and the transistor M.sub.2b has a configuration similar to the described configuration of the transistor M.sub.2a.

(70) FIG. 7C is a configuration diagram of a protection circuit 170a (170b) connected to both of the lines L.sub.CLKA1 and L.sub.CLKB1. Hereinafter, the circuit is also simply referred to as the protection circuit 170a. The protection circuit 170a includes transistors M.sub.1a and M.sub.2a. A drain terminal of the transistor M.sub.1a is connected to the line L.sub.CLKA1 and a gate terminal of the transistor M.sub.2a. A source terminal of the transistor M.sub.1a and a source terminal of the transistor M.sub.2a are connected to the reference potential GND1. A drain terminal of the transistor M.sub.2a is connected to the line L.sub.CLKB1 and a gate terminal of the transistor M.sub.1a. The electric charges are charged/discharged from the reference potential GND1 to the line L.sub.CLKA1 through the transistor M.sub.1a, and the electric charges are charged/discharged from the reference potential GND1 to the line L.sub.CLKB1 through the transistor M.sub.2a. In the protection circuit 170a, the number of transistors can be reduced as compared with the protection circuits 170a and 170b. This makes it possible to reduce the circuit scale and the cost.

(71) (Modification 4)

(72) FIGS. 8A to 8C are configuration diagrams each illustrating a protection circuit in which the circuits described in FIGS. 7A to 7C are connected in multiple stages. As an example, a case where the circuits described in FIGS. 7A to 7C are connected in two stages is illustrated in FIGS. 8A to 8C; however, the circuits may be connected in three or more stages.

(73) FIG. 8A is a configuration diagram of protection circuits 170a2 and 170b2 in which the diodes described in the present embodiment are connected in multiple stages. The protection circuit 170a2 further includes diodes D.sub.1a and D.sub.4a in addition to the protection circuit 170a, and the protection circuit 170b2 further includes diodes D.sub.3b and D.sub.4b in addition to the protection circuit 170b. The diode D.sub.3a is a diode causing the current to flow therethrough in the direction same as the diode D.sub.1a, and is connected in series with the diode D.sub.1a. The diode D.sub.4a is a diode causing the current to flow therethrough in the direction same as the diode D.sub.2a, and is connected in series with the diode D.sub.2a. The diode D.sub.3b is a diode causing the current to flow therethrough in the direction same as the diode D.sub.1b, and is connected in series with the diode D.sub.1b. The diode D.sub.4b is a diode causing the current to flow therethrough in the direction same as the diode D.sub.2b, and is connected in series with the diode D.sub.2b.

(74) The predetermined potential differences V and V2 are necessary for operation of the protection circuits 170a2 and 170b2, as with the protection circuits 170a and 170b. Connecting the diodes in the multiple stages allow for optional setting of the potential differences V and V2. As a result, it is possible to reduce influence on the signals flowing through the line L.sub.CLKA1 and L.sub.CLKB1.

(75) FIG. 8B is a diagram illustrating protection circuits 170a2 and 170b2 in which the transistors described in FIG. 7B are connected in multiple stages. The protection circuit 170a2 further includes transistors M.sub.3a and M.sub.4a in addition to the protection circuit 170a, and the protection circuit 170b2 further includes transistors M.sub.3b and M.sub.4b in addition to the protection circuit 170b. The transistor M.sub.3a is connected in series with the transistor M.sub.1a (source terminal of transistor M.sub.1a and drain terminal of transistor M.sub.3a are connected). A gate terminal of the transistor M.sub.3a is connected to the drain terminal of the transistor M.sub.3a, and a source terminal of the transistor M.sub.1a is connected to the reference potential GND1. The transistor M.sub.4a is connected in series with the transistor M.sub.2a (source terminal of transistor M.sub.2a and drain terminal of transistor M.sub.4a are connected). A gate terminal of the transistor M.sub.4a is connected to a source terminal of the transistor M.sub.4a, and the source terminal of the transistor M.sub.4a is connected to the reference potential GND1. When the electric charges are discharged, the transistors M.sub.1a and M.sub.3a are turned on and cause the current to flow therethrough. When the electric charges are charged, the transistors M.sub.2a and M.sub.4a are turned on and cause the current to flow therethrough.

(76) The protection circuit 170b2 has a configuration similar to the described configuration of the protection circuit 170a2. The transistor M.sub.1a corresponds to the transistor M.sub.1b, the transistor M.sub.2a corresponds to the transistor M.sub.2b, the transistor M.sub.3a corresponds to the transistor M.sub.3b, and the transistor M.sub.4a corresponds to the transistor M.sub.4b.

(77) Also, in the protection circuits 170a2 and 170b2, connecting the transistors in the multiple stages allows for optional setting of the potential differences V and V2, as with the protection circuits 170a2 and 170b2. As a result, it is possible to reduce influence on the signals flowing through the line L.sub.CLKA1 and L.sub.CLKB1.

(78) FIG. 8C is a configuration diagram of a protection circuit 170a2 (170b2) in which the transistors described in FIG. 7C are connected in multiple stages. Hereinafter, the circuit is also simply referred to as the protection circuit 170a2. The protection circuit 170a2 further includes transistors M.sub.3a and M.sub.4a in addition to the protection circuit 170a2. The transistor M.sub.3a is connected in series with the transistor M.sub.1a (source terminal of transistor M.sub.1a and drain terminal of transistor M.sub.1a are connected). A gate terminal of the transistor M.sub.3a is connected to a gate terminal of the transistor M.sub.1a and a drain terminal of the transistor M.sub.2a. A source terminal of the transistor M.sub.3a is connected to the reference potential GND1. The transistor M.sub.4a is connected in series with the transistor M.sub.2a (source terminal of transistor M.sub.2a and drain terminal of transistor M.sub.4a are connected). A gate terminal of the transistor M.sub.4a is connected to the gate terminal of the transistor M.sub.2a and the drain terminal of the transistor M.sub.1a. A source terminal of the transistor M.sub.4a is connected to the reference potential GND1. The electric charges are charged/discharged from the reference potential GND1 to the line L.sub.CLKA1 through the transistors M.sub.1a and M.sub.3a, and the electric charges are charged/discharged from the reference potential GND1 to the line L.sub.CLKB1 through the transistors M.sub.2a and M.sub.4a.

(79) Also, in the protection circuit 170a2, connecting the transistors in the multiple stages allows for optional setting of the potential differences V and V2, as with the protection circuits 170a2 and 170b2. As a result, it is possible to reduce influence on the signals flowing through the line L.sub.CLKA1 and L.sub.CLKB1. Further, in the protection circuit 170a2, the number of transistors can be reduced as compared with the protection circuits 170a2 and 170b2. This makes it possible to reduce the circuit scale and the cost.

(80) (Modification 5)

(81) FIG. 9 is a configuration diagram of an electronic circuit 180 that further includes protection circuits 170c and 170d between the frequency converter 130 and the electromagnetic field coupler 140 of the electronic circuit 100. The protection circuit 170c is connected to the line L.sub.A1 and the reference potential GND1, and the protection circuit 170d is connected to the line L.sub.B1 and the reference potential GND1. The protection circuits 170c and 170d are respectively similar to the protection circuits 170a and 170b in the present embodiment, and various configurations described in the modifications 3 and 4 are applicable to the protection circuits 170c and 170d.

(82) When a potential of the line L.sub.A1 is defined as a potential V.sub.A1, and a potential of the line L.sub.B1 is defined as a potential V.sub.B1, the potentials V.sub.A1 and V.sub.B1 are also varied following variation of the input common mode potential V.sub.CM as in the present embodiment. First, variation of the potential V.sub.A1 is described. The line L.sub.A1 has a capacitance based on a parasitic capacitance of the line L.sub.A1 itself, and a capacitance of the capacitor C.sub.SIG1 and an output capacitance of the frequency converter 130 connected to the line L.sub.A1. Hereinafter, the capacitance is also referred to as a capacitance C.sub.3. By movement of the electric charges between the capacitance C.sub.3 and the reference potential GND1, the potential V.sub.A1 is varied following variation of the input common mode potential V.sub.CM. The line L.sub.A1 is connected to the transistors M.sub.1 and M.sub.4, and the electric charges can move through the drain and the source of each of the transistors M.sub.1 and M.sub.4. In a case where the slew rate of the input common mode potential V.sub.CM is steep, however, movement of the electric charges cannot catch up with variation of the input common mode potential V.sub.CM, and a potential difference V3 between the potential V.sub.A1 and the input common mode potential V.sub.CM may not maintain the certain level. Providing the protection circuit 170c that operates when the potential difference V3 becomes a predetermined value makes it possible to make movement of the electric charges between the line L.sub.A1 and the reference potential GND1 faster. The potential difference V3 can be maintained at the certain level and the circuits of the transistors M.sub.1 and M.sub.4, the capacitor C.sub.SIG1, and the like connected to the line L.sub.A1 can be protected by the protection circuit 170c. As a result, the electronic circuit 100 can have higher CMTI characteristics.

(83) Variation of the potential V.sub.B1 is similar to the variation of the potential V.sub.A1. The line L.sub.B1 has a capacitance based on a parasitic capacitance of the line L.sub.B1 itself and a capacitance of the capacitor C.sub.SIG2 and an output capacitance of the frequency converter 130 connected to the line L.sub.B1. Hereinafter, the capacitance is also referred to as a capacitance C.sub.4. By movement of the electric charges between the capacitance C.sub.4 and the reference potential GND1, the potential V.sub.B1 is varied following variation of the input common mode potential V.sub.CM. The line L.sub.B1 is connected to the transistors M.sub.2 and M.sub.3, and the electric charges can move through the drain and the source of each of the transistors M.sub.2 and M.sub.3. In a case where the slew rate of the input common mode potential V.sub.CM is steep, however, movement of the electric charges cannot catch up with variation of the input common mode potential V.sub.CM, and a potential difference V4 between the potential V.sub.B1 and the input common mode potential V.sub.CM may not maintain the certain level. Providing the protection circuit 170d that operates when the potential difference V4 becomes a predetermined value makes it possible to make movement of the electric charges between the line L.sub.B1 and the reference potential GND1 faster. The potential difference V4 can be maintained at the certain level and the circuits of the transistors M.sub.2 and M.sub.3, the capacitor C.sub.SIG2, and the like connected to the line L.sub.B1 can be protected by the protection circuit 170d. As a result, the electronic circuit 100 can have higher CMTI characteristics.

(84) (Modification 6)

(85) FIG. 10 is a configuration diagram of an electronic circuit 180 that further includes a protection circuit 170e between the input terminal INA and the frequency converter 130 of the electronic circuit 180, and further includes a protection circuit 170f between the input terminal INB and the frequency converter 130 of the electronic circuit 180. The protection circuit 170e is connected to the line L.sub.A0 and the reference potential GND1, and the protection circuit 170f is connected to the line L.sub.B0 and the reference potential GND1. The protection circuits 170e and 170f are similar to the protection circuits 170a and 170b according to the present embodiment, and various configurations described in the modifications 3 and 4 are also applicable to the protection circuits 170e and 170f.

(86) When a potential of the line L.sub.A0 is defined as a potential V.sub.A0, and a potential of the line L.sub.B0 is defined as a potential V.sub.B0, the potentials V.sub.A0 and V.sub.B0 are also varied following variation of the input common mode potential V.sub.CM as in the present embodiment. First, variation of the potential V.sub.A0 is described. The line L.sub.A0 has a capacitance based on a parasitic capacitance of the line L.sub.A0 itself, and a capacitance of the input terminal INA and an input capacitance of the frequency converter 130 connected to the line L.sub.A0. Hereinafter, the capacitance is also referred to as a capacitance C.sub.5. By movement of the electric charges between the capacitance C.sub.5 and the reference potential GND1, the potential V.sub.A0 is varied following variation of the input common mode potential V.sub.CM. In the line L.sub.A0, the electric charges can move through the input terminal INA and the ESD circuit 160a. In a case where the slew rate of the input common mode potential V.sub.CM is steep, however, movement of the electric charges cannot catch up with variation of the input common mode potential V.sub.CM, and a potential difference V5 between the potential V.sub.A0 and the input common mode potential V.sub.CM may not maintain the certain level. Providing the protection circuit 170e that operates when the potential difference V5 becomes a predetermined value makes it possible to make movement of the electric charges between the line L.sub.A0 and the reference potential GND1 faster. The potential difference V5 can be maintained at the certain level and the circuits of the input terminal INA, the transistors M.sub.1 and M.sub.3, and the like connected to the line L.sub.A0 can be protected by the protection circuit 170e. As a result, the electronic circuit 100 can have higher CMTI characteristics.

(87) Variation of the potential V.sub.B0 is similar to the variation of the potential V.sub.A0. The line L.sub.B0 has a capacitance based on a parasitic capacitance of the line L.sub.B0 itself and a capacitance of the input terminal INB and an input capacitance of the frequency converter 130 connected to the line L.sub.B0. Hereinafter, the capacitance is also referred to as a capacitance C.sub.6. By movement of the electric charges between the capacitance C.sub.6 and the reference potential GND1, the potential V.sub.B0 is varied following variation of the input common mode potential V.sub.CM. In the line L.sub.B0, the electric charges can move through the input terminal INB and the ESD circuit 160b. In a case where the slew rate of the input common mode potential V.sub.CM is steep, however, movement of the electric charges cannot catch up with variation of the input common mode potential V.sub.CM, and a potential difference V6 between the potential V.sub.B0 and the input common mode potential V.sub.CM may not maintain the certain level. Providing the protection circuit 170f that operates when the potential difference V6 becomes a predetermined value makes it possible to make movement of the electric charges between the line L.sub.B0 and the reference potential GND1 faster. The potential difference V6 can be maintained at the certain level and the circuits of the input terminal INB, the transistors M.sub.2 and M.sub.4, and the like connected to the line L.sub.B0 can be protected by the protection circuit 170f. As a result, the electronic circuit 100 can have higher CMTI characteristics.

(88) (Modification 7)

(89) FIG. 11 is a configuration diagram of an electronic circuit 100T in which the capacitors of the electromagnetic field couplers 120 and 140 are replaced with transformers. An electromagnetic field coupler 120 includes a transformer T.sub.CLK, and an electromagnetic field coupler 140 includes a transformer T.sub.SIG. The transformer T.sub.CLK includes paired coils performing electromagnetic field coupling, and the isolation barrier 101 is positioned between the coils. The transformer T.sub.SIG includes paired coils performing electromagnetic field coupling, and the isolation barrier 101 is positioned between the coils. This makes it possible to improve an SN ratio of each of the restoration signals. Further, the electromagnetic field couplers 120 and 140 may include a combination of a capacitor and a transformer.

(90) The modifications of the electronic circuit 100 have been described above. These modifications can be used in combination. The electronic circuit 100 can be variously arranged on a chip. Arrangement examples are described below.

Arrangement Example 1

(91) FIG. 12 is a configuration diagram of an electronic circuit 100A in which the electromagnetic field couplers 120 and 140 and the frequency converter 130 are arranged on one chip, and the other devices are arranged on a different chip. The electromagnetic field couplers 120 and 140 and the frequency converter 130 (illustrated as Passive Mixer in drawing) are arranged on Chip1. A circuitry 190 (illustrated as Active Circuitry in drawing) is arranged on Chip2. The circuitry 190 includes at least the frequency converter 151, and includes components arranged on the output side among the components of the electronic circuit 100. For example, the circuitry 190 includes the control circuit 110 and the de-modulation circuit 150. Hereinafter, a part of the circuitry 190 may be arranged on a further different chip.

Arrangement Example 2

(92) FIG. 13 is a configuration diagram of an electronic circuit 100B in which the electromagnetic field couplers 120 and 140 and the frequency converter 151 are arranged on one chip, and the frequency converter 130 is arranged on a different chip. The frequency converter 130 is arranged on Chip1. The electromagnetic field couplers 120 and 140 and the circuitry 190 are arranged on Chip2.

Arrangement Example 3

(93) FIG. 14 is a configuration diagram of an electronic circuit 100C that further includes an electromagnetic field coupler 120 connected in series with the electromagnetic field coupler 120, and an electromagnetic field coupler 140 connected in series with the electromagnetic field coupler 140. The electromagnetic field couplers 120 and 140 may be respectively similar to the electromagnetic field couplers 120 and 140 according to the present embodiment, or the electromagnetic field couplers 120 and 140 may be applied. The electromagnetic field couplers 120 and 140 and the frequency converter 130 are arranged on Chip1. The electromagnetic field couplers 120 and 140 and the circuitry 190 are arranged on Chip2. The electromagnetic field couplers are connected in series in two stages, which makes it possible to further enhance isolation property between the input terminals INA and INB and the output terminals OUTP and OUTN of the electronic circuit 100. Further, even if the electromagnetic field couplers on one of the chips may be broken down, the isolation property of a certain level or more can be maintained by the electromagnetic field couples on the other chip, which improves safety. The electromagnetic field couplers 120 and 140 may be connected in three or more stages.

Arrangement Example 4

(94) FIG. 15 is a configuration diagram of an electronic circuit 100D in which the electromagnetic field couplers 120 and 140 are arranged on a further different chip. The frequency converter 130 is arranged on Chip1. The electromagnetic field couplers 120 and 140 are arranged on Chip2. The circuitry 190 is arranged on Chip3. The electromagnetic field couplers 120 and 140 are arranged on the chip different from the chips for the frequency converter 130 and the circuitry 190, which enables Chip2 on which the electromagnetic field couplers 120 and 140 are arranged to be manufactured by a process different from a process for Chip1 and Chip3. As a result, Chip2 can be manufactured by a process high in withstand voltage performance, and the isolation property between the input terminals INA and INB and the output terminals OUTP and OUTN of the electronic circuit 100D can be further enhanced.

(95) The present embodiment, and the modification examples and the arrangement examples thereof have been described above. The electronic circuit according to the present embodiment includes the protection circuits 170a and 170b between the frequency converter 130 not receiving supply of power and the electromagnetic field coupler 120 transmitting the clock signals through the electromagnetic field coupling. Even in a case where the potentials V.sub.INA and V.sub.INB of the input signals and the reference potential V.sub.GND1 are steeply varied, the protection circuits 170a and 170b can protect the internal circuit of the electronic circuit 100 from destruction caused by potential difference. As a result, the electronic circuit 100 can have high CMTI characteristics.

Second Embodiment

(96) In a second embodiment, an application example using the electronic circuit 100 described in the first embodiment is described. FIG. 16 is a configuration diagram of a power converter 200 (illustrated as Power Converter in drawing) using the electronic circuit 100. The power converter 200 converts power input from an alternating-current power supply 20 into direct-current power, and outputs the direct-current power to a load 30 (illustrated as Load in drawing). The power converter 200 includes electronic circuits 100a and 100b, a controller 201 (illustrated as PFC Controller in drawing), resistors R.sub.D1, R.sub.D2, and R.sub.SHUNT, an inductor L, gate drivers G.sub.D1 and G.sub.D2 (illustrated as Gate Drivers in drawing), switching devices P.sub.D1 and P.sub.D2 (illustrated as Power Devices in drawing), diodes D.sub.D1 and D.sub.D2, and a capacitor C.sub.D.

(97) The electronic circuits 100a and 100b are each similar to the electronic circuit 100 described in the first embodiment. The input terminal INA of the electronic circuit 100a is connected to one end of the resistor R.sub.SHUNT, and the input terminal INB of the electronic circuit 100a is connected to the other end of the resistor R.sub.SHUNT. The resistor R.sub.SHUNT converts the input current to the power converter 200 into a voltage. A voltage at the one end of the resistor R.sub.SHUNT is input as the input signal S.sub.INA of the electronic circuit 100a, and a voltage at the other end of the resistor R.sub.SHUNT is input as the input signal S.sub.INB of the electronic circuit 100a. The electronic circuit 100a operates as a current measurement device measuring the input current of the power converter 200. The electronic circuit 100a finally transmits signals representing the input current (illustrated as I.sub.L in drawing) of the power converter 200, as the restoration signals S.sub.A3 and S.sub.B3 to the controller 201.

(98) The input terminal INA of the electronic circuit 100b is connected between the resistors R.sub.D1 and R.sub.D2, and the input terminal INB of the electronic circuit 100b is connected to an end of the resistor R.sub.D2 opposite to an end connected to the resistor R.sub.D1. The resistors R.sub.D1 and R.sub.D2 divide the input voltage to the power converter 200. A voltage at the end of the resistor R.sub.D2 connected to the resistor R.sub.D1 is input as the input signal S.sub.INA of the electronic circuit 100b, and a voltage at the other end of the resistor R.sub.D2 is input as the input signal S.sub.INB of the electronic circuit 100b. The electronic circuit 100b operates as a voltage measurement device measuring the input voltage of the power converter 200. The electronic circuit 100b finally transmits signals representing the input voltage of the power converter 200, as the restoration signals S.sub.A3 and S.sub.B3 to the controller 201. In FIG. 16, a voltage difference between two ends of the alternating-current power supply is illustrated as V.sub.AC.

(99) The controller 201 determines a current that is supplied from the gate driver G.sub.D1 to the switching device P.sub.D1 and a current that is supplied from the gate driver G.sub.D2 to the switching device P.sub.D2, by using the signals representing the input current of the power converter 200 transmitted from the electronic circuit 100a and the signals representing the input voltage of the power converter 200 transmitted from the electronic circuit 100b. The controller 201 instructs the gate drivers G.sub.D1 and G.sub.D2 to supply the respective determined currents. In the present embodiment, as an example, the controller 201 is a PFC (Power Factor Collection) Controller; however, an optional processing IC is applicable.

(100) The gate driver G.sub.D1 supplies the current to the switching device P.sub.D1 in response to the instruction from the controller 201. For example, in FIG. 16, the gate driver G.sub.D1 supplies the current to a gate terminal of the switching device P.sub.D1. The gate driver G.sub.D2 supplies the current to the switching device P.sub.D2 in response to the instruction from the controller 201. For example, in FIG. 16, the gate driver G.sub.D2 supplies the current to a gate terminal of the switching device P.sub.D2.

(101) The switching device P.sub.D1 performs switching based on the current supplied from the gate driver G.sub.D1. The switching device P.sub.D2 performs switching based on the current supplied from the gate driver G.sub.D2. A direct current is generated by the switching of the switching devices P.sub.D1 and P.sub.D2. The direct current is adjusted by the diodes D.sub.D1 and D.sub.D2 and the capacitor C.sub.D, and the adjusted current is output as an output current to the load 30.

(102) The power converter 200 according to the present embodiment has been described above. Modifications of the power converter 200 can be variously implemented and embodied. For example, any of the modifications and the arrangement examples described in the first embodiment is applicable to each of the electronic circuits 100a and 100b provided in the power converter 200. The power converter 200 according to the present embodiment causes the electronic circuit 100a to operate as the current measurement device, and causes the electronic circuit 100b to operate as the voltage measurement device. As a result, the output direct current can be controlled based on the input current and the input voltage of the power converter 200. Even in a case where the input current and the input voltage of the power converter 200 and the reference potential GND1 are steeply varied, using the electronic circuits 100a and 100b makes it possible to protect the internal circuits of the electronic circuits 100a and 100b from destruction caused by potential difference. The electronic circuits 100a and 100b each have high CMTI characteristics, which reduce the noise of the signals representing the input current and the input voltage transmitted to the controller 201. As a result, the controller 201 can more accurately instruct the gate drivers G.sub.D1 and G.sub.D2.

Third Embodiment

(103) In a third embodiment, an application example using the electronic circuit 100 described in the first embodiment is described. FIG. 17 is a configuration diagram of an inverter 300 using the electronic circuit 100. The inverter 300 is, for example, a three-phase inverter supplying a current to a motor M. The inverter 300 includes electronic circuits 100a, 100b, 100c, and 100d, a controller 301 (illustrated as MCU in drawing), resistors R.sub.D1, R.sub.D2, R.sub.SHUNT1, R.sub.SHUNT2, and R.sub.SHUNT3, gate drivers G.sub.D1, G.sub.D2, G.sub.D3, G.sub.D4, G.sub.D5, and G.sub.D6, and switching devices P.sub.D1, P.sub.D2, P.sub.D3, P.sub.D4, P.sub.D5, and P.sub.D6.

(104) Each of the electronic circuits 100a, 100b, 100c, and 100d is similar to the electronic circuit 100 described in the first embodiment. The input terminal INA of the electronic circuit 100a is connected between the resistors R.sub.D1 and R.sub.D2, and the input terminal INB of the electronic circuit 100a is connected to an end of the resistor R.sub.D2 opposite to an end connected to the resistor R.sub.D1. The resistors R.sub.D1 and R.sub.D2 divide an input voltage V+ to the inverter 300. A voltage at the end of the resistor R.sub.D2 connected to the resistor R.sub.D1 is input as the input signal S.sub.INA of the electronic circuit 100a, and a voltage at the other end of the resistor R.sub.D2 is input as the input signal S.sub.INB of the electronic circuit 100a. The electronic circuit 100a operates as a voltage measurement device measuring the input voltage V+ of the inverter 300. The electronic circuit 100a finally transmits signals representing the input voltage V+ of the inverter 300, as the restoration signals S.sub.A3 and S.sub.B3 to the controller 301.

(105) The input terminal INA of the electronic circuit 100b is connected one end of the resistor R.sub.SHUNT1, and the input terminal INB of the electronic circuit 100b is connected to the other end of the resistor R.sub.SHUNT1. The resistor R.sub.SHUNT1 converts an output current I.sub.1 generated by the switching devices P.sub.D1 and P.sub.D2 into a voltage. A voltage at one end of the resistor R.sub.SHUNT1 is input as the input signal S.sub.INA of the electronic circuit 100b, and a voltage at the other end of the resistor R.sub.SHUNT1 is input as the input signal S.sub.INB of the electronic circuit 100b. The electronic circuit 100b operates as a current measurement device measuring the output current I.sub.1 generated by the switching devices P.sub.D1 and P.sub.D2. The electronic circuit 100b finally transmits signals representing the output current I.sub.1, as the restoration signals S.sub.A3 and S.sub.B3 to the controller 301.

(106) The input terminal INA of the electronic circuit 100c is connected to one end of the resistor R.sub.SHUNT2, and the input terminal INB of the electronic circuit 100c is connected to the other end of the resistor R.sub.SHUNT2. The resistor R.sub.SHUNT2 converts an output current I.sub.2 generated by the switching devices P.sub.D3 and P.sub.D4 into a voltage. A voltage at one end of the resistor R.sub.SHUNT2 is input as the input signal S.sub.INA of the electronic circuit 100c, and a voltage at the other end of the resistor R.sub.SHUNT2 is input as the input signal S.sub.INB of the electronic circuit 100c. The electronic circuit 100c operates as a current measurement device measuring the output current I.sub.2 generated by the switching devices P.sub.D3 and P.sub.D4. The electronic circuit 100c finally transmits signals representing the output current I.sub.2, as the restoration signals S.sub.A3 and S.sub.B3 to the controller 301.

(107) The input terminal INA of the electronic circuit 100d is connected one end of the resistor R.sub.SHUNT3, and the input terminal INB of the electronic circuit 100d is connected to the other end of the resistor R.sub.SHUNT3. The resistor R.sub.SHUNT3 converts an output current I.sub.3 generated by the switching devices P.sub.D5 and P.sub.D6 into a voltage. A voltage at one end of the resistor R.sub.SHUNT3 is input as the input signal S.sub.INA of the electronic circuit 100d, and a voltage at the other end of the resistor R.sub.SHUNT3 is input as the input signal S.sub.INB of the electronic circuit 100d. The electronic circuit 100d operates as a current measurement device measuring the output current I.sub.3 generated by the switching devices P.sub.D5 and P.sub.D6. The electronic circuit 100d finally transmits signals representing the output current I.sub.3, as the restoration signals S.sub.A3 and S.sub.B3 to the controller 301.

(108) The controller 301 determines a current supplied from the gate driver G.sub.D1 to the switching device P.sub.D1, a current supplied from the gate driver G.sub.D2 to the switching device P.sub.D2, a current supplied from the gate driver G.sub.D3 to the switching device P.sub.D3, a current supplied from the gate driver G.sub.D4 to the switching device P.sub.D4, a current supplied from the gate driver G.sub.D5 to the switching device P.sub.D5, and a current supplied from the gate driver G.sub.D6 to the switching device P.sub.D6, by using the signals representing the input voltage and the signals representing the output currents I.sub.1, I.sub.3, and I.sub.3 of the inverter 300, transmitted from the electronic circuits 100a to 100d. The controller 301 instructs the gate drivers G.sub.D1 to G.sub.D6 to supply the respective determined currents. In the present embodiment, as an example, the controller 301 is an MCU (Micro Control Unit); however, an optional processing IC is applicable.

(109) The gate drivers G.sub.D1 to G.sub.D6 supply the currents to the respective switching devices P.sub.D1 to P.sub.D6 in response to the instruction from the controller 301. The gate drivers G.sub.D1 to G.sub.D6 are provided corresponding to the respective switching devices P.sub.D1 to P.sub.D6, and supply the currents instructed by the controller 301 to the respective corresponding switching devices. For example, in FIG. 17, the gate driver G.sub.D1 supplies the current instructed by the controller 301 to a gate terminal of the switching device P.sub.D1. The gate driver G.sub.D2 supplies the current instructed by the controller 301 to a gate terminal of the switching device P.sub.D2. The gate driver G.sub.D3 supplies the current instructed by the controller 301 to a gate terminal of the switching device P.sub.D3. The gate driver G.sub.D4 supplies the current instructed by the controller 301 to a gate terminal of the switching device P.sub.D4. The gate driver G.sub.D5 supplies the current instructed by the controller 301 to a gate terminal of the switching device P.sub.D5. The gate driver G.sub.D6 supplies the current instructed by the controller 301 to a gate terminal of the switching device P.sub.D6.

(110) The switching devices P.sub.D1 to P.sub.D6 perform switching based on the currents supplied from the respective connected gate drivers G.sub.D1 to G.sub.D6. The output currents are generated by the switching of the switching devices P.sub.D1 to P.sub.D6. For example, the output current I.sub.1 is generated by the switching of the switching devices P.sub.D1 and P.sub.D2, the output current I.sub.2 is generated by the switching of the switching devices P.sub.D3 and P.sub.D4, and the output current I.sub.3 is generated by the switching of the switching devices P.sub.D5 and P.sub.D6. The generated output currents I.sub.1 to I.sub.3 are output to the motor M and drive the motor M.

(111) The inverter 300 according to the present embodiment has been described above. Modifications of the inverter 300 can be variously implemented and embodied. For example, any of the modifications and the arrangement examples described in the first embodiment is applicable to each of the electronic circuits 100a to 100d provided in the inverter 300. Further, the resistors R.sub.D1 and R.sub.D2, the gate drivers G.sub.D1 and G.sub.D2, and the switching device P.sub.D1 and P.sub.D2 described in the present embodiment may be similar to or different from those described in the second embodiment.

(112) The inverter 300 according to the present embodiment causes the electronic circuit 100a to operate as the voltage measurement device, and causes the electronic circuits 100b to 100d to operate as the current measurement devices. As a result, the output currents I.sub.1 to I.sub.3 can be controlled based on the input voltage and the output currents I.sub.1 to I.sub.3 of the inverter 300. Even in a case where the input voltage and the output currents I.sub.1 to I.sub.3 of the inverter 300 and the reference potential GND1 are steeply varied, using the electronic circuits 100a to 100d makes it possible to protect the internal circuits of the electronic circuits 100a to 100d from destruction caused by potential difference. The electronic circuits 100a to 100d each have high CMTI characteristics, which reduces the noise of the signals representing the input voltage and the signals representing the output currents I.sub.1 to I.sub.3 of the inverter 300, transmitted to the controller 301. As a result, the controller 301 can more accurately instruct the gate drivers G.sub.D1 to G.sub.D6.

(113) While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.