MANUFACTURING METHOD OF CIRCUIT SUBSTRATE

Abstract

A manufacturing method of a circuit substrate comprises the steps of providing a laminated substrate comprising an insulating layer and a circuit layer disposed on the insulating layer; forming a photoresist layer on the circuit layer; mechanically cutting the photoresist layer and a part of the circuit layer to form gaps; etching the circuit layer in the gaps until a surface of the insulating layer is exposed to form a circuit layout; and removing the photoresist layer to form the circuit substrate.

Claims

1. A manufacturing method of a circuit substrate, comprising: providing a laminated substrate comprising an insulating layer and a circuit layer disposed on the insulating layer; forming a photoresist layer on the circuit layer; mechanically cutting the photoresist layer and a part of the circuit layer to form gaps; etching the circuit layer in the gaps until a surface of the insulating layer is exposed to form a circuit layout; and removing the photoresist layer to form the circuit substrate.

2. The manufacturing method of claim 1, wherein a depth of a circuit layer removed by mechanically cutting in the gap is 50-90% of a thickness of the circuit layer.

3. The manufacturing method of claim 1, wherein the thickness of the circuit layer is 0.4-6 mm

4. The manufacturing method of claim 1, wherein the circuit layer is a copper layer.

5. The manufacturing method of claim 1, wherein the laminated substrate further comprises a metal substrate disposed on a bottom surface of the insulating layer, and the metal substrate is a copper layer or an aluminum layer.

6. The manufacturing method of claim 1, wherein the gap has a sidewall with an angle of 75-90 degrees.

7. The manufacturing method of claim 1, wherein the gap has a top width W1 and a bottom width W2 and a ratio W2/W1 is in the range of 0.5-0.9.

8. The manufacturing method of claim 1, wherein the gap has a top width W1 and the circuit layer has a thickness H and a ratio H/W1 is in the range of 1-5.

9. The manufacturing method of claim 1, wherein the step of etching performs less than 30% over etch.

10. The manufacturing method of claim 1, wherein the insulating layer has a thermal conductivity of 2-20W/m.Math.K.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present application will be described according to the appended drawings in which:

[0018] FIG. 1 through FIG. 5 show the method of manufacturing a circuit substrate in accordance with an embodiment of the present application;

[0019] FIG. 6 shows an enlarged view of a gap in FIG. 5; and

[0020] FIG. 7 shows a flow chart for manufacturing a circuit substrate in accordance with an embodiment of the present application.

DETAILED DESCRIPTION OF THE INVENTION

[0021] The making and using of the presently preferred illustrative embodiments are discussed in detail below. It should be appreciated, however, that the present application provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific illustrative embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0022] FIG. 1 through FIG. 5 show a process of making a circuit substrate in accordance with an embodiment of the present application. In FIG. 1, a laminated substrate 10 comprises a metal substrate 13, an insulating layer 11 and a circuit layer 12. The insulating layer 11 is disposed on an upper surface of the metal substrate 13 and the circuit layer 12 is disposed on the upper surface of the insulating layer 11 to form a laminated structure. The metal substrate 13 may have a thickness of 0.3-5 mm and may be a copper layer or an aluminum layer for heat dissipation. The insulating layer 11 may have a thickness of 0.05-0.25 mm and may be a polymer layer containing thermally conductive filler. The thermal conductivity of the insulating layer 11 may be 2-20W/m.Math.K, e.g., 5W/m.Math.K, 8W/m.Math.K or 12W/m.Math.K. The circuit layer 12 may have a thickness of 0.4-6 mm, e.g., 1 mm, 3 mm or 5 mm, and may be a copper layer or an aluminum layer.

[0023] In FIG. 2 and FIG. 3, a photoresist layer 14 is formed on the circuit layer 12. In an embodiment, the photoresist layer 14 has a thickness of 20-30 m. The photoresist layer 14 and a part of the circuit layer 12 are mechanically cut out by a cutter to form gaps 15 at positions with reference to a circuit layout. As a result, the circuit layer 12 still has a portion remaining in the gaps 15. In FIG. 4, the circuit layer 12 in the gaps 15 is etched until a surface of the insulating layer 11 is exposed. In an embodiment, chemical etching is employed and etchant may use acidic solution, e.g., copper chloride. A ratio of the thickness of the circuit layer 12 to be etched to the photoresist thickness is 16-200. Afterwards, the photoresist layer 14 is removed to form a circuit substrate 20 as shown in FIG. 5.

[0024] FIG. 6 shows details of a gap 15. For clarity and simplicity, the metal substrate is omitted in FIG. 6. In the formation of the gap 15 in the circuit layer 12, the circuit layer 12 is mechanically cut to a depth H1 and then is etched to a surface of the insulating layer 11 with a depth H2. The depth of the gap 15 is equal to the thickness H of the circuit layer 12, i.e., H=H1+H2. The depth H1 removed by mechanically cut is 50-90% of the thickness H, i.e., H1/H=50-90%. For example, H1/H=60% or 80%. If H1/H is less than 50%, making the gap 15 becomes slow and the opening or the top of the gap 15 is enlarged. If H1/H is greater than 90%, there is a concern to cut the insulating layer 11 due to inaccurate control of mechanical cutting. An angle between a sidewall of a portion of the gap 15 formed by mechanical cutting and a horizontal plane is 75-90. If over-etched, the opening of the gap 15 is enlarged and the angle of the sidewall of the gap 15 becomes smaller, e.g., less than 70. As a consequence, circuit quality would be deteriorated. In accordance with the present application, the etching step performs less than 30% or 20% over etch, and therefore the bottom sidewalls of the gap 15 may be in the form of arcs. If the top width of the gap 15 is W1 and the bottom width of the gap 15 is W2, W2/W1 is 0.5-0.9, e.g., 0.6 or 0.8. Because wet etching is isotropic, the gap cannot be wet etched deeply and the width of the gap is usually equal to or larger than the depth of the gap. In accordance with the present application, the gap 15 can be made deeper with H/W1 of 1-5. Table 1 shows the dimensions of gaps in accordance with embodiments E1-E7 of the present application, the unit of H, H1, H2, W1 and W2 is millimeters.

TABLE-US-00001 TABLE 1 H H1 H2 W1 W2 W2/W1 H/W1 E1 0.4 0.3 0.1 0.3 0.25 85 0.83 1.33 E2 1 0.8 0.2 0.5 0.35 85 0.7 2 E3 3.2 2.9 0.3 1.8 1.2 84 0.67 1.78 E4 2 1.8 0.2 0.5 0.3 87 0.6 4 E5 5 4.1 0.9 5 4.2 84 0.84 1 E6 2.5 2 0.5 2 1 75 0.5 1.25 E7 3 1.8 1.2 0.8 0.5 85 0.63 3.75

[0025] is A flow chart of the manufacturing method of a circuit substrate in accordance with the present application is shown in FIG. 7. Step S61: Providing a laminated substrate comprising an insulating layer and a circuit layer disposed on the insulating layer. Step S62: Forming a photoresist layer on the circuit layer. Step S63: Mechanically cutting the photoresist layer and a part of the circuit layer to form gaps. Step S64: Etching the circuit layer in the gaps until a surface of the insulating layer is exposed to form a circuit layout. Step S65: Removing the photoresist layer to form a circuit substrate.

[0026] Traditionally, the circuit layout with gaps formed by a single process of wet etching has a limitation that the width of the gap is not less than the depth of the gap and the depth of the gap is equal to the thickness of the circuit layer. To form a deep gap or a narrow gap, it is difficult to fully etch the circuit layer down to the bottom and the circuit layer still remains in the gap. Moreover, the deep or narrow gap may cause longer etching time and therefore the gap in the circuit layer of a thickness more than 0 4 mm would not be manufactured by etching. The thick circuit layer is a bottleneck hard to breakthrough by traditionally wet etching. In combination of mechanical cutting and chemical or wet etching in accordance with the present application, a circuit layer of a thickness of 0.4-6 mm can be made to form gaps of circuit layout. For example, for a circuit layer of a thickness up to 5 mm made by the method of the present application, the line gap can be 0.7-1 mm and etching factor is greater than 9 This resolves the problem that line gap is limited to the circuit layer thickness. The method of the present application overcomes etching inefficient problems and is suitable for high current applications of the circuit substrate with a thick circuit layer.

[0027] The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by persons skilled in the art without departing from the scope of the following claims.