Microelectronic device

Abstract

This invention relates to a microelectronic device comprising: a first support, a second support, first respective faces of the first support and second support being arranged opposite, and a sealing layer between said first faces, characterized in that the sealing layer comprises at least one layer of an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w, with x strictly greater than 0 and less than or equal to 4.5, y strictly greater than 0 and less than or equal to 1, z strictly greater than 0 and less than or equal to 5.5, w greater than or equal to 0 and less than or equal to 1.

Claims

1. A method for making a microelectronic device comprising a first support, a second support, first respective faces of the first support and the second support being arranged opposite, with the method comprising: forming a sealing layer between said first respective faces of the first support and the second support, wherein the sealing layer comprises at least one layer of an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w, with x being greater than 0 and less than or equal to 4.5, y being greater than 0 and less than or equal to 1, z being greater than 0 and less than or equal to 5.5, w being greater than or equal to 0 and less than or equal to 1; and after the forming of the sealing layer, performing an anodic bonding between the sealing layer and the first face of the first support and between the sealing layer and the first face of the second support by applying a voltage less than 100 volts and/or a temperature less than 150 C.

2. The method according to claim 1, wherein the forming of the sealing layer comprises forming a hermetic cavity delimited by the first face of the first support, the first face of the second support and the sealing layer.

3. The method according to claim 1, wherein at least one among parameters x, y, z, w of the ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w varies along a thickness dimension of the sealing layer.

4. A microelectronic device comprising: a first support; a second support; and a sealing layer comprising an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w, with x being greater than 0 and less than or equal to 4.5, y being greater than 0 and less than or equal to 1, z being greater than 0 and less than or equal to 5.5, w being greater than or equal to 0 and less than or equal to 1, between and anodically bonded to the first support and the second support.

5. The method of claim 2, wherein at least one of the first face of the first support and the first face of the second support, carries at least one electronic component, and wherein the at least one electronic component is encapsulated in said hermetic cavity.

6. The method of claim 5, further comprising forming a layer of Li.sub.xP.sub.yO.sub.zN.sub.w on the electronic component, said layer formed from a same ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w as the sealing layer.

7. The method of claim 5, wherein the electronic component is selected among a micro-battery and an electrochromic component.

8. The method of claim 1, further comprising forming a barrier layer, wherein at least one portion of the barrier layer is disposed on an external flank of the sealing layer or on an internal flank of the sealing layer.

9. The method of claim 1, further comprising forming an intermediate barrier layer between two portions of the sealing layer.

10. The method of claim 3, further comprising forming a composition gradient w/y that changes from a minimum value on a bonding interface of the sealing layer in contact with one among the first support and the second support having a highest thermal expansion coefficient to a maximum value on a bonding interface of the sealing layer in contact with another support among the first support and the second support having a least thermal expansion coefficient.

11. The method of claim 1, further comprising forming a second sealing layer, wherein the second sealing layer comprises at least one layer of an ionic conductive material of formula Li.sub.x1P.sub.y1O.sub.z1N.sub.w1, with x1 being greater than 0 and less than or equal to 4.5, y1 being greater than 0 and less than or equal to 1, z1 being greater than 0 and less than or equal to 5.5, w1 being greater than or equal to 0 and less than or equal to 1; and after forming the second sealing layer, bonding the first support with a second additional support.

12. The method of claim 11, further comprising selecting different chemical compositions respectively for the sealing layer and the second sealing layer.

13. A method for making a microelectronic device comprising a first support, a second support, first respective faces of the first support and the second support being arranged opposite, with the method comprising: forming a sealing layer between and in contact with said first respective faces of the first support and the second support, wherein the sealing layer comprises at least one layer of an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w, with x being greater than 0 and less than or equal to 4.5, y being greater than 0 and less than or equal to 1, z being greater than 0 and less than or equal to 5.5, w being greater than or equal to 0 and less than or equal to 1, and wherein, after the forming of the sealing layer, performing an anodic bonding by applying a voltage less than 100 volts and/or a temperature less than 150 C.

14. A microelectronic device comprising: a first support; a second support; and a layer of anodic bonding comprising an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w, with x being greater than 0 and less than or equal to 4.5, y being greater than 0 and less than or equal to 1, z being greater than 0 and less than or equal to 5.5, w being greater than or equal to 0 and less than or equal to 1, between and anodically bonded to the first support and the second support.

Description

BRIEF INTRODUCTION OF THE FIGURES

(1) Other characteristics, purposes and advantages of this invention shall appear when reading the following detailed description, along with the annexed drawings, provided as non-limiting examples, and wherein:

(2) FIG. 1A shows a cross-section view of a first support whereon a sealing layer is deposited.

(3) FIG. 1B shows a cross-section view of a first support and of a second support separated by a sealing layer.

(4) FIG. 2 shows a cross-section view of a first support whereon a component is positioned, and of a second support, separated by a sealing layer; with the component being encapsulated in a cavity delimited by the first support, the second support and the sealing layer.

(5) FIG. 3 shows a cross-section view of a particular embodiment showing the presence of a barrier layer positioned on the flanks of the sealing layer internal and external to the cavity.

(6) FIG. 4 shows a cross-section view of a particular embodiment showing a plurality of barrier layers.

(7) FIG. 5 shows a cross-section view of a particular embodiment wherein the sealing layer has a gradient in its chemical composition that changes in relation to its thickness.

(8) FIG. 6 shows a cross-section view of a particular embodiment where in a second support is separated from the first support by a first sealing layer and a second additional support is separated from the first support by a second sealing layer.

(9) FIGS. 7a, 7b and 7c show another embodiment of the invention.

(10) The drawings are provided by way of examples and do not limit the invention. They consist of block diagrams intended to facilitate the comprehension of the invention and are not necessarily to the scale of practical applications. In particular, the relative thicknesses of the various layers and substrates may not be representative of reality.

DETAILED DESCRIPTION

(11) Before beginning a detailed review of the embodiments of the invention, hereinafter are mentioned optional characteristics that may be used according to any combination or alternatively: The device is such that at least one among the first support 1 and the second support 2 carries on its first face at least one electronic component 3; it comprises a hermetic cavity 9 delimited by the first face of the first support 1, the first face of the second support 2 and the sealing layer 4, said at least electronic component 3, being encapsulated in said cavity 9; with the cavity 9 comprising a getter; the electronic component 3 comprises a layer of Li.sub.xP.sub.yO.sub.zN.sub.w formed from the same layer of an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w as the sealing layer 4, more preferably in order form one among: a micro-battery, an electrochromic component; the sealing layer 4 forms a closed contour; the device comprises a barrier layer 5; with at least one portion of the barrier layer 5 being arranged on an external flank of the sealing layer 4; a portion of the barrier layer 5 is arranged on an internal flank of the sealing layer 4; the barrier layer 5 comprises an insulating dielectric material; an intermediate barrier layer 6 is positioned between two portions of the sealing layer 4; at least one among the parameters x, y, z, w of the compound Li.sub.xP.sub.yO.sub.zN.sub.w can change in the thickness of the sealing layer 4; a composition gradient w/y changes from a minimum value on a bonding interface of the sealing layer 4 in contact with one among the first and the second supports 1, 2 having the highest thermal expansion coefficient to a maximum value on a bonding interface of the sealing layer in contact with the other support among the first and the second supports 1, 2 having the least expansion coefficient. The device comprises a second sealing layer 42 pour assembler the first support 1 with a second additional support 22; the second sealing layer 42 comprises at least one layer of an ionic conductive material of formula Li.sub.x1P.sub.y1O.sub.z1N.sub.w1, with x1 strictly greater than 0 and less than or equal to 4.5, y1 strictly greater than 0 and less than or equal to 1, z1 strictly greater than 0 and less than or equal to 5.5, w1 greater than or equal to 0 and less than or equal to 1; the sealing layer 4 and the second sealing layer 42 have different chemical compositions; the second sealing layer 42 has a thickness less than 5 microns, preferably less than 2 microns; the sealing layer 4 a thickness less than 5 microns, preferably less than 2 microns; at least one support among the first support 1 and the second support 2 has a hollow on its first face. the first support 1 and/or the second support 2 are/is formed from a material with a base of glass, doped or non-doped semi-conductor, metal or a semi-conductor comprising a metal layer. after the formation of the sealing layer 4, an anodic bonding is carried out by applying a voltage less than 100 volts and/or a temperature less than 150 C.; the step of forming the sealing layer is configured in such a way as to form a hermetic cavity 9 delimited by the first face of the first support 1, the first face of the second support 2 and the sealing layer 4; at least one among the first support 1 and the second support 2 carries on its first face at least one electronic component 3, in such a way that the component 3 is encapsulated in said cavity 9; at least one layer of the component 3 is formed from the layer of an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w of the sealing layer 4. a getter is formed in the cavity 9; the step of forming the sealing layer 4 comprises the formation of a barrier layer 5; with the barrier layer 5 being arranged on an external flank of the sealing layer 4. the barrier layer 5 is arranged on an internal flank of the sealing layer 4; an intermediate barrier layer 6 is formed in such a way that it is positioned between two portions of the sealing layer 4; at least one from the parameters x, y, z, w of the compound Li.sub.xP.sub.yO.sub.zN.sub.w can change in the thickness of the sealing layer 4; a composition gradient w/y is formed that changes from a minimum value on a boding interface of the sealing layer 4 in contact with one among the first and the second supports having the highest thermal expansion coefficient to a maximum value on a boding interface of the sealing layer in contact with the other support among the first and the second supports having the least expansion coefficient. a second sealing layer is formed in order to assemble the first support with a second additional support; the second sealing layer comprises at least one layer of an ionic conductive material of formula Li.sub.x1P.sub.y1O.sub.z1N.sub.w1, with x1 strictly greater than 0 and less than or equal to 4.5, y1 strictly greater than 0 and less than or equal to 1, z1 strictly greater than 0 and less than or equal to 5.5, w1 greater than or equal to 0 and less than or equal to 1;

(12) It is specified that, in the framework of this invention, the term on does not necessarily mean in contact with.

(13) As such, for example, the deposition of a layer on another layer, does not necessarily mean that the two layers are directly in contact with one another but this means that one of the layers at least partially covers the other by being either directly in contact with it, or by being separated from it by a film, another layer or another element.

(14) It is also specified that, in the framework of this invention, the thickness of a layer is measured according to a direction perpendicular to the surface according to which this layer has its maximum extension. Typically, when the layers form cylinder portions, their thickness is taken according to a direction perpendicular to the two faces forming disks. In FIG. 2 for example, the thickness is taken according to the vertical.

(15) The invention relates to a method for carrying out a microelectronic device, in reference to FIGS. 1 to 6. According to the invention, microelectronic device means a device comprising elements with micronic and/or nanometric dimensions. Such a device may or may not comprise one or several components. It can also be an assembly of supports with a basis of layers of which for example a portion is made of a semiconductor material or materials.

(16) FIG. 1A shows a cross-section view of a first support 1 on a first face of which is deposited a sealing layer 4. It is preferably meant by support, a substrate, a chip or a wafer comprising at least one chip. Is meant in particular any substrate that comprises at least one electronic element. The first support 1 can, for example, include silicon, doped silicon, a semiconductor, glass, a metal or an insulating substrate that has a metal deposition on the surface.

(17) Advantageously, the sealing layer 4 comprises at least one layer of an ionic conductive material, of formula Li.sub.xP.sub.yO.sub.zN.sub.w with 0<x4.5, 0<y1, 0<z5.5 and 0w1. The sealing layer 4 possibly has a thickness less than 5 m, preferably less than 2 m. Preferably, this sealing layer 4 has a thickness between 0.1 and 5 microns. The sealing layer 4 is carried out in particular by deposition techniques such as: reactive spray deposition, laser ablation, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), or sol-gel deposition.

(18) A second step consists in putting into contact the first support 1 covered with the sealing layer 4 with a second support 2. FIG. 1B shows a cross-section view of a first support and of a second support separated by a sealing layer 4.

(19) The second support 2 can, for example, include silicon, doped silicon, a semi-conductor, glass, a metal or an insulating substrate that has a metal deposition on the surface.

(20) An anodic bonding is then carried out by applying a low voltage, preferably less than 100 volts, and/or a low temperature, preferably less than 150 C.

(21) The first support and second support 1, 2 can be a passive substrate without an active layer, a substrate with electrical elements or a substrate with one or several components of the same nature or of different natures. The predominant criterion in the choice of the materials comprising the supports 1, 2 is dictated by the barrier properties required for the target application. These supports 1, 2 of a thickness preferentially less than 100 microns can be of a metal, ceramic, glass nature or any other material or combinations of materials that make it possible to guarantee if needed sufficient seal with respect to the oxidizing species such as for example: water H.sub.2O or/and oxygen O.sub.2, or/and nitrogen N.sub.2, or/and rare gases.

(22) According to the target application, other criteria of a nature that is optical (transparence and transmittance), thermal, chemical-physical (resistance to corrosion) or mechanical can be required. Preferably, the supports 1, 2 are chosen from the wide range of different families of glasses (borofloat, borosilicates or derivatives thereof), at thicknesses in particular less than or equal to 100 microns.

(23) In the embodiment in FIG. 1B the device of the invention does not comprise a cavity. The sealing layer is a full layer and makes it possible to seal the two supports. The objective of the invention can reside in this sealing, without the formation of a cavity. The sealing layer can for example be a full wafer or form any closed contour or not suitable for the sealing. This sealing can be of course reversible and the 2 supports can be dissociated by using mechanical stresses and/or by using a suitable thermal treatment and/or par chemical etching and/or by laser ablation of the sealing layer.

(24) According to a preferred but not limiting embodiment of the invention, at least one component 3 is formed in the device. The steps of carrying out an electronic device, comprising at least one component 3, for example of the lithium micro-battery type, can be carried out such as shown in FIGS. 2 to 6.

(25) Generally, the component 3 (for example, a micro-battery) is carried out by known techniques of prior art. The dimensions and the thicknesses of the layers that comprise the component 3, are given for the purposes of illustration in order to show the principles of the invention. The description provided in the rest of this document shall make reference to a particular lithium micro-battery device, with the understanding that this example is provided for the purposes of illustration and is not limiting. It can be transposed to any electronic, optical, optoelectronic, micromechanical or other component. According to particular embodiments, the component 3 is chosen from a micro-battery, an electrochromic component, a micro-sensor, or another component that integrates a sealing layer, preferably of formula Li.sub.xP.sub.yO.sub.zN.sub.w in its structure.

(26) In FIG. 2, the component 3 is encapsulated in a hermetic cavity 9 delimited by the first face of the first support 1, the first face of the second support 2 and the sealing layer 4. Advantageously, at least one support among the first support 1 and the second support 2 is hollow. The assemblage comprised by the first support 1 and the second support 2 is a mechanically solid assembly. The active layers of the component 3 are imprisoned in a perfectly hermetic cavity 9 defined by a juncture between the first support 1 and the second support 2. Optionally, the cavity 9 generated by the sealing of the second support 2 on the first support 1, comprising the component 3, can be controlled in atmosphere, by carrying out the methods of sealing under an inert gas (such as argon) or in a vacuum. A getter can be used to absorb at least partially gaseous species such as oxygen and/or nitrogen. In particular, in order to obtain a controlled pressure (nature and partial pressure of the gases), a deposition of a getter can be added that is more preferably metal as a thin layer of the NEG (Non Evaporable getter) type. The thickness of the latter can be between 0.2 and 2 m and its composition is chosen in such a way that it is thermally activatable at a temperature compatible with the device 3. By way of example a ternary alloy TiZrV can be activated at a temperature close to 150 C., while a binary alloy with a base of Ti and/or Zr will be activatable at a higher temperature, but less than 400 C.

(27) In the framework of this invention, the method for transferring the second support 2 onto the first support 1 is made possible by the use of sealing techniques. The principle is to provide the first support 1 with a sealing layer 4 homogeneously or in the form of a sealed seam or micro-seam, before mechanically freezing the second support 2 on the first support 1. Advantageously, the sealing material is designed in the form of sealed seam at the periphery of the first support 1, in such a way as to surround the sensitive component 3. The sealing layer 4 advantageously forms a closed contour around the at least one component 3. Advantageously, the sealing layer 4 is formed from an electrically insulating material. The shape, height, length and width of the sealing layer 4 are parameters that can be adjusted according to the nature of the devices or microelectronic components.

(28) According to an embodiment of the invention, the thickness of the sealing layer 4 is advantageously chosen in such a way as to create a cavity 9 between the first support 1 and the second support 2 required for correct electrical functionality without altering the electrical properties of the component 3, for example a battery. The height of such a cavity 9 is defined by the difference between the thickness of the sealing layer 4 and that of the component 3, forming for example a battery. Typically, the minimum value of this height is set to around 5% of the value of the total thickness of the component 3. The dimensions (the thickness in particular) of the sealing layer 4, recommended in the embodiments, can be adjusted according to the applications. However, it must be ensured that the barrier and mechanical robustness properties are preserved.

(29) This sealing layer 4 can be carried out on the first support 1 containing the component 3, or alternatively on the second support 2, by using the various techniques known in prior art. As an indication, dispense or screen-printing are the preferred techniques that are the most compatible with respect to the dimensions and architectures required for the sealing layer 4.

(30) According to the recommended principles in the framework of this invention, the sealing layer 4 surrounds and delimits the active portions of the component 3.

(31) In addition, this solution guarantees increased mechanical robustness of the assembly comprised of the microelectronic device and its packaging. This major advantage has application in the methods for the three-dimensional assembly of microelectronic components in general and more particularly the components made from ultra-thin substrates (less than 50 microns thick) requiring the use of ultra-thin encapsulation covers, such as the second support 2.

(32) Advantageously, sealing by anodic bonding makes it possible to carry out a hermetic sealing of the component 3 sensible, without degrading the performance of said component 3.

(33) Sealing by anodic bonding is a simple and robust method that offers a highly promising solution for the encapsulation of microelectronic devices. One of the main advantages of this technique is linked to its facility of implementation independently of the flatness of the surfaces to be bonded due to its high wetting capacities. Generally, the seal of the sealing layer 4 is the first criterion sought for the encapsulation solution by the transfer of a second support 2.

(34) According to a particular embodiment shown in FIG. 3, a barrier layer 5 is arranged on at least one of the flanks of the sealing layer 4, Preferably, the barrier layer 5 forms at least one portion that has a closed contour closing the flank of the sealing layer 4 between the first faces of the supports 1, 2. According to an embodiment, the barrier layer 5 is arranged on the flank of the sealing layer 4 external to the cavity 9. According to another embodiment, the barrier layer 5 is arranged on the flank of the sealing layer 4 interne to the cavity 9. Preferably, the barrier layer 5 is positioned in two portions on either side of the sealing layer 4, in other words on the flanks internal and external to the cavity 9, making it possible to provide an additional barrier and to improve the hermeticity of the sealing. The barrier layer 5 comprises more preferably an insulating dielectric material. This additional layer can, for example, be an oxide, a nitride or a silicon oxinitride, an aluminum oxide or a titanium oxide deposited by CVD, PECVD or LPCVD. The barrier layer 5 is for example formed using lithographic or photolithographic techniques. The barrier layer 5 has a thickness or width according to the plane of the faces to be assembled, more preferably between 1 and 10 microns.

(35) According to an embodiment shown in FIG. 4, an intermediate barrier layer 6 is positioned between the two portions (internal and external) of the barrier layer 5 and/or between two portions of the sealing layer 4. As such, the sealing is carried out by an alternation of several motifs. The intermediate barrier layer 6 comprises more preferably an insulating dielectric material. This intermediate barrier layer 6 can, for example, be an oxide, a nitride or a silicon oxinitride, an aluminum oxide or a titanium oxide deposited by CVD, PECVD or LPCVD. The intermediate barrier layer 6 is for example formed using lithographic or photolithographic techniques. The intermediate barrier layer 6 has a thickness or width according to the plane of the faces to be assembled, more preferably between 1 and 10 microns.

(36) The barrier layer 5 and the intermediate barrier layer 6 advantageously represent hermetic pillars of mechanical consolidation of the stack formed by the first support 1 and the second support 2. Due to their barrier properties, these partitions guarantee a lateral encapsulation of the component 3. Through its geometrical distribution, the sealing layer 4 covers, according to a preferred embodiment, the entire peripheral perimeter defined by the dimensions of the component 3. Such an arrangement of the sealing layer 4 effectively contributes to an increase mechanical robustness of the first support 1-second support 2 assembly. Preferably, there is no space between the barrier layer 5 and/or the intermediate barrier layer 6 and the sealing layer 4.

(37) According to a non-limiting embodiment of the invention, the first support 1 is a glass substrate, for example with a borosilicate or alumina-borosilicate base.

(38) A sealing layer 4 is then formed, of formula Li.sub.xP.sub.yO.sub.zN.sub.w by a technique of reactive sputtering, using a target of Li.sub.3PO.sub.4, under a gas 100% N.sub.2, in the following conditions: flow rate N.sub.2 of 100 sccm (standard cubic centimeter per minute), radiofrequency power density (RF) of 4 watts/cm.sup.2, deposition temperature of 150 C.

(39) A second support 2 is then deposited, for example a substrate made of silicon. Then a putting into contact of the first support 1 and of the second support 2 is then carried out in order to form a glass/silicon structure. Anodic bonding is then carried out at a voltage of 100 volts, under a temperature of 150 C.

(40) Phosphorus oxinitride glasses can have a variation in the thermal expansion coefficient according to their composition, in particular according to the function of the atomic percentage in nitrogen. This characteristic is implemented in the alternatives shown in FIGS. 5 and 6.

(41) FIG. 5 shows a first alternative consisting in carrying out a composition gradient in nitrogen in the thickness of the sealing layer 4 of formula Li.sub.xP.sub.yO.sub.zN.sub.w (for example by varying the flow rate of N.sub.2 during the deposition in the case of a vacuum deposition method). For example, it has been shown that an increase in the ratio N/P results in a decrease in the thermal expansion coefficient of glasses of the Li.sub.xP.sub.yO.sub.zN.sub.w type (Journal of Non-Crystalline Solids 181 (1995) 201-214). The thermal expansion coefficient can for example decrease more than 30% for a ratio N/P changing from 0 to 0.8). This composition gradient (which results in a gradient in terms of thermal expansion coefficient) can attenuate the differences in the thermal expansion coefficients between two different substrates taking place during the anodic bonding. According to this embodiment, at least one among the parameters x, y, z, w of the compound Li.sub.xP.sub.yO.sub.zN.sub.w changes in the thickness of the sealing layer 4.

(42) FIG. 6 shows a second alternative consisting in carrying out a sealing layer 4 that has at least two different compositions that translate at least two different thermal expansion coefficient on two different zones of a support 1 (for example, the center and the periphery of a wafer of silicon). This configuration makes it possible to carry out an anodic bonding between a first support 1, a second support 2 and a second additional support 22. According to an embodiment, a first sealing layer 4 assembles the first support 1 with a second support 2 and a second sealing layer 42 assembles the first support 1 with a second additional support 22. Preferably, the first sealing layer 4 and the second sealing layer 42 have different chemical compositions. Advantageously, the second sealing layer 42 comprises at least one layer of an ionic conductive material of formula Li.sub.xP.sub.yO.sub.zN.sub.w.

(43) Applying a suitable temperature and voltage makes it possible to seal, in a sustainable manner, the various devices, therefore carrying out a hermetic and robust assembly with an integration that offers a reduction in the encumbrance of the packaging.

(44) FIGS. 7a to 7c show a particular embodiment wherein a Li.sub.xP.sub.yO.sub.zN.sub.w layer is common to the sealing zone and to the electronic component present on one of the two substrates (for example the substrate 1 as in FIG. 7a)

(45) For example in the case of a micro-battery of an electrochromic component, a Li.sub.xP.sub.yO.sub.zN.sub.w layer is present in the stack and plays the role of an ionic conductor. The Li.sub.xP.sub.yO.sub.zN.sub.w layer can as such be deposited and structured at a single time as shown in the layer 4 deposited and having been subjected to removals in such a way as to form the desired patterns (by all typical means in particular by lithography or photolithography) and as such allows for a sealing that can be seen in FIG. 7c with a gain in terms of cost for the method. A portion of the Li.sub.xP.sub.yO.sub.zN.sub.w layers is therefore used for the sealing and at least one other is used for the formation of the component 3.

(46) The alternatives or options described in this portion stem directly from the description of the previous technological steps. They are valid for illustrative applications such as micro-batteries but can be transposed to other microelectronic components. Unless mentioned otherwise, the steps that describe the examples presented in each part are based on the same principles announced hereinabove. Particularly advantageously, the method of bonding according to this invention is suited for applications such as the hermetic sealing of sensitive components (in terms of resistance to temperature and electrical fields), for example, MEMS (acronym for Micro-Electro-Mechanical System), micro-batteries, electrochromic components, microsensors.