Interlocking circuit and procedure for blocking a data line

Abstract

An interlocking circuit and procedure for suppressing an echo on a receiving line are provided. The interlocking circuit blocks the receiving line when there is a signal on a transmission line. The receiving line has a transmission side at which the echo signal is located and a receiving side at which the echo signal can be blocked. The echo signal of a CAN driver is suppressed such that an actuating component for a headlamp light matrix does not receive any unwanted commands.

Claims

1. An interlocking circuit for suppressing an echo, the circuit comprising: a receiving line (Rx); a transmission line (Tx); wherein the receiving line is locked when there is a signal on the transmission line (Tx), where the receiving line has a first receiving side at which the echo signal is present as well as a second receiving side at which the echo signal is blocked; wherein a control signal derived from the signal on the transmission line is on a control line, where the control line is connected to an input of an inverter (INV), which has an output connected to an input of an OR gate for signals with negative logic or an AND gate for signals with positive logic, where a second input of the OR gate or the AND gate is connected to a transmission side of the receiving line and an output of the OR gate or the AND gate to the first receiving side or the second receiving side of the receiving line.

2. The interlocking circuit in accordance with claim 1, wherein a delay circuit (D1+R1+C1) influences the control signal (A) such that the interlocking circuit interlocks for a longer period than a period during which the signal is on the transmission line.

3. The interlocking circuit in accordance with claim 2, wherein the delay circuit connects the transmission line to the control line (A) via a diode and the control line to a supply voltage and a capacitor (C1) to the ground via a resistor (R1).

4. An interlocking circuit for suppressing an echo, the circuit comprising: a receiving line (Rx); a transmission line (Tx); wherein the receiving line is locked when there is a signal on the transmission line (Tx), where the receiving line has a first receiving side at which the echo signal is present as well as a second receiving side at which the echo signal is blocked; wherein a CAN driver generates the echo and is connected to the transmission line and the transmission side of the transmission line.

5. An interlocking circuit for suppressing an echo, the circuit comprising: a receiving line (Rx); a transmission line (Tx); wherein the receiving line is locked when there is a signal on the transmission line (Tx), where the receiving line has a first receiving side at which the echo signal is present as well as a second receiving side at which the echo signal is blocked; wherein at least one light matrix manager module is connected to the transmission line and the first receiving side or the second receiving side of the receiving line, where a minimum of one light matrix manager module transmits the signal to the transmission line.

6. The interlocking circuit in accordance with claim 5, wherein the interlocking circuit is positioned on a printed circuit board that also holds a CAN driver, a communication interface and the minimum of one light matrix manager module.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Reference is now made more particularly to the drawings, which illustrate the best presently known mode of carrying out the invention and wherein similar reference characters indicate the same parts throughout the views.

(2) FIG. 1 shows a communication architecture between a control device and light matrix management modules.

(3) FIG. 2 shows various architectures for connecting multiple light matrix management modules.

(4) FIG. 3 shows a block diagram for a CAN driver.

(5) FIG. 4 shows the measurement for the input and output of a CAN driver.

(6) FIG. 5 shows an implementation of the switches in the form of a circuit

(7) FIG. 6 shows a circuit logic for an interlocking circuit.

(8) FIG. 7 shows a measurement for the transmission delay of a leading edge.

(9) FIG. 8 shows a measurement for the transmission delay of a trailing edge.

(10) FIG. 9 shows a measurement with an interlock duration that is too short.

(11) FIG. 10 shows a delay circuit in conjunction with the interlocking circuit.

(12) FIG. 11 shows a signal measurement from FIG. 10.

(13) FIG. 12 shows a measurement of the communication between the CAN driver and light matrix management module while using the delay circuit in conjunction with the interlocking circuit.

(14) FIG. 13 shows an assembly variant for a printed circuit board.

DETAILED DESCRIPTION OF THE DRAWINGS

(15) FIG. 1 describes a design for a communication architecture between a control device (Master ECU (MCU)) and various light matrix management modules (LMMs).

(16) Here, an architecture is shown that allows for full duplex communication. The transmission output (Tx) for the MCU is connected to the receiving inputs (Rx) of all LMMs. The same applies to the transmission outputs (Tx) for all LMMs connected to the receiving inputs (Rx) of the MCU.

(17) One advantage of this arrangement is that it is inexpensive to implement as a solution. It may be the most inexpensive of all solutions presented here. This setup allows distances between the MCU and the LMMs of up to 50 cm or 70 cm to be bridged without impeding the EMC durability too significantly.

(18) FIG. 2 shows two different architectures.

(19) FIG. 2a shows a point-to-point (PtP) connection between an MCU and multiple LMMs arranged on a printed circuit board (PCB). Between the MCU and the printed circuit board, there is a cable connection over which it is preferable to implement a CAN or UN connection.

(20) There must be an internal clock available on each printed circuit board and this clock must be used to sense the UART communication signal. This is because there is no clock provided that is generated outside of the printed circuit board. For the PtP variant, only one pulse generator is necessary for the entire printed circuit board. The multiple LMMs have access to this pulse generator.

(21) For the PtP variant, the EMC susceptibility to interference can be improved by adding a totem pole push-pull output stage for the transmission signal (Tx) of the LMM.

(22) FIG. 2b shows a point-to-multipoint (PtM) connection between an MCU and several LMMs, all of which are arranged on a printed circuit board. There is a cable connection between the MCU and the various printed circuit boards that is ideally established using a CAN or UN connection. This can create a Y configuration, which consists of individual cables from the MCU to each printed circuit board (and, as a result, each LMM) or bus architecture in accordance with FIG. 1.

(23) The PtM variant requires several pulse generators (typically one for each printed circuit board). This can make the PtM variant more expensive than the PtP variant. The same is even more true of the increased current consumption generated by several pulse generators if they are operated with 5V instead of 3.3 V or communication is carried out using the higher of the two voltage types.

(24) The total pull-up resistor value must be observed in the PtM variant. When equipping the printed circuit boards, it may be necessary to select the pull-up resistor values based on the number of printed circuit boards to be connected. Depending on the type of circuit, the various pull-up resistors may be switched in parallel. This means that the resistor values should be selected so that they do not lie below a minimum value. For example, the total resistor value can be 1, 2 or 5 kiloohms.

(25) Certain applications, such as those in automobiles, require specific minimum data transmission rates that are subject to any applicable EMC influence. For example, data transmission rates of 500 kbps may be required at a cycle rate 16 times higher (corresponding to 8 MHz). This cycle rate may be too high for secure transmission and distribution via cable.

(26) The PtM variant can also be used in a single headlamp, but usually, each printed circuit board is responsible for a different function (such as the cornering light, high beam, low beam).

(27) FIG. 3 shows a block diagram of a CAN driver that provides conversion between the CAN signals on the left side and UART signals on the right side.

(28) In this drawing, it is important to note that the pin designated TxD is an input. This means that the Tx signal of the communication partner must be connected here.

(29) Likewise, the RxD pin identifies an output at which the CAN driver transmits data.

(30) A CAN driver or CAN-UART converter converts 5V (or 3.3 V) UART Tx and Rx signals into CAN CANH and CANL signals, which are known to consist of low voltage and differential signals. These types of signals can be transmitted more easily over longer distances. This is frequently achieved using twisted cables. The CAN driver also fulfills other automotive requirements, such as short circuit protection to the ground and on-board supply voltage (12 V).

(31) Unfortunately, these drivers generate a local echo. This forwards signals fed to the UART-side input (TxD) to the CAN side, at which point they reach the CANH and CANL. From there, they are transmitted to the receiver block, where they are made available to the UART-side RxD output.

(32) A microcontroller can suppress the echo by blocking the receive interrupt or even utilizing the echo signal by verifying that the received signal is the same as the transmitted signal.

(33) However, this process will probably interfere with the LMM and its internal state machine if the machine receives bit sequences from the echo that are not part of its architecture. In other words, this can cause the state machine of a connected LMM to malfunction if a message (data word) is sent to the LMM over the echo and if this message is not one that the LMM was expecting.

(34) FIG. 4 shows a measurement of a CAN driver where a signal (41) of the LMM is transmitted to the TxD input of the CAN driver and an echo signal (42) is generated at the RxD output of the CAN driver. There is a delay between the signals (in this case, approximately 100 Ns). Accordingly, an interlocking circuit must be dimensioned such that it locks before the beginning of the echo and this lock is not released until the echo disappears. In this example, this means that interlocking circuit must activate faster than 100 Ns after the leading edge of the TxD signal and, after the trailing edge, must block more than 100 Ns after the TxD signal deactivates.

(35) Two commercially available components for the CAN driver are recommended. As described in the data sheet, the TLE6250 features a transmission delay between 150 Ns and 280 Ns for both edges. As described in the data sheet, the TJA 1051 features a transmission delay of 40 Ns to 250 Ns.

(36) FIG. 5 shows the circuitry (wiring) of a CAN driver with an interlocking circuit.

(37) The IC1000, the CAN driver located in the center, conducts conversions between the left CAN signals (CANH, CANL) and right serial UART signals (RxD, TxD).

(38) There are components between the CAN inputs/outputs and the CAN driver that are the basic wiring for interference suppression, e.g. a L1000 bifilar inductor or R1000, R1001 resistors for the bus end termination.

(39) The D1001, R1002, C 1002 components are used as a delay element unlocking in accordance with FIG. 10.

(40) The IC1001 component is used for logical wiring for blocking the receiving line in accordance with FIG. 6.

(41) It is worth noting again that, from the perspective of the CAN driver, the cable designated TxD that transmits the data from the connected LMM to the CAN driver is an input despite what the designation indicates.

(42) In FIG. 6, a circuit logic is recommended that provides a logic function for 0 active levels (negative logic) in accordance with the Rx formula=(NOT A) OR B, where A is a control signal that, when it is active, blocks signal B. The control signal is derived from the transmission signal and, in the simplest cases, these signals are identical.

(43) Signal B is the transmission-side Rx receiving line (from CAN Rx), i.e. the RxD output signal from the CAN driver.

(44) In a hardware configuration, the control line containing the control signal is connected to the input of an inverter (INV), whose output is connected to one of two inputs of an OR gate. The second input is connected to the transmission side of the receiving line (from CAN Rx), e.g. the RxD pin of the CAN driver. The output of the OR gate is connected to the receiving side of the receiving line (to LMM Rx), e.g. the Rx pin of the LMM(s).

(45) It should also be mentioned that this interlocking circuit does not have a direct connection between the RxD output of the CAN driver (from CAN Rx) and the Rx input of the LMM component (to LMM Rx), but instead a connection is simply established using the gate such that it can be used for locking (if necessary). Otherwise, the Tx transmission line can directly connect the two components from from LMM Tx to to CAN Tx.

(46) The preceding circuit is suitable for signals with negative logic (0-active logic). If there is positive logic, meaning that the bit value (1) is generated by a high level, the OR gate must be replaced by an AND gate to ensure that the interlocking function is identical.

(47) This logic function can be creating using configurable multifunction gates such as the 74LVC1G57, 74LVC1G97 and 74LVC1G98 components.

(48) The 74LVC1G57GW-Q100 is ideal because it is affordable and qualified for automotive applications.

(49) FIGS. 7 and 8 show the transmission delays for these logic circuits, which have switching times of less than 8 Ns, making them fast enough to block the receiving line before the CAN driver receives the echo.

(50) Curves 71 and 81 show an A or Tx input signal in the logic circuit, while curves 72 and 82 show the resulting output signal.

(51) FIG. 7 shows the curve progression for the leading edge, while FIG. 8 shows this curve progression for the trailing edge.

(52) FIG. 9 depicts the issue of the interlocking circuit switching in time before the leading edge of the echo (in accordance with FIG. 6), but not waiting until after the end of the echo to unlock again. In this case, the interlock would have to remain active for 280 Ns after the end of the signal in the transmission line in accordance with the measurement.

(53) In signals with negative logic, the leading edge is falling (from high to low level) and the trailing edge rising (from low to high). In signals with positive logic, the reverse is true.

(54) Signal 91 is the signal present in the Tx transmission line, i.e. the TxD input signal of the CAN driver. The echo signal (92) that appears on the transmission side of the Rx receiving line is the output signal of the CAN driver. Signal 93 shows the unwanted part of the echo which would have still been let through because an exclusively available circuit in accordance with FIG. 6 would not be locked long enough.

(55) FIG. 10 shows a circuit that causes a delay in disabling the control signal for locking; in other words, a time delay with a time delay constant.

(56) A D1, D1001 diode is switched in the reverse direction between the transmission line and control line. Its cathode side faces the transmission line and its anode side faces the control line. This means that if the Tx is a high level, the diode locks. If it is a low level, it allows energy to pass through. This ensures that a falling edge of the Tx signal that corresponds to the leading edge in negative logic is transmitted immediately to the control signal. Conversely, a rising edge locks the diode, which then makes the control signal dependent on the other components.

(57) Control line A is connected to the Vcc supply voltage via an R1, R1002 resistor and to ground with a C1, C1002 capacitor. The capacitor discharges a low level of the Tx signal via the diode which is then switched in the forward direction. Otherwise, the capacitor discharges from the low to high level at a speed that corresponds to the component values. The switchover point of the control signal is determined by the switching level (e.g. Vcc/2). The time constant is determined by the resistor and capacitor value.

(58) From this point, the downstream logic circuit would switch from the inverter (INV) and OR gate. This was presented in FIG. 6.

(59) FIG. 11 shows a measurement of the signals. v(a) is the measurement of the analog Tx signal, v(b) the measurement of the analog control signal, v(c) the measurement of the digital control signal and v(d) the measurement of the digital Tx signal.

(60) An alternating 0-1 bit sample is used for this measurement, as can be seen when looking at the equidistant edges of the digital Tx signal v(d). The digital control signal that shows the durations of active locking now has a delay and is activated again after the trailing edge of the Tx signal. As such, the unwanted remainder of the echo signal shown in FIG. 9 can now also be suppressed.

(61) Optionally, other components that carry out other or improved functions may lie along the signal paths between the described components. For example, signal driver stages can still be installed between the Tx cable and diode or the RC element and logic circuit.

(62) The time constant of this measurement is selected to ensure that it corresponds to half the duration of a bit (approx. 500 Ns). This permits enough tolerance for the required delay and activates the interlocking circuit again when the stop bit is generated, enabling communication without limitations to the chronological sequence. The receive channel is reactivated to receive more communication from the MCU right after locking.

(63) FIG. 12 shows communication between an MCU and an LMM via a CAN driver in which the interlocking circuit is used in accordance with FIG. 10. Here, a data word is transmitted from the MCU to the LMM, which then responds by transmitting a data word to the MCU.

(64) Signal 121 is the bit sample that is transmitted from the MCU to the LMM via the receiving line (Rx) of the CAN driver and can contain a request to the LMM to transmit this data. This signal is measured on the receiving side of the LMM, i.e. downstream from the output of the interlocking circuit gate.

(65) Conversely, signal 123 is the receiving line signal, but is measured on the output side of the CAN driver. Here, the echo in the right half of the measurement that resulted from the Tx signal is visible.

(66) Signal 122 shows the aforementioned Tx signal on the signal line, which may be, for example, the requested data that the LMM transmits to the MCU or CAN driver.

(67) As such, the inventive circuit was used to suppress the echo of the response from the LMM.

(68) FIG. 13 shows a configuration variant for a printed circuit board that permits configuration in accordance with the circuit from FIG. 5, as indicated by the crossed-out components in the figure. However, an alternative configuration is shown here in cases where CAN communication is not carried out between the MCU and LMM, but direct UART communication is used instead.

(69) Essentially, the ST1-T or CANH output pin is simply connected to the UART-side Tx via the R1010 resistor with the R1008 pull-up. Likewise, the ST1-Rx or CANL input pin is simply connected to the UART-side Rx via the R1013 resistor with R1009 pull-up. A short circuit in place of contact resistors is also conceivable.

REFERENCE NUMERAL LIST

(70) MCU Master ECU, control unit Tx Transmit pin, transmission line Rx Receive pin, receiving line TPS92661 Light matrix management module, type TI TPS92661 LMM Light matrix management module CANH Can high connection CANL Can low connection Vcc Supply voltage TxD Connection for transmission line, input in CAN driver RxD Connection for receiving line, output from CAN driver 41 Signal to transmission line 42 Signal to receiving line (here, echo) D1000, Components for CAN input circuit C1000, R1000, R1001, L1000 IC1000 CAN driver D1001, (D1), Components for delay circuit R1002, (R1), C1002, (C1) IC1001 Logic component A Control signal B, Transmission-side receive signal from CANRx toCANRx Receiving-side receive signal INV Inverter OR OR gate 71 Input signal of a logic component of a leading edge 72 Output signal of a logic component of a leading edge 81 Input signal of a logic component of a trailing edge 82 Output signal of a logic component of a trailing edge 91 Transmission signal to toCANTx 92 Receive signal to fromCANRx 93 Remaining echo signal to toLMMRx toCANTx Transmission line connection to CAN driver fromLMMTx Transmission line connection to LMM v(a) Measurement of the analog transmission signal v(b) Measurement of the analog control signal v(c) Measurement of the digital control signal v(d) Measurement of the digital transmission signal 121 Bit sample signal from MCU to LMM (request) 122 Bit sample signal from LMM to MCU (reply) 123 Signal at the RxD output of the CAN driver R1010, Contact resistors R1013 R1008, Pull-up resistors R1009