Wafer-based charged particle accelerator, wafer components, methods, and applications

Abstract

A wafer-based charged particle accelerator includes a charged particle source and at least one RF charged particle accelerator wafer sub-assembly and a power supply coupled to the at least one RF charged particle accelerator wafer sub-assembly. The wafer-based charged particle accelerator may further include a beam current-sensor. The wafer-based charged particle accelerator may further include at least a second RF charged particle accelerator wafer sub-assembly and at least one ESQ charged particle focusing wafer. Fabrication methods are disclosed for RF charged particle accelerator wafer sub-assemblies, ESQ charged particle focusing wafers, and the wafer-based charged particle accelerator.

Claims

1. A wafer-based charged particle accelerator, comprising: a first RF charged particle accelerator wafer sub-assembly comprising a wafer, the wafer defining an orifice through which a charged particle beam can travel, the wafer further having electrical isolation between a first electrically conductive electrode disposed on a first side of the wafer and a second electrically conductive electrode disposed on an opposing second side of the wafer to form an electric field interacting with the orifice so that a charged particle beam traveling through the orifice will encounter an electric field generated by the first electrode and second electrode; and RF voltage-generating electronics disposed on the wafer.

2. The wafer-based charged particle accelerator of claim 1, further comprising: a power supply operatively coupled to the first RF charged particle accelerator wafer sub-assembly.

3. The wafer-based charged particle accelerator of claim 1, wherein the second electrode is in the form of an RF resonator configured as either a) a thin film inductor in series with an air gap capacitor, or b) a coplanar waveguide resonator, so as to transform a low voltage on the wafer to a high voltage on the second side of the wafer.

4. The wafer-based charged particle accelerator of claim 3, further comprising a beam current-sensor.

5. The wafer-based charged particle accelerator of claim 4, wherein the beam current-sensor is disposed in the wafer.

6. The wafer-based charged particle accelerator of claim 4, wherein the beam current-sensor is disposed on another wafer disposed in a drift space.

7. The wafer-based charged particle accelerator of claim 6, further comprising: a second RF charged particle accelerator wafer sub-assembly comprising a wafer, the wafer defining an orifice through which a charged particle beam can travel, the wafer further having electrical isolation between a first electrically conductive electrode disposed on a first side of the wafer and a second electrically conductive electrode disposed on an opposing second side of the wafer to form an electric field interacting with the orifice so that a charged particle beam traveling through the orifice will encounter an electric field generated by the first electrode and second electrode; and at least one ESQ charged particle focusing wafer.

8. The wafer-based charged particle accelerator of claim 7, wherein the at least one ESQ charged particle focusing wafer comprises an electrically insulative wafer or planar wafer having at least one through-hole, each through-hole providing a beam path to focus the charged particle beam, each through-hole having at least four electrodes disposed at the inner perimeter of the through-hole, where each electrode further comprises one of a) exposed areas of the wafer covered by a conductive material in selected areas to form an electric field distribution to focus the charged particle beam, and b) conductive pillar-like structures coupled to insulating connectors, connected to the wafer, linearly aligned with the RF charged particle accelerator wafer sub-assemblies.

9. The wafer-based charged particle accelerator of claim 8, wherein the conductive pillar-like structures comprise a solid rod or a hollow cylinder.

10. The wafer-based charged particle accelerator of claim 9, further comprising a feedback circuit to receive an output from the beam current-sensor and to modify control voltages of the first electrode and the second electrode to focus the charged particle beam.

11. A wafer-based charged particle accelerator for use with a charged particle source, comprising: at least one RF charged particle accelerator wafer sub-assembly comprising a wafer having electrical isolation between at least a first and a second electrically conductive electrode; and a RF voltage-generating electronics disposed on the wafer; wherein at least the first and the second electrode are disposed on respective and opposing first and second sides of the wafer to create an electric field, wherein the wafer has one or more orifices through which a charged particle beam can travel, encountering the electric field generated by the at least first and second electrode, and wherein the second electrode is in the form of an RF resonator.

12. The wafer-based charged particle accelerator of claim 11, further comprising: a power supply operatively coupled to the at least one RF charged particle accelerator wafer sub-assembly.

13. The wafer-based charged particle accelerator of claim 11, wherein the RF resonator is configured as a thin film inductor in series with an air gap capacitor to transform a low voltage on the wafer to a high voltage on the second side of the wafer.

14. The wafer-based charged particle accelerator of claim 11, wherein the RF resonator is configured as a coplanar waveguide resonator to transform a low voltage on the wafer to a high voltage on the second side of the wafer.

15. The wafer-based charged particle accelerator of claim 11, further comprising a beam current-sensor.

16. The wafer-based charged particle accelerator of claim 15, further comprising a feedback circuit to receive an output from the beam current-sensor and to modify control voltages of the first electrode and the second electrode to focus the charged particle beam.

17. A RF charged particle accelerator wafer sub-assembly comprising a wafer defining an orifice through which a charged particle beam can travel, the wafer further electrical isolating a first electrode disposed on a first side of the wafer and a second electrode disposed on an opposing second side of the wafer, the first electrode and the second electrode operatively forming an electric field interacting with the orifice so that a charged particle beam traveling through the orifice will encounter an electric field generated by the first electrode and second electrode.

18. The RF charged particle accelerator of claim 17, further comprising a beam current-sensor.

19. The RF charged particle accelerator of claim 18, further comprising a feedback circuit to receive an output from the beam current-sensor and to modify control voltages of the first electrode and the second electrode to focus the charged particle beam.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 schematically illustrates top, cross section, and bottom views of some structures used for implementation of ESQ and RF wafers including insulated holes, holes with sidewall metal coatings, holes with partial sidewall metal coatings, metal-filled vias, as well as top and bottom patterning for routing of electrical signals and contact to sidewall metals, or vias, according to exemplary aspects of the invention.

(2) FIG. 2 schematically illustrates (left stack) a PCB built using methods known in the art and (right stack) fabrication of ESQ wafers using an additional drilling step to selectively remove metal on certain parts of the via as dictated by the drill contour path, according to an exemplary aspect of the invention.

(3) FIGS. 3A-3G schematically illustrate the process steps for fabricating ESQ wafers using PCB machining with a laser tool, according to an exemplary embodiment of the invention.

(4) FIG. 4 schematically illustrates the process steps for fabricating ESQ wafers using glass micromachining, according to an exemplary aspect of the invention.

(5) FIG. 5 (steps 1-11) schematically illustrate ESQ wafer assembly (i.e., two stacked ESQ wafers) fabrication process steps using a silicon wafer, according to an exemplary aspect of the invention.

(6) FIGS. 6A-6H (steps a-h) schematically illustrate a single ESQ wafer fabrication process, according to an exemplary aspect of the invention.

(7) FIG. 7 pictorially shows different views and details of an ESQ wafer and a single ESQ unit cell, according to an exemplary aspect of the invention

(8) FIG. 8 schematically shows the overall architecture and unit cell structure of a MEMS based MEQALAC, according to an exemplary embodiment of the invention.

(9) FIG. 9A schematically illustrates a 3D view of an inductor-capacitor (LC tank circuit) resonator design; FIG. 9B a picture of the assembled fabricated LC resonator where the top PC-board electrode is attached to the bottom using insulating plastic bolts, where a bottom wafer can have a spiral inductor connected to the capacitor formed between the bottom wafer and the top ground wafer. The graph shows the resonance of the LC tank at about 12 MHz demonstrating quality factors of 20-30. FIG. 9C shows the equivalent circuit of the LC tank demonstrating a passively increased voltage across the air gap, according to exemplary embodiments of the invention.

(10) FIG. 10A schematically illustrates a 2D view of a single RF acceleration unit cell using four wafers; FIG. 10B: a 3D view of the assembled single RF acceleration unit cell, according to an exemplary embodiment of the invention.

(11) FIGS. 11A-11F: Coplanar waveguide resonator accelerator wafer: FIG. 11A a coplanar waveguide resonator is formed on the accelerator wafer with orifices for the charged particle beams to pass through, such that nodes and antinodes of the voltage provide passive voltage magnification; FIG. 11B shows that a single wafer provides the electrodes to accelerate particles through it nodes and antinodes of the CPS resonator; FIG. 11C shows the conceptual sketch of the CPW resonator; FIG. 11D shows the physical implementation of a CPW resonator for the accelerator wafer; FIG. 11E Stacks of a CPW resonator and a ground wafer can also be used to form an accelerator section; FIG. 11F two accelerator structures can be stacked to form a complete accelerator sub-unit with ground potentials at input and output. One side of the wafer is grounded while the opposite side has a high voltage owing to the CPW resonance. Two such wafers are formed to form a drift space between the two wafers and the two active high voltages are in phase to not accelerate or deaccelerate in the drift space. The second wafer accelerates the beam again as the phase of the voltages have changed such as to provide an electric field in the desired direction of acceleration.

(12) FIG. 12 schematically and graphically shows simulation results with xenon ion beam energy gain along a lattice of ESQs and 12 RF gap assemblies, according to an illustrative embodiment of the invention.

(13) FIG. 13 schematically and graphically shows early simulations of ion acceleration in an RF gap assembly.

(14) FIG. 14 schematically illustrates pulsed operation of the accelerator cell, according to an exemplary embodiment of the invention.

(15) FIG. 15A is a photo of an assembled stack of four PCB based RF wafers for demonstrations of multi-beamlet transport and acceleration; FIG. 15B is a schematic of an RF circuit for beam acceleration in the stack of four wafers; FIG. 15C is a photo of an assembled stack of six ESQ wafers (grey) that match the ion beam from an ion source into the accelerator structure and a series of four RF acceleration wafers as in FIG. 15B, two ESQ wafers and another four RF acceleration wafers, according to illustrative embodiments of the invention.

(16) FIG. 16 shows a current trace of ions injected in a 33 beamlet pattern into the RF wafer stack, before the RF was turned on.

(17) FIG. 17 schematically illustrates an RF wafer assembly for accelerating ions, according to an exemplary embodiment of the invention.

(18) FIG. 18 graphically shows a plot of ion currents vs. retarding field for a series of RF power conditions.

(19) FIG. 19 schematically illustrates an ESQ wafer assembly for focusing ions, according to an exemplary embodiment of the invention.

(20) FIG. 20: Camera image showing nine beamlet apertures, we see light emitted from a scintillator following pulsed ion beam impact.

(21) FIG. 21 shows photos of the mounted ESQ wafer and the 33 beamlet pattern fabricated using a PC board process.

(22) FIG. 22 top: shows a photo of the beamlet pattern in the ESQ (top left insert) and overlay of focusing patterns from application of +100 V and then 100 V. The expected pattern from ideal ESQs and envelope calculations of our geometry and bias conditions is a cross of two ellipses; bottom: images of beamlet patterns for a 33 array of beamlets for two ESQ voltages showing focusing in two perpendicular directions.

(23) FIG. 23 shows an example of envelope calculations of expected ESQ focusing. For an ESQ bias of 100 V the initially round beamlets are focused to ellipses.

(24) FIG. 24 show examples where the leakage currents across ESQs and across the PCBs was very low due to improved surface treatment after laser processing and fabrication of ESQ structures.

DETAILED DESCRIPTION OF EXEMPLARY, NON-LIMITING EMBODIMENTS OF THE INVENTION

(25) Both Electrostatic Quadrupole (ESQ) wafers and RF wafers for a wafer-based charged particle accelerator include an insulating wafer substrate with one or more of insulated holes, holes with sidewall metal coatings, holes with partial sidewall metal coatings, metal-filled vias, as well as top and bottom patterning for routing of electrical signals and contact to sidewall metals or vias. Insulated substrates may include printed circuit boards (PCBs; e.g., FR4), glass with Through-Glass-Vias (TGVs), and silicon, as well as 3D printed structures.

(26) Different versions of ESQ and RF wafers with different performance vs ease of fabrication tradeoffs may require implementation of one or more of the following structures on an insulating substrate, some of which are illustrated in FIG. 1: through-holes with metal coated or insulating sidewalls 101; through-holes with partially metal coated or insulating sidewalls 102; through-holes with closely spaced metal vias (10 nm-200 m) 103; top and bottom metals layers for electrical signal routing and contact to vias or sidewall metals of the through-holes 104.

(27) In addition, the substrate should allow high-breakdown fields so that large voltages (>1 kV) can be applied across adjacent metal, via, and sidewall-metal structures to help with electrostatic focusing, guiding, or acceleration of charged particles. The metal thickness is chosen to minimize resistive losses at RF frequencies associated with direct resistance and skin effects. Aspect ratios, gaps, and thickness of the substrate will depend on the particular device and the choice of fabrication, each introducing potential cost and performance tradeoffs. We describe five (i-v) different fabrication approaches for the embodied RF and ESQ wafers.

(28) (i) Fabrication of ESQ and RF Wafers Using PCB Machining and Contour Routing with a Drill Bit

(29) Two-sided printed circuit boards (PCB's) can be machined by a combination of drilling, contour routing, electroless plating, electroplating, lamination, photolithography, and etching, well known to those skilled in the art. In the embodied method, due to the inherent nature of electroless plating, all the sidewalls of vias are covered with metal, since regular PCBs used in electronics only require vias with all sidewalls metal-coated. However, ESQ wafers require removal of metal sidewalls in certain parts of the via. This may be realized by traversing a drill bit over a contour that overlaps with the boundary of the sidewalls over which metal needs to be removed. This process is summarized in FIG. 2, in which the left stack shows a PCB that can be built using methods known in the art; the right stack illustrating fabrication of ESQ wafers using an additional drilling step to selectively remove metal on certain parts of the via as dictated by the drill contour path. After the contour routing is done, part of the sidewall in the circular metal is free of metal, while part of it remains metallized.

(30) (ii) Fabrication of ESQ and RF Wafers Using PCB Machining with Laser

(31) Compared to what is available from a standard two layer PCB fabrication process, there are additional requirements for ESQ and RF wafers. As RF wafers do not require sidewall metal coating, their fabrication process is simpler compared to the process for ESQ wafers. Since any process to fabricate an ESQ wafer can also be used to fabricate an RF wafer, we illustrate the fabrication steps for an ESQ wafer, which in general may require: (1) non-circular vias; and (2) partially metal-coated sidewalls. Both of these aspects can be accommodated using a laser cutter (e.g., LPKF ProtoLaser U, which removes copper or FR4 material by abrasion. Using laser micromachining, top and bottom metal layers can be patterned and holes can be made through the board. Alignment between top and bottom is achieved by using an integrated vision system and pre-fabricated alignment fiducials. Furthermore, by using the integrated camera of the tool, top and bottom layers can be registered for alignment. Main steps of an exemplary process to fabricate an ESQ wafer are illustrated in FIGS. 3A-3G. In this process, the starting FR4 based board (double clad, 0.028, 1 oz. FR4 board that is cut in the shape of a 4 inch wafer) has copper on both sides as seen on the top cross section in FIG. 3A. In FIG. 3B holes are cut into the PCB using the laser tool. As the holes in the PCB's are created using a scanned laser beam rather than a milling tool, arbitrary hole shapes can also be easily realized. For ESQ wafers only, after the definition of holes, metal (e.g., Cu) is evaporated in a conformal evaporator with a rotating chuck system on both sides (typically 1-2 m; e.g., 500 nm), as per FIGS. 3C and 3D. The metal may be electroplated from both sides for better coverage of the sidewalls. In FIG. 3E the wafer is isolation cut with the laser to remove part of the sidewall over which no metal is desired (only for the ESQ process). In FIG. 3F the top metal layer is patterned using the laser after alignment with fiducials. In FIG. 3G the bottom metal is patterned after alignment with fiducials.

(32) (iii) Fabrication of ESQ and RF Wafers Using Glass Micromachining and Through-Glass Vias

(33) Instead of FR4, glass may be used as the insulating substrate with Through-Glass-Vias (TGV). This allows fabrication on a low cost substrate with smaller features than what might be possible with PCB fabrication. Furthermore, high vacuum compatibility of glass and high breakdown voltages are advantageous. The basic steps of the process flow are illustrated in FIG. 4. First, arbitrary shaped through-holes are laser machined (left panel). Then parts of the holes that will form the vias are filled with a conductive slurry/epoxy through a stencil mask and cured (venter panel). Next, top and bottom metallizations are done for routing either through physical vapor deposition and/or electroplating (right panel).

(34) (iv) Fabrication of ESQ and RF Wafers Using Silicon Micromachining

(35) FIG. 5 schematically illustrates ESQ (and RF acceleration structure) fabrication process steps (1-11) on a silicon wafer. Using this technique the fabrication of RF wafers is relatively simple, as they consist of arrays of through holes where each hole is surrounded by a ring of metal. For an ESQ wafer the fabrication process is started with highly doped silicon wafer (for example 100 mm, 4 in, resistivity=0.005-.020 Ohm cm, thickness 490-510 m). The doped silicon wafer is oxidized and coated with silicon nitride for electrical isolation. To supply the high voltages into the ESQ, the deposited oxide and nitride layers are patterned and a metal layer is deposited onto the electrode pillar regions (step 5). After forming metal contacts, the pillar structures are fabricated using Deep Reactive Ion Etching (DRIE) (step 8). Finally, to develop an ESQ unit cell, two wafers are bonded using an intermediate metal layer (step 11). These ESQ unit cells stand only on the oxide and nitride layers; hence, the electrical breakdown voltage of the oxide and nitride stack layer is an important parameter to determine the operating voltage of the ESQ unit cell. In an exemplary aspect, 1 m oxide and 2 m silicon nitride layers have been deposited and withstood a breakdown voltage of 3000 V (V=Ed, V=Breakdown voltage, E=Dielectric strength [10.sup.9 V/m for both oxide and nitride] and d=3 m, thickness [Oxide=1 m and Nitride=2 m]).

(36) FIGS. 6A-6H (steps a-h) schematically illustrate a single ESQ wafer fabrication process, according to an exemplary aspect of the invention. FIG. 6A shows a LPCVD nitride and oxide coated highly doped silicon wafer; FIG. 6B: the oxide and nitride is patterned for metal deposition; FIG. 6C metal is selectively evaporated onto the patterned surface; FIG. 6D PECVD oxide on back side (stop layer for DRIE); FIG. 6E the front side oxide and nitride is patterned; FIG. 6F the front side is deep-reactive ion-etched (DRIE); FIG. 6G the PECVD oxide is removed to make a through-aperture; FIG. 6H wire bonding.

(37) FIG. 7 pictorially shows different views and details of an ESQ wafer and a single ESQ unit cell, according to an exemplary aspect of the invention.

(38) (v) Fabrication of ESQ and RF Wafers Using 3D Printing

(39) ESQ wafers and RF wafers can also be fabricated by 3D printing. An advantage of 3D printing is the ability to form structures with small 3D features such as protrusions and holes in a low cost dielectric polymer substrate. In one implementation, the ESQ electrode diameter is 1 to 2 mm and the minimum feature size achievable in 3D printing is 50 to 100 m. For ESQ structures, one implementation is to form two of the required four electrodes that constitute an ESQ in the polymer substrate on two separate wafers. The top surface of the polymer wafers is then coated with a few micron thick layer of, e.g., copper, which also coats the sides of the cylindrical ESQ electrodes. Two copper coated wafers with two ESQ electrodes of the same polarity per beamlet are then stacked together to form the finished ESQ wafer with the selected number of ESQs.

(40) RF (or wafers that provide high voltage pulses) for ion acceleration consist of holes for beams to transvers and rings of metal electrodes on a dielectric substrate. The arrays for holes can also be formed by 3D printing. Metal electrodes can be formed by (local) metal coating of rings around the electrodes.

(41) FIG. 9A schematically illustrates a 3D view of an inductor-capacitor (LC tank circuit) resonator design; FIG. 9B a picture of the assembled fabricated LC resonator where the top PC-board electrode is attached to the bottom using insulating plastic bolts, where a bottom wafer can have a spiral inductor connected to the capacitor formed between the bottom wafer and the top ground wafer. The top wafer can be affixed to the bottom wafer using insulating bolts. The graph shows the resonance of the LC tank at about 12 MHz demonstrating quality factors of 20-30. FIG. 9B shows the electric field lines from the bottom wafer to top wafer that can accelerate the charged particles. FIG. 9C shows the equivalent circuit of the LC tank demonstrating a passively increased voltage across the air gap, according to exemplary embodiments of the invention.

(42) FIG. 10A schematically illustrates a 2D view of a single RF acceleration unit cell using four wafers; FIG. 10B a 3D view of the assembled single RF acceleration unit cell, according to an exemplary embodiment of the invention.

(43) FIGS. 11A-11F illustrates a coplanar waveguide resonator accelerator wafer. In FIG. 11A a coplanar waveguide resonator is formed on the accelerator wafer with orifices for the charged particle beams to pass through, such that nodes and antinodes of the voltage provide passive voltage magnification. FIG. 11B shows that a single wafer provides the electrodes to accelerate particles through it nodes and antinodes of the CPS resonator. FIG. 11C shows the conceptual sketch of the CPW resonator. FIG. 11D shows the physical implementation of a CPW resonator for the accelerator wafer. FIG. 11E shows stacks of a CPW resonator and a ground wafer can also be used to form an accelerator section. FIG. 11F shows two accelerator structures stacked to form a complete accelerator sub-unit with ground potentials at input and output. One side of the wafer is grounded while the opposite side has a high voltage owing to the CPW resonance. Two such wafers are formed to form a drift space between the two wafers and the two active high voltages are in phase to not accelerate or deaccelerate in the drift space. The second wafer accelerates the beam again as the phase of the voltages have changed such as to provide an electric field in the desired direction of acceleration.

(44) Based on the beam dynamics simulations with WARP3D and beam envelope codes, we have designed and are developing RF (radio-frequency)-acceleration wafers and ESQ (electrostatic quadrupole) wafers. We have tested ESQ and RF wafers and have achieved ion acceleration in a 33 beamlet array with a stack of RF wafers, accelerating argon ions (12 A total current per beamlet) from 10 keV to about 11.7 keV. High voltages for incremental acceleration of charged particles can be provided by RF or by high voltage pulses (e.g., from power transistors).

(45) Simulations of MEQALAC Structures

(46) FIG. 8 shows a schematic of the overall architecture and unit cell structure of a MEMS wafer-based charged particle accelerator. It is constructed by stacking of ESQ and RF wafers and driving them by DC and RF voltages of appropriate phases, respectively. FIG. 8 also illustrates the multi-pixel structure of the wafers. The figure inset shows a 22 array of pixels each for a charged beamlet for simplicity. Microfabrication allows packing of a large number of pixels on a single wafer along with electronics and sensors to monitor the beam distribution and intensity.

(47) Our modeling run included six RF stages (i.e., 12 acceleration gaps) and ESQ doublets between each of the RF stages. We started with a matched injection condition that we had calculated with beam envelope codes (vs. particle-in-cell simulations with WARP, which are more computationally demanding). We calculated and optimized the phase offset and RF-gaps (RF-gap=/2; where is the ratio of ion velocity divided by the speed of light and is the RF wavelength). We also increased the ESQ value by 2% between each gap. The simulations are for xenon ions (Xe.sup.1+), injected with 40 keV from an ion source, where a realistic beam emittance from our multi-cusp type plasma ion source is assumed. The current per beamlet is 20 N A, with a 40 m beam radius in an aperture (or beamlet channel) with a radius of 90 m. The simulations (FIG. 12) show acceleration from 40 keV to 87 keV over a distance of 28 cm, or 4.3 kV per RF gap, which is 86% of the applied RF peak voltage.

(48) We tracked ion loss and found transmission of 85% of ions. Most losses occur right after injection and losses in later cells are below 1% per cell. Based on past experience with injecting and matching symmetric beams to an alternating gradient focusing lattice, we expect to significantly reduce the initial particle loss by tuning the strength of the first 4-6 electrostatic quadrupoles. Although the simulations were performed with xenon, first beam experiments are being conducted with argon, which is much lower in cost compared to xenon.

(49) In earlier simulations of single gaps, illustrated in FIG. 13, ions move from left to right and the horizontal axis, Z (mm), is in mm. The vertical axis, X (mm), is also in mm and shows the dimension perpendicular to the beam propagation. On the right the RF voltage is shown in false color (the color scale is close to the vertical axis). In the bottom row, the kinetic energy of ions, E.sub.kin, is shown expressed as beam potential in kV for a series of positions of the beam bunch in the RF structure. Ions are injected at 20 kV and gain energy as they enter (left to right) and then transmit the RF structure. Here, the horizontal scale is expanded in the four panels in the bottom row to highlight the change in ion energy along the RF structure. The main result shown is that in this geometry ions gain about 5 kV in two steps, when entering and then when exiting the RF gap.

(50) The simulations also show that under these specific conditions we implemented an energy tilt on the ions in the bunch and this could be optimized for drift compression if desired.

(51) Continuous wave (RF) operation of the MEQALAC requires a large, external high voltage source. The accelerator can also be operated in pulsed mode. This approach requires feedback and relies on detection of the incoming beams and switching of accelerating voltages with electronically adjusted delays. This approach is illustrated in FIG. 14. As illustrated, the incoming beam is detected by charge monitoring systems, and is used to trigger the accelerating voltages after electronically adjusted delays so that the particles see accelerating voltages during their time in accelerating gaps. This approach offers the advantage that an external, high voltage source can be eliminated with necessary accelerating voltages supplied internally.

(52) Operation of Accelerator Structures from the PCB Process

(53) RF Acceleration

(54) We assembled a stack of four RF wafers and mounted them in a vacuum chamber together with an ion source for first beam tests. We tested the multi-cusp plasma ion source and extracted about 26 A of argon beam (Ar.sup.1+) per beamlet from a 33 array of beamlets. In these first PCB beamlet structures, the beamlet diameter is of order 1 mm.

(55) FIG. 15A shows the assembly of the four PCB RF wafers with 33 beamlet array through which the beam is transported. We applied RF HV pulses to demonstrate RF acceleration and observed an energy gain of about 1 to 2 kV. As illustrated in FIG. 15B, which schematically shows an RF circuit for beam acceleration in the stack of four wafers, ions are accelerated between the first wafer (at ground) and the second (at RF HV), ions then drift for a distance matched to /2, then they are accelerated a second time between the RF biased wafer and the forth wafer at ground. FIG. 15C is a photo of an assembled stack of six ESQ wafers (grey) that match the ion beam from an ion source into the accelerator structure and a series of four RF acceleration wafers as in FIG. 15B, two ESQ wafers and another four RF acceleration wafers

(56) FIG. 16 shows a current trace of Ar.sup.1+ ion current during a 4 us pulse where ions are transported through a 3>3 beamlet array in a stack of four RF wafers, but without RF voltage applied. The injection bias is 12 kV and the total beam current is 240 A. A Faraday cup was mounted right after the RF wafer stack for current measurements. We have a broad range of control over the plasma on time and ion extraction pulse length.

(57) Using the setup shown in FIG. 17, pulses of argon ions were injected into the RF wafer assembly and ion acceleration was observed. A retarding field was applied to a high transmission grid to measure the ion beam kinetic energy. This was first run with the RF off and repeat voltage scans on the grid with varying RF power levels. We observed transport of ions that were accelerated by 0.7 kV (low RF power level) and up to 1.7 kV (high RF power level). RF HV is applied from an off-board tank circuit through a low capacitance cable to the wafer stack as shown in FIGS. 15A-15C.

(58) The plasma ion source has a three grid extraction system. A floating grid, followed by a grid that is biased at 2 kV with respect to the source body. The following electrode is held at +1 kV when no ions are extracted and the potential is lowered to approx. 3 kV during extraction (also with respect to the source body). For the following runs, we biased the source at 10 kV. The RF wafer stack consists of four wafers. The first and last are grounded and the second and third are connected to the RF. We went with this layout, since a) the vacuum gap between wafer 1 and 2 and between 3 and 4 can hold higher voltages vs. the voltage across an RF wafer and b) RF losses in the FR4 are no concern in this configuration. The RF-stack is followed by a mesh that we can bias to high voltage. We use this as an energy filter, e.g., if the voltage RF sub-assemblies is higher than the beam potential, no ions will pass the mesh. This way we can test if our beam has been accelerated by the RF. The mesh will also have a focusing or de-focusing effect.

(59) We extract the beam from the source at 10 kV and send the beam through the RF wafer stack (two RF acceleration gaps). The beam then passes through an energy filter (positive biased mesh) and is captured by a Faraday-cup. We measure the beam energy by scanning the mesh voltage and see when the current drops to zero. We repeat this with the RF amplitude set to different levels and test different frequencies. We clearly see that the beam gets accelerated by up to 1 kV; e.g., the drop-off moves from 10.5 kV to 11.5 kV (FIG. 18). This was a proof-of-concept demonstration of multi-beamlet RF acceleration in a PCB wafer platform.

(60) FIG. 18 shows a plot of ion currents vs. retarding field for a series of RF power conditions. The argon ion beam in a 33 beamlet array was injected at 10 kV and the highest observed RF acceleration was 1.78 kV.

(61) We see that for the RF data, the beam charge vs. mesh voltage drops off at higher voltages, showing that the beam gained energy in the RF structure. We can also see that the energy spread of the beam increased during RF acceleration, which is to be expected, since we entered the RF structure with a 4 s long beam pulse, which corresponds to about 80 RF oscillations at 20 MHz. The energy gain can still be optimized, since in our current setup the frequency is not optimized for the fixed RF-gap between RF-wafers 2 and 3. Therefore, the second RF-acceleration gap might have had the wrong phase. Also, the ion source and extraction was not yet fully optimized for these runs, so ion currents can be further increased.

(62) ESQ Focusing

(63) We have achieved first ESQ operation with focusing of 5 keV He.sup.+ beamlets (10 A/beamlet). We used He.sup.+ to increase light output from the scintillator. We operated at 100 V ESQ bias. FIG. 19 is a schematic of the setup with ion source, ESQ wafer, scintillator for beam profile measurements with a gated and image intensified camera and Faraday cup for current measurements.

(64) For the first ESQ beam tests we chose to operate with helium ions at 5 keV. The lighter helium ions produce a proportionally higher light out-put in the plastic scintillator. The multi-cusp ion source can produce well in excess of 80 mA/cm.sup.2 He.sup.+ ions when driven to high discharge power. For heavier ions the current density decreases and we expect to be able to extract 10 mA/cm.sup.2 of xenon ions from this type of ion source. This translates into 100 A to 800 A for Xe.sup.+ and He.sup.+ ions, respectively, that we can inject into 1 mm.sup.2 beamlets. We will determine limits on transportable current in our ESQ lattice and compare measurements with calculated limits (e. g. following the analysis by A. Maschke). For the current ESQ tests, we injected at a modest current density of 10 A per beamlet, which is adequate for testing of ESQ focusing and RF acceleration.

(65) We image the beam induced pattern of emitted light from the scintillator with a gated camera. In the first experiments we also observed background light from the ion source filament. FIG. 20 (Left) shows camera image showing six beamlet apertures. Detected light is dominated by background from the ion source filament which was in line of sight. FIG. 20 (Right) shows that after background subtraction we see light emitted following pulsed helium beam impact (from 1 ms pulses). This background light was most intense from three of the 9 holes in our 33 array (FIG. 21) and we mechanically masked these for the measurements we report here. We can eliminate this background using better bandpass filters, modified camera positioning, etc.

(66) FIG. 22 shows a photo of the typical elliptical deformation of a round beam that is the result of focusing the beam in one direction and at the same time defocusing the beam in the other direction from applying different polarities to the ESQ electrodes. Combining two ESQs into a doublet then allows the beam to be focused in both directions. We show an example of envelope calculations in FIG. 23. For an ESQ bias of 100 V the initially round beamlets are focused to ellipses. Here, we initialized the calculations with beam conditions form the scintillator measurements.

(67) We have tested the HV holding capability of ESQ wafers based on PCB. In FIG. 24, we show examples where the leakage currents across ESQs and across the PCBs was very low due to improved surface treatment after laser processing and fabrication of ESQ structures. This is important for ESQ operation and we can apply voltages up to 1 kV (resulting in electrical fields 10 kV/cm), which exceeds the design goals for efficient ESQ focusing with our geometry and ion beam energies.