Fast vector multiplication and accumulation circuit

Abstract

A fast vector multiplication and accumulation circuit is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector. A scheduler is configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively. A self-accumulating adder is signally connected to the scheduler and includes a compressor, at least two delay elements and at least one shifter. The compressor is configured to add the scheduled operands to generate a plurality of compressed operands. The at least two delay elements are connected to the compressor. The shifter is configured to shift one of the compressed operands. An adder is signally connected to the output ports of the compressor so as to add the compressed operands to generate the inner product.

Claims

1. A fast vector multiplication and accumulation circuit, which is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector, the fast vector multiplication and accumulation circuit comprising: a scheduler configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively; a self-accumulating adder signally connected to the scheduler and comprising: a compressor having a plurality of input ports and a plurality of output ports, wherein one of the input ports sequentially receives the scheduled operands, the compressor is configured to add the scheduled operands to generate a plurality of compressed operands, and the compressed operands are transmitted via the output ports; at least two delay elements connected to other two of the input ports of the compressor, respectively, wherein one of the at least two delay elements is connected to one of the output ports; and at least one shifter connected between another one of the output ports and another one of the at least two delay elements, wherein the at least one shifter is configured to shift one of the compressed operands; and an adder signally connected to the output ports of the compressor so as to add the compressed operands to generate the inner product.

2. The fast vector multiplication and accumulation circuit of claim 1, further comprising: an activation unit signally connected to the adder, wherein the activation unit receives the inner product and implements a non-linear operation.

3. The fast vector multiplication and accumulation circuit of claim 2, wherein the non-linear operation comprises a sigmoid function, a signum function, a threshold function, a piecewise-linear function, a step function or a tanh function.

4. The fast vector multiplication and accumulation circuit of claim 2, wherein the non-linear operation is implemented as a piecewise quadratic approximation.

5. The fast vector multiplication and accumulation circuit of claim 1, wherein the compressor is a full adder, the full adder has a first input port, a second input port, a third input port, a first output port and a second output port, one of the at least two delay elements is disposed between the first input port and the first output port, the other one of the at least two delay elements is disposed between the second input port and the second output port, and the third input port is signally connected to the scheduler.

6. The fast vector multiplication and accumulation circuit of claim 1, wherein the compressor is a 7-to-3 compressor, the 7-to-3 compressor has a first input port, a second input port, a third input port, a fourth input port, a fifth input port, a sixth input port, a seventh input port, a first output port, a second output port and a third output port, the at least two delay elements comprise a first delay element and a second delay element, the at least one shifter comprises a first shifter and a second shifter, the self-accumulating adder further comprises a third delay element, the first delay element is disposed between the first input port and the first output port, the second delay element and the second shifter are disposed between the second input port and the third output port, the third delay element and the first shifter are disposed between the third input port and the second output port, and the fourth input port, the fifth input port, the sixth input port and the seventh input port are signally connected to the scheduler.

7. The fast vector multiplication and accumulation circuit of claim 1, wherein the adder is implemented as a carry look-ahead adder, a carry propagate adder, a carry save adder or a ripple carry adder.

8. The fast vector multiplication and accumulation circuit of claim 1, further comprising: a controlling processor signally connected to the scheduler, the self-accumulating adder and the adder, wherein the controlling processor is configured to control the scheduler, the self-accumulating adder and the adder.

9. The fast vector multiplication and accumulation circuit of claim 1, wherein the scheduler comprises: at least one priority encoder sequentially receiving the multipliers of the multiplier vector, wherein the at least one priority encoder determines at least one valid bit position of each of the multipliers; and at least one barrel shifter sequentially receiving the multiplicands of the multiplicand vector, wherein the at least one barrel shifter is signally connected to the at least one priority encoder, and the at least one barrel shifter is configured to shift the multiplicands to arrange the multiplicands into the scheduled operands according to the at least one valid bit position.

10. The fast vector multiplication and accumulation circuit of claim 1, wherein the fast vector multiplication and accumulation circuit is implemented as an application specific integrated circuit (ASIC) on a semiconductor process, and the semiconductor process comprises a complementary metal-oxide-semiconductor (CMOS) process or a silicon on insulator (SOI) process.

11. The fast vector multiplication and accumulation circuit of claim 1, wherein the fast vector multiplication and accumulation circuit is implemented as a field programmable gate array (FPGA).

12. A fast vector multiplication and accumulation circuit, which is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector, the fast vector multiplication and accumulation circuit comprising: a scheduler configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively; a self-accumulating adder signally connected to the scheduler, wherein the self-accumulating adder is configured to add the scheduled operands to generate a plurality of compressed operands; and an adder signally connected to the self-accumulating adder so as to add the compressed operands to generate the inner product.

13. The fast vector multiplication and accumulation circuit of claim 12, wherein the scheduler comprises: at least one priority encoder sequentially receiving the multipliers of the multiplier vector, wherein the at least one priority encoder determines at least one valid bit position of each of the multipliers; and at least one barrel shifter sequentially receiving the multiplicands of the multiplicand vector, wherein the at least one barrel shifter is signally connected to the at least one priority encoder, and the at least one barrel shifter is configured to shift the multiplicands to arrange the multiplicands into the scheduled operands according to the at least one valid bit position.

14. The fast vector multiplication and accumulation circuit of claim 12, wherein the adder is implemented as a carry look-ahead adder, a carry propagate adder, a carry save adder or a ripple carry adder.

15. The fast vector multiplication and accumulation circuit of claim 12, wherein the self-accumulating adder comprises: a compressor having a plurality of input ports and a plurality of output ports, wherein one of the input ports sequentially receives the scheduled operands, the compressor is configured to add the scheduled operands to generate the compressed operands, and the compressed operands are transmitted via the output ports; and at least two delay elements connected to other two of the input ports of the compressor, respectively, wherein one of the at least two delay elements is connected to one of the output ports.

16. The fast vector multiplication and accumulation circuit of claim 15, wherein the compressor is a full adder, the full adder has a first input port, a second input port, a third input port, a first output port and a second output port, one of the at least two delay elements is disposed between the first input port and the first output port, the other one of the at least two delay elements is disposed between the second input port and the second output port, and the third input port is signally connected to the scheduler.

17. The fast vector multiplication and accumulation circuit of claim 15, wherein the compressor is a 7-to-3 compressor, the 7-to-3 compressor has a first input port, a second input port, a third input port, a fourth input port, a fifth input port, a sixth input port, a seventh input port, a first output port, a second output port and a third output port, the at least two delay elements comprise a first delay element, a second delay element and a third delay element, the first delay element is disposed between the first input port and the first output port, the second delay element is disposed between the second input port and the third output port, the third delay element is disposed between the third input port and the second output port, and the fourth input port, the fifth input port, the sixth input port and the seventh input port are signally connected to the scheduler.

18. The fast vector multiplication and accumulation circuit of claim 12, wherein the fast vector multiplication and accumulation circuit is implemented as an application specific integrated circuit (ASIC) on a semiconductor process, and the semiconductor process comprises a complementary metal-oxide-semiconductor (CMOS) process or a silicon on insulator (SOI) process.

19. The fast vector multiplication and accumulation circuit of claim 12, wherein the fast vector multiplication and accumulation circuit is implemented as a field programmable gate array (FPGA).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

(2) FIG. 1 shows a circuit block diagram of an artificial neural network accelerator according to one embodiment of the present disclosure.

(3) FIG. 2 shows a circuit block diagram of a fast vector multiplication and accumulation circuit according to one example of FIG. 1.

(4) FIG. 3A shows a circuit block diagram of a scheduler of FIG. 2.

(5) FIG. 3B shows a circuit block diagram of a priority encoder of FIG. 3A.

(6) FIG. 3C shows a circuit block diagram of a barrel shifter of FIG. 3A.

(7) FIG. 3D shows pipeline timing diagrams of the scheduler of FIG. 3A.

(8) FIG. 4A shows a circuit block diagram of a self-accumulating adder according to one example of FIG. 2.

(9) FIG. 4B shows pipeline timing diagrams of the self-accumulating adder of FIG. 4A.

(10) FIG. 5 shows a circuit block diagram of an adder according to one example of FIG. 2.

(11) FIG. 6 shows a circuit block diagram of an adder according to another example of FIG. 2.

(12) FIG. 7 shows pipeline timing diagrams of the adder of FIG. 6.

(13) FIG. 8 shows a flow chart of a fast vector multiplication and accumulation method according to one embodiment of the present disclosure.

(14) FIG. 9 shows a circuit block diagram of a fast vector multiplication and accumulation circuit according to another example of FIG. 1.

(15) FIG. 10 shows a circuit block diagram of a self-accumulating adder according to another example of FIG. 2.

(16) FIG. 11 shows a flow chart of a fast vector multiplication and accumulation method according to another embodiment of the present disclosure.

DETAILED DESCRIPTION

(17) FIG. 1 shows a circuit block diagram of an artificial neural network accelerator 110 according to one embodiment of the present disclosure. FIG. 2 shows a circuit block diagram of a fast vector multiplication and accumulation circuit 100 according to one example of FIG. 1. The artificial neural network accelerator 110 includes a dynamic random access memory 102 (DRAM), a global buffer 104 (GLB), a plurality of fast vector multiplication and accumulation circuits 100 and a control processor 500. The fast vector multiplication and accumulation circuit 100 is applied to the artificial neural network accelerator 110 and configured to calculate an inner product Z of a multiplier vector M.sub.r and a multiplicand vector M.sub.c. The fast vector multiplication and accumulation circuit 100 includes a scheduler 200, a self-accumulating adder 300 and an adder 400.

(18) The scheduler 200 is configured to arrange a plurality of multiplicands of the multiplicand vector M.sub.c into a plurality of scheduled operands M.sub.s according to a plurality of multipliers of the multiplier vector M.sub.r, respectively. For example, equation (1) represents an inner product computation of the multiplier vector M.sub.r and the multiplicand vector M.sub.c. Table 1 lists the results of the inner product computation of equation (1) accomplished by the fast vector multiplication and accumulation circuit 100 of FIG. 2.

(19) $\begin{array}{cc}\left(M_c,M_r\right)=\left(\left[\begin{array}{c}10\\ 15\\ 3\end{array}\right],\left[\begin{array}{c}7\\ 4\\ 9\end{array}\right]\right)=\left(\left[\begin{array}{c}{00001010}_2\\ {00001111}_2\\ {00000011}_2\end{array}\right],\left[\begin{array}{c}{00000111}_2\\ {00000100}_2\\ {00001001}_2\end{array}\right]\right)=107+154+39=157& \left(1\right)\end{array}$

(20) TABLE-US-00001 TABLE 1 M.sub.c[0] 00001010 (Ms) M.sub.c[0] (<<1) 00010100 (Ms) M.sub.c[0] (<<2) 00101000 (Ms) S[0] 00110110 C.sub.out[0] 000010000 M.sub.c[1] (<<2) 00111100 (Ms) S[1] 00011010 C.sub.out[1] 00110100 M.sub.c[2] 00000011 (Ms) S[2] 01110001 C.sub.out[2] 00010100 M.sub.c[2] (<<3) 00011000 (Ms) S[3] 01111101 C.sub.out[3] 00100000 10011101 = 157.sub.dec = Z

(21) In equation (1) and Table 1, it is assumed that the multiplicand vector M.sub.c includes three multiplicands M.sub.c[0], M.sub.c[1] and M.sub.c[2]. The decimal representations of the three multiplicands M.sub.c[0], M.sub.c[1] and M.sub.c[2] are 10, 15 and 3, respectively. The binary representations of the three multiplicands M.sub.c[0], M.sub.c[1] and M.sub.c[2] are 00001010, 00001111 and 00000011, respectively. The multiplier vector M.sub.r includes three multipliers. The decimal representations of the three multipliers are 7, 4 and 9, respectively. The binary representations of the three multipliers are 00000111, 00000100 and 00001001, respectively. When a first multiplicand M.sub.c[0] (i.e., 10.sub.dec and 00001010.sub.bin) is multiplied by a first multiplier (i.e., 7.sub.dec and 00000111.sub.bin), the scheduler 200 arranges the first multiplicand M.sub.c[0] into three scheduled operands M.sub.s according to three 1 of the first multiplier (00000111.sub.bin). The three scheduled operands M.sub.s are 00001010, 00010100 and 00101000, respectively. The first one of the three scheduled operands M.sub.s is equal to the first multiplicand M.sub.c[0]. The first multiplicand M.sub.c[0] is left shifted by one bit to form the second one of the three scheduled operands M.sub.s. The first multiplicand M.sub.c[0] is left shifted by two bits to form the third one of the three scheduled operands M.sub.s, as shown in lines 1-3 of Table 1. Moreover, when a second multiplicand M.sub.c[1] (i.e., 15.sub.dec and 00001111.sub.bin) is multiplied by a second multiplier (i.e., 4.sub.dec and 00000100.sub.bin), the scheduler 200 arranges the second multiplicand M.sub.c[1] into one scheduled operand M.sub.s according to one 1 of the second multiplier (00000100.sub.bin). The scheduled operand M.sub.s is 00111100. In other words, the second multiplicand M.sub.c[1] is left shifted by two bits to form the scheduled operand M.sub.s, as shown in line 6 of Table 1. In addition, when a third multiplicand M.sub.c[2] (i.e., 3.sub.dec and 00000011.sub.bin) is multiplied by a third multiplier (i.e., 9.sub.dec and 00001001.sub.bin), the scheduler 200 arranges the third multiplicand M.sub.c[2] into two scheduled operands M.sub.s according to two 1 of the third multiplier (00001001.sub.bin). The two scheduled operands M.sub.s are 00000011 and 00011000, respectively. The first one of the two scheduled operands M.sub.s is equal to the third multiplicand M.sub.c[2]. The third multiplicand M.sub.c[2] is left shifted by three bits to form the second one of the two scheduled operands M.sub.s, as shown in lines 9 and 12 of Table 1.

(22) The self-accumulating adder 300 is signally connected to the scheduler 200. The self-accumulating adder 300 is configured to add the scheduled operands M.sub.s to generate a plurality of compressed operands S[n], C.sub.out[n], wherein n is an integer greater than or equal to 0. For example, the self-accumulating adder 300 sequentially performs four addition operations which includes a first addition operation, a second addition operation, a third addition operation and a fourth addition operation, as shown in equation (1) and Table 1. The first addition operation represents that the self-accumulating adder 300 adds three scheduled operands M.sub.s (i.e., M.sub.c[0]=00001010, M.sub.c[0](<<1)=00010100 and M.sub.c[0](<<2)=00101000) to generate two compressed operands S[0], C.sub.out[0], as shown in lines 4 and 5 of Table 1. The second addition operation represents that the self-accumulating adder 300 adds the two compressed operands S[0], C.sub.out[0] and a scheduled operand M.sub.s (i.e., M.sub.c[1](<<2)=00111100) to generate two compressed operands S[1], C.sub.out[1], as shown in lines 7 and 8 of Table 1. The third addition operation represents that the self-accumulating adder 300 adds the two compressed operands S[1], C.sub.out[1] and a scheduled operand M.sub.s (i.e., M.sub.c[2]=00000011) to generate two compressed operands S[2], C.sub.out[2], as shown in lines 10 and 11 of Table 1. The fourth addition operation represents that the self-accumulating adder 300 adds the two compressed operands S[2], C.sub.out[2] and a scheduled operand M.sub.s (i.e., M.sub.c[2](<<2)=00011000) to generate two compressed operands S[3], C.sub.out[3], as shown in lines 13 and 14 of Table 1.

(23) The adder 400 is signally connected to the output ports S, C.sub.out of the compressor 300 so as to add the two compressed operands S[3], C.sub.out[3] to generate the inner product Z, as shown in line 15 of Table 1. The adder 400 is implemented as a carry look-ahead adder, a carry propagate adder, a carry save adder or a ripple carry adder.

(24) In addition, a controlling processor 500 is disposed in the artificial neural network accelerator 110 and signally connected to the scheduler 200, the self-accumulating adder 300 and the adder 400. The controlling processor 500 is configured to control the scheduler 200, the self-accumulating adder 300 and the adder 400. The controlling processor 500 may be a central processing unit (CPU), a micro-control unit (MCU), or other control logic circuits. The artificial neural network accelerator 110 includes a plurality of layer processing modules (not shown). The controlling processor 500 is signally connected to the layer processing modules. The controlling processor 500 detects the layer processing modules. The controlling processor 500 generates a plurality of controlling signals and transmits the controlling signals to the scheduler 200, the self-accumulating adder 300 and the adder 400 according to a processed result of the layer processing modules so as to determine a schedule or stop an operation of the scheduler 200, the self-accumulating adder 300 and the adder 400. In another embodiment, the artificial neural network accelerator 110 includes a first layer processing module and a second layer processing module. The first layer processing module has a first layer output end. The second layer processing module has a second layer input end. The fast vector multiplication and accumulation circuit 100 is disposed between the first layer output end of the first layer processing module and the second layer input end of the second layer processing module to process an output signal of the first layer processing module. In addition, the fast vector multiplication and accumulation circuit 100 may be implemented as an application specific integrated circuit (ASIC) on a semiconductor process, and the semiconductor process includes a complementary metal-oxide-semiconductor (CMOS) process or a silicon on insulator (SOI) process. The fast vector multiplication and accumulation circuit 100 may be implemented as a field programmable gate array (FPGA). Therefore, the fast vector multiplication and accumulation circuit 100 of the present disclosure is suitable for use in the artificial neural network accelerator 110 and utilizes the self-accumulating adder 300 combined with application-specific integrated circuits (ASIC) to accomplish a fast inner product operation, thereby greatly reducing the computational complexity, latency and power consumption.

(25) FIG. 3A shows a circuit block diagram of a scheduler 200 of FIG. 2; FIG. 3B shows a circuit block diagram of a priority encoder 210 of FIG. 3A; FIG. 3C shows a circuit block diagram of a barrel shifter 220a of FIG. 3A; and FIG. 3D shows pipeline timing diagrams of the scheduler 200 of FIG. 3A. In FIGS. 2, 3A, 3B, 3C and 3D, the scheduler 200 includes a priority encoder 210, two barrel shifters 220a, 220b, five delay elements 230 and four switch elements 240.

(26) The priority encoder 210 sequentially receives the multipliers of the multiplier vector M.sub.r. The priority encoder 210 determines at least one valid bit position of each of the multipliers. In other words, the priority encoder 210 determines a position of a value of each of the multipliers, and the value of each of the multipliers is equal to 1. The priority encoder 210 includes eight priority encoding input ports M.sub.0, M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5, M.sub.6, M.sub.7, nine priority controlling signals P.sub.0, P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.5, P.sub.6, P.sub.7, P.sub.8, eight priority encoding output ports EP.sub.0, EP.sub.1, EP.sub.2, EP.sub.3, EP.sub.4, EP.sub.5, EP.sub.6, EP.sub.6, EP.sub.7 and a signal READY. The eight priority encoding input ports M.sub.0-M.sub.7 receive the multipliers of the multiplier vector M.sub.r. The nine priority controlling signals P.sub.0-P.sub.8 are inner signals of the priority encoder 210 and represent a priority status. The priority controlling signal P.sub.0 is equal to 1 (i.e., a logical true value). When one of the nine priority controlling signals P.sub.n is 0, the subsequent priority controlling signals P.sub.n+1-P.sub.8 cannot obtain the priority state. The priority encoder 210 includes nineteen AND gates and nine inverters, as shown in FIG. 3B. The eight priority encoding output ports EP.sub.0-EP.sub.7 of the priority encoder 210 generated by the serial connection of the nineteen AND gates and the nine inverters can determine the position of the value of each of the multipliers, and the value of each of the multipliers is equal to 1. For example, if the multiplier of the multiplier vector M.sub.r is 7 (00000111.sub.bin), the eight priority encoding input ports M.sub.0, M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5, M.sub.6, M.sub.7 are 1, 1, 1, 0, 0, 0, 0, 0, respectively. Then, the eight priority encoding output ports EP.sub.0, EP.sub.1, EP.sub.2, EP.sub.3, EP.sub.4, EP.sub.5, EP.sub.6, EP.sub.7 are 1, 0, 0, 0, 0, 0, 0, 0, respectively. In other words, if the multiplier of the multiplier vector M.sub.r is not equal to zero, the eight priority encoding output ports EP.sub.0-EP.sub.7 are 1, 0, 0, 0, 0, 0, 0, 0, respectively. On the contrary, if the multiplier of the multiplier vector M.sub.r is equal to zero, the eight priority encoding output ports EP.sub.0-EP.sub.7 are all zero.

(27) The structure of the barrel shifter 220a is the same as the structure of the barrel shifter 220b. The barrel shifter 220a includes a plurality of tri-state buffers, eight barrel shifting input ports x.sub.0, x.sub.1, x.sub.2, x.sub.3, x.sub.4, x.sub.5, x.sub.6, x.sub.7, eight barrel shifting output ports y.sub.0, y.sub.1, y.sub.2, y.sub.3, y.sub.4, y.sub.5, y.sub.6, y.sub.7 and eight barrel shifting control ports w.sub.0, w.sub.1, w.sub.2, w.sub.3, w.sub.4, w.sub.5, w.sub.6, w.sub.7, as shown in FIG. 3C. The eight barrel shifting control ports w.sub.0-w.sub.7 are connected to the eight priority encoding output ports EP.sub.0-EP.sub.7 of FIG. 3B, respectively. The barrel shifter 220a sequentially receives the multiplier of the multiplier vector M.sub.r and is signally connected to the priority encoder 210. The barrel shifter 220a is configured to shift the multiplier of the multiplier vector M.sub.r according to the valid bit position. The barrel shifter 220b sequentially receives the multiplicands M.sub.c[0], M.sub.c[1], M.sub.c[2] of the multiplicand vector M.sub.c. The barrel shifter 220b is signally connected to the priority encoder 210, and the barrel shifter 220b is configured to shift the multiplicands M.sub.c[0], M.sub.c[1], M.sub.c[2] to arrange the multiplicands M.sub.c[0], M.sub.c[1], M.sub.c[2] into the scheduled operands M.sub.s according to the valid bit position. In addition, the multiplier vector M.sub.r and the multiplicand vector M.sub.c are shifted a plurality of times according to a priority encoding result of the multiplier vector M.sub.r. Each shift operation is determined by the switch elements 240. The scheduled operands M.sub.s may be outputted after each shift operation is carried out. In FIG. 3A, a signal LOAD can control the scheduler 200 and represent that a new multiplier vector M.sub.r and a new multiplicand vector M.sub.c are loaded into the scheduler 200. The scheduler 200 may generate signals READY, PROC, FIFO_WEN to correctly arrange the scheduled operands M.sub.s and outputs the scheduled operands M.sub.s to the self-accumulating adder 300. The signal READY represents the completion of all shift operations. The signal PROC represents the shift operation. The signal FIFO_WEN represents that shift operation is carried out one time, and a set of the scheduled operand M.sub.s is written into input ports of a next level.

(28) The five delay elements 230 and the four switch elements 240 are controlled by the controlling processor 500. The controlling processor 500 can generate control signals to allow the input ports and output ports of the priority encoder 210 and the barrel shifter 220a, 220b to correctly correspond to each other in time, thereby improving the efficiency of the pipeline. The delay elements 230 are configured to delay signals. The switch elements 240 are configured to determine to load a new multiplier vector M.sub.r and a new multiplicand vector M.sub.c into the scheduler 200 or to use a feedback path in the scheduler 200 to shift output signals of the barrel shifter 220a, 220b. In FIG. 3D, when one of the multiplicands of the multiplicand vector M.sub.c and one of the multipliers of the multiplier vector M.sub.r are inputted into the scheduler 200 in a first cycle (e.g., cycle=1), output signals of the priority encoding output ports EP.sub.0-EP.sub.7 of the priority encoder 210, output signals of the barrel shifting output ports y.sub.0-y.sub.7 of the barrel shifter 220a, 220b and the scheduled operand M.sub.s are generated in a second cycle (e.g., cycle=2). L of the signal LC.sub.0.sup.(0) represents Load. C of the signal CE.sub.0.sup.(1) represents Compute. W of the signal WC.sub.0.sup.(1) represents Write.

(29) FIG. 4A shows a circuit block diagram of a self-accumulating adder 300 according to one example of FIG. 2; and FIG. 4B shows pipeline timing diagrams of the self-accumulating adder 300 of FIG. 4A. The self-accumulating adder 300 includes a compressor 310, at least two delay elements 320a, 320b and at least one shifter 330. The compressor 310 has a plurality of input ports X, Y, C.sub.in and a plurality of output ports S, C.sub.out. One of the input ports C.sub.in sequentially receives the scheduled operands M.sub.s. The compressor 310 is configured to add the scheduled operands M.sub.s to generate a plurality of compressed operands S[n], C.sub.out[n], and the compressed operands S[n], C.sub.out[n] are transmitted via the output ports S, C.sub.out. The two delay elements 320a, 320b are connected to other two of the input ports X, Y of the compressor 310, respectively. One of the two delay elements 320a is connected to one of the output ports S. The shifter 330 is connected between another one of the output ports C.sub.out and the other one of the two delay elements 320b. The shifter 330 is configured to shift one of the compressed operands C.sub.out[n]. In detail, the compressor 310 is a full adder (FA). The full adder has a first input port X, a second input port Y, a third input port C.sub.in, a first output port S and a second output port C.sub.out. The full adder is a 3 to 2 compressor. A truth table of the full adder is shown in Table 2. One of the two delay elements 320a is disposed between the first input port X and the first output port S. The other one of the two delay elements 320b and the shifter 330 are disposed between the second input port Y and the second output port C.sub.out, and the third input port C.sub.in is signally connected to the scheduler 200. In FIG. 4B, after n+5 cycles, the first output port S and the second output port C.sub.out can correctly output the compressed operands S[n], C.sub.out[n] which are utilized by a subsequent circuit, such as the adder 400. The compressed operands S[n+5], C.sub.out[n+5] are corresponding to the signals C.sub.1.sup.(n+3), C.sub.1.sup.(m+3), respectively. An input register and an output FIFO are coupled to an input end and an output end of the self-accumulating adder 300, respectively. The input register and the output FIFO are controlled by the controlling processor 500.

(30) TABLE-US-00002 TABLE 2 X Y C.sub.in S C.sub.out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

(31) FIG. 5 shows a circuit block diagram of an adder 400 according to one example of FIG. 2; FIG. 6 shows a circuit block diagram of an adder 400a according to another example of FIG. 2; and FIG. 7 shows pipeline timing diagrams of the adder 400a of FIG. 6. In FIG. 5, the adder 400 includes two parallel-in serial-out (PISO) modules 410a, 410b, a full adder 420 and a serial-In parallel-out (PISO) module 430. The full adder 420 is connected between the two parallel-in serial-out modules 410a, 410b and the serial-In parallel-out module 430. In FIG. 6, the adder 400a includes two parallel-in serial-out modules 410a, 410b, a full adder 420, a serial-In parallel-out module 430, an exclusive OR (XOR) gate 440, a priority encoder 450, a counter 460 and a comparator 470. The exclusive OR gate 440 is coupled to the first output port S and the second output port C.sub.out of the self-accumulating adder 300. The exclusive OR gate 440 is connected to the priority encoder 450 and the serial-In parallel-out module 430. The exclusive OR gate 440 transmits an output signal to the priority encoder 450 and the serial-In parallel-out module 430. The priority encoder 450 and the counter 460 are connected to the comparator 470. In the comparator 470, when a value of the input port X is equal to a value of the input port Y, a value of the output port EQ is equal to 1. On the contrary, when the value of the input port X is different from the value of the input port Y, the value of the output port EQ is equal to 0. The exclusive OR gate 440, the priority encoder 450, the counter 460 and the comparator 470 are utilized to generate a signal READY to determine a most valid bit of a signal q[15:0] according to the compressed operands S[15:0], C.sub.out[15:0]. The signal q[15:0] has sixteen bits. If the signal READY is equal to 0, it represents that the most valid bit of the signal q[15:0] has not yet been found. If the signal READY is equal to 1, it represents that the most valid bit of the signal q[15:0] has been found and may be utilized to early stop the adder 400, thereby greatly reducing the computation and power consumption. For example, if the signal q[15:0] is equal to 0000000011111111, the signal q[7] is the most valid bit, and the compressed operands S[15:8], C.sub.out[15:8] are all zero. The adder 400 does not need to further process the addition of the compressed operands S[15:8], C.sub.out[15:8]. In FIG. 7, after n+5 cycles, the serial-In parallel-out module 430 can correctly output the inner product Z which is utilized by a subsequent circuit, such as an activation unit 600. In FIG. 7, the signal RST represents Reset. Accordingly, each of the adders 400, 400a of the present disclosure utilizes a specific signal judgement circuit to greatly reduce the computation and power consumption.

(32) FIG. 8 shows a flow chart of a fast vector multiplication and accumulation method 700 according to one embodiment of the present disclosure. The fast vector multiplication and accumulation method 700 may be used in the fast vector multiplication and accumulation circuit 100 of FIG. 2. The fast vector multiplication and accumulation method 700 provides a scheduling step S12, a self-accumulating and adding step S14 and an adding step S16. The scheduling step S12 is for driving a scheduler 200 to arrange a plurality of multiplicands of the multiplicand vector M.sub.c into a plurality of scheduled operands M.sub.s according to a plurality of multipliers of the multiplier vector M.sub.r, respectively. The self-accumulating and adding step S14 is for driving a self-accumulating adder 300 to add the scheduled operands M.sub.s to generate a plurality of compressed operands S[n], C.sub.out[n]. The adding step S16 is for driving an adder 400 to add the compressed operands S[n], C.sub.out[n] to generate an inner product Z. Therefore, the fast vector multiplication and accumulation method 700 of the present disclosure is suitable for use in an inner product operation of the artificial neural network and utilizes the scheduling step S12 combined with the self-accumulating and adding step S14 to accomplish a fast inner product operation, thereby greatly reducing the computational complexity, latency and power consumption.

(33) FIG. 9 shows a circuit block diagram of a fast vector multiplication and accumulation circuit 100a according to another example of FIG. 1. The fast vector multiplication and accumulation circuit 100a includes a scheduler 200, a self-accumulating adder 300, an adder 400, a controlling processor 500 and an activation unit 600.

(34) In FIG. 9, the detail of the scheduler 200, the self-accumulating adder 300, the adder 400 and the controlling processor 500 is the same as the example of FIG. 2 and will not be described again herein. In FIG. 9, the fast vector multiplication and accumulation circuit 100a further includes the activation unit 600. The activation unit 600 is signally connected to the adder 400. The activation unit 600 receives the inner product Z and implements a non-linear operation. The non-linear operation includes a sigmoid function, a signum function, a threshold function, a piecewise-linear function, a step function or a tan h function. In addition, the non-linear operation may be implemented as a piecewise quadratic approximation.

(35) FIG. 10 shows a circuit block diagram of a self-accumulating adder 300a according to another example of FIG. 2. The self-accumulating adder 300a is configured to process a large number of the multiplier vector M.sub.r and the multiplicand vector M.sub.c at one time. The self-accumulating adder 300a includes a compressor 310a, a first delay element 320a, a second delay element 320b, a third delay element 320c, a first shifter 330a and a second shifter 330b. The compressor 310a is a 7 to 3 compressor having a first input port X.sub.0, a second input port X.sub.1, a third input port X.sub.2, a fourth input port X.sub.3, a fifth input port X.sub.4, a sixth input port X.sub.5, a seventh input port X.sub.6, a first output port Y.sub.0, a second output port Y.sub.1 and a third output port Y.sub.2. The first delay element 320a is disposed between the first input port X.sub.0 and the first output port Y.sub.0. The second delay element 320b and the second shifter 330b are disposed between the second input port X.sub.1 and the third output port Y.sub.2. The third delay element 320c and the first shifter 330a are disposed between the third input port X.sub.2 and the second output port Y.sub.1. The fourth input port X.sub.3, the fifth input port X.sub.4, the sixth input port X.sub.5 and the seventh input port X.sub.6 are signally connected to the scheduler 200. A truth table of the compressor 310a is shown in Table 3.

(36) TABLE-US-00003 TABLE 3 X.sub.0 X.sub.1 X.sub.2 X.sub.3 X.sub.4 X.sub.5 X.sub.6 Y.sub.0 Y.sub.1 Y.sub.2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 . . . 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1 0 . . . 0 0 0 0 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 . . . 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 0 . . . 1 1 1 1 1 1 1 1 1 1

(37) FIG. 11 shows a flow chart of a fast vector multiplication and accumulation method 700a according to another embodiment of the present disclosure. The fast vector multiplication and accumulation method 700a may be used in the fast vector multiplication and accumulation circuit 100a of FIG. 9. The fast vector multiplication and accumulation method 700a provides a scheduling step S22, a self-accumulating and adding step S24, an adding step S26 and an activation step S28.

(38) The scheduling step S22 is for driving a scheduler 200 to arrange a plurality of multiplicands of the multiplicand vector M.sub.c into a plurality of scheduled operands M.sub.s according to a plurality of multipliers of the multiplier vector M.sub.r, respectively. In detail, the scheduling step S22 includes a priority encoding step S222 and a barrel shifting step S224. The priority encoding step S222 is for driving a priority encoder 210 (shown in FIG. 3A) to sequentially receive the multipliers of the multiplier vector M.sub.r. The priority encoder 210 determines at least one valid bit position of each of the multipliers. The barrel shifting step S224 is for driving barrel shifters 220a, 220b (shown in FIG. 3A) to sequentially receive the multiplicands of the multiplicand vector M.sub.c. The barrel shifters 220a, 220b are signally connected to the priority encoder 210, and the barrel shifters 220a, 220b are configured to shift the multiplicands to arrange the multiplicands into the scheduled operands M.sub.s according to the valid bit position.

(39) The self-accumulating and adding step S24 is for driving a self-accumulating adder 300 (shown in FIG. 4A) to add the scheduled operands M.sub.s to generate a plurality of compressed operands S[n], C.sub.out[n]. In detail, the self-accumulating and adding step S24 includes a compressing step S242, a delaying step S244 and a shifting step S246. The compressing step S242 is for driving a compressor 310 (shown in FIG. 4A) to add the scheduled operands M.sub.s to generate a plurality of compressed operands S[n], C.sub.out[n]. The delaying step S244 is for driving two delay elements 320a, 320b (shown in FIG. 4A) to delay the compressed operands S[n], C.sub.out[n] and then transmit the compressed operands S[n], C.sub.out[n] to the compressor 310. The shifting step S246 is for driving a shifter 330 (shown in FIG. 4A) to shift the compressed operand C.sub.out[n] and then transmit the compressed operand C.sub.out[n] to the delay element 320b. Moreover, the self-accumulating and adding step S24 may be for selecting a 3 to 2 compressor, a 7 to 3 compressor or other types of adder as the compressor 310. The 3 to 2 compressor and the 7 to 3 compressor are shown in FIGS. 4A and 10, respectively.

(40) The adding step S26 is for driving an adder 400 or an adder 400a to add the compressed operands S[n], C.sub.out[n] to generate an inner product Z. The adder 400 is shown in FIG. 5. The adder 400a is shown in FIG. 6.

(41) The activation step S28 is for driving an activation unit 600 (shown in FIG. 9) to receive the inner product Z and implements a non-linear operation. The non-linear operation includes a sigmoid function, a signum function, a threshold function, a piecewise-linear function, a step function or a tan h function. Therefore, the fast vector multiplication and accumulation method 700a of the present disclosure is suitable for use in an inner product operation of the artificial neural network and utilizes the scheduling step S22 combined with the self-accumulating and adding step S24 to accomplish a fast inner product operation, thereby not only greatly reducing the computational complexity, latency and power consumption, but also reducing the chip area and the cost of production. Table 4 lists the total number of full adders (hardware complexity) used in the present disclosure and a conventional direct MAC circuit. It is obvious that the hardware complexity of the present disclosure is lower than the hardware complexity of the conventional direct MAC circuit.

(42) TABLE-US-00004 TABLE 4 Hardware complexity Direct MAC Present disclosure # Full adders 80(64.Math.16) 32(1616) # FA time/matrix OP (Worst case) N N # FA time/matrix OP (Equal 0/1) N N/2

(43) According to the aforementioned embodiments and examples, the advantages of the present disclosure are described as follows.

(44) 1. The fast vector multiplication and accumulation circuit and the fast vector multiplication and accumulation method of the present disclosure utilize the self-accumulating adder combined with application-specific integrated circuits (ASIC) to accomplish a fast inner product operation, thereby greatly reducing the computational complexity, latency and power consumption. In addition, the fast vector multiplication and accumulation circuit and the fast vector multiplication and accumulation method of the present disclosure utilize a multi-bit compressor of the self-accumulating adder and a binary arithmetic coding of the scheduler to greatly enhance a level of vector parallelism of a long vector inner product operation.

(45) 2. The fast vector multiplication and accumulation circuit and the fast vector multiplication and accumulation method of the present disclosure are suitable for use in an inner product operation of the artificial neural network.

(46) 3. The fast vector multiplication and accumulation circuit and the fast vector multiplication and accumulation method of the present disclosure utilize the scheduling step combined with the self-accumulating and adding step to accomplish a fast inner product operation, thereby not only greatly reducing the computational complexity, latency and power consumption, but also reducing the chip area and the cost of production.

(47) Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

(48) It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.