Nanosheet radiation dosimeter

Abstract

A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.

Claims

1. A semiconductor radiation monitor comprising: a nanosheet stack comprising a charge storage dielectric material nanosheet sandwiched between a first silicon channel material nanosheet and a second silicon channel material nanosheet, and suspended above a semiconductor substrate, wherein the charge storage dielectric material nanosheet has a first surface that directly contacts a surface of the first silicon channel material nanosheet, and a second surface, opposite the first surface, that directly contacts a surface of the second silicon channel material nanosheet; a functional gate structure located beneath the first silicon channel material nanosheet and above the second silicon channel material nanosheet; a topmost inner spacer located laterally adjacent to the function gate structure that is located above the second silicon channel material nanosheet and having a bottommost surface directly contacting a topmost surface of the second silicon channel material nanosheet; and a lowermost inner spacer located laterally adjacent to the function gate structure that is located beneath the first silicon channel material nanosheet and having a topmost surface directly contacting a bottommost surface of the first silicon channel material nanosheet.

2. The semiconductor radiation monitor of claim 1, wherein the charge storage dielectric material nanosheet is lattice matched to the first and second silicon channel material nanosheets and is composed of an epitaxial oxide.

3. The semiconductor radiation monitor of claim 2, wherein the epitaxial oxide is composed of lanthanum (II) oxide, gadolinium(III)-oxide, dysprosium(III)-oxide, holmium(III) oxide, erbium (III) oxide, thulium (III) oxide, lutetium(III) oxide, cerium (IV) oxide, lanthanum-yttrium oxide, gadolinium-erbium oxide, neodymium-erbium oxide, neodymium-gadolinium oxide, or lanthanum-erbium oxide.

4. The semiconductor radiation monitor of claim 1, wherein the charge storage dielectric material nanosheet has a same width as the first and second silicon channel material nanosheets.

5. The semiconductor radiation monitor of claim 1, wherein charge storage dielectric material nanosheet is composed of a dielectric oxide and has width that is less than a width of the first and second silicon channel material nanosheets, and wherein an intermediate inner spacer is located at the end of the charge storage dielectric material nanosheet.

6. The semiconductor structure of claim 1, further comprising a source/drain structure on each side of the nanosheet stack and in direct physically contact with a sidewall of the first silicon channel material nanosheet and in direct physical contact with a sidewall of the second silicon channel material nanosheet.

7. The semiconductor radiation monitor of claim 6, wherein the source/drain structure has a faceted topmost surface.

8. The semiconductor radiation monitor of claim 6, further comprising a contact structure contacting a surface of each source/drain structure.

9. The semiconductor radiation monitor of claim 8, wherein each contact structure is located within an interlayer dielectric material layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross sectional view of an exemplary semiconductor radiation monitor (i.e., dosimeter) of the present application and during an early stage of fabrication, the exemplary semiconductor radiation monitor including a material stack structure of, and from bottom to top, a sacrificial semiconductor material layer, a first silicon channel material layer, an epitaxial oxide layer, and a second silicon channel material layer located on a surface of a semiconductor substrate.

(2) FIG. 2 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 1 after forming a sacrificial gate structure and a dielectric spacer material layer on a surface of the material stack structure.

(3) FIG. 3 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 2 after removing physically exposed portions of the material stack structure that are not protected by the sacrificial gate structure and the dielectric spacer material layer to provide a nanosheet material stack of, and from bottom to top, a sacrificial semiconductor material nanosheet, a first silicon channel material nanosheet, an epitaxial oxide nanosheet, and a second silicon channel material nanosheet located beneath the sacrificial gate structure and the dielectric spacer material layer.

(4) FIG. 4 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 3 after recessing the sacrificial semiconductor material nanosheet and forming an inner dielectric spacer on exposed sidewalls of the recessed sacrificial semiconductor material nanosheet.

(5) FIG. 5 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 4 after forming a source/drain structure on each side of the nanosheet material stack.

(6) FIG. 6 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 5 after forming an interlayer dielectric (ILD) material layer on the source/drain structure.

(7) FIG. 7 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 6 after removing the sacrificial gate structure.

(8) FIG. 8 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 7 after removing the recessed sacrificial semiconductor material nanosheet.

(9) FIG. 9 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 8 after forming a functional gate structure in an area previously containing the recessed sacrificial semiconductor material nanosheet and the area previously including the sacrificial gate structure.

(10) FIG. 10 is a cross sectional view of the exemplary semiconductor radiation monitor of FIG. 9 after forming contact structures.

(11) FIG. 11 is a cross sectional view of another exemplary semiconductor radiation monitor in accordance with the present application.

DETAILED DESCRIPTION

(12) The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.

(13) In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

(14) It will be understood that when an element as a layer, region or substrate is referred to as being on or over another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being beneath or under another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being directly beneath or directly under another element, there are no intervening elements present.

(15) As mentioned above, the present application provides a semiconductor radiation monitor that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet. The semiconductor radiation monitor of the present application provides instantaneous readout of a radiation dose through simple electrical measurement (wired or wireless) as compared to conventional TLDs, which require extended post radiation sample processing. The semiconductor radiation monitor of the present application can provide a direct change in threshold voltage measurement by simple I-V or C-V measurement for radiation dose calculation. The semiconductor radiation monitor of the present application can be fabricated utilizing CMOS processing steps and requires no new processes to be developed, which facilitates device scaling with advantages such as embedded/implantable applications. In commercial radiation sensing field effect transistors (RADFETs), support electronics are required to maintain specific current/voltage for change in threshold voltage readouts. These readouts contain a component dependent on the biasing current, which limits device scalability.

(16) Moreover, the charge storage region, i.e., the dielectric material nanosheet, decouples the charge storage part from the radiation detection/readout which enables non-destructive electrical readout. In bulk Si radiation dosimeters (e.g., RADFETs), the radiation detection is conducted in the front gate/oxide/Si where the charge is stored. The repetitive readout voltage may eventually induce leakage of stored charge.

(17) Furthermore, the semiconductor radiation monitor of the present application has a long (compared to radiation treatment time) charge retention time (at least 30 days), enabling long-term radiation dose tracking.

(18) Referring first to FIG. 1, there is illustrated an exemplary semiconductor radiation monitor (i.e., dosimeter) of the present application and during an early stage of fabrication, the exemplary semiconductor radiation monitor including a material stack structure of, and from bottom to top, a sacrificial semiconductor material layer 12, a first silicon channel material layer 14, an epitaxial oxide layer 16, and a second silicon channel material layer 18 located on a surface of a semiconductor substrate 10. In accordance with this embodiment of the present application, the first silicon channel material layer 14, the epitaxial oxide layer 16, and the second silicon channel material layer 18 of the material stack structure are lattice matched.

(19) The semiconductor substrate 10 that can be employed in the present application includes at least one semiconductor material that has semiconducting properties. Examples of semiconductor materials that can be used as the semiconductor substrate 10 include, for example, silicon (Si), a silicon germanium (SiGe) alloy, a silicon germanium carbide (SiGeC) alloy, germanium (Ge), III/V compound semiconductors or II/VI compound semiconductors. In one embodiment, the semiconductor substrate 10 is a bulk semiconductor substrate. The term bulk semiconductor substrate denotes a substrate that is composed entirely of one or more semiconductor materials. In one example, the bulk semiconductor substrate is composed entirely of Si.

(20) In some embodiments, the semiconductor substrate 10 is composed of a semiconductor-on-insulator (SOI) substrate. An SOI substrate typically includes a handle substrate, an insulator layer and a topmost semiconductor material layer. In some embodiments, the handle substrate of the SOI substrate may include a semiconductor material, as described above. In other embodiments, the handle substrate may be omitted, or the handle substrate may be composed of a conductive material and/or an insulator material. The insulator layer of the SOI substrate may include a crystalline or non-crystalline dielectric material. In one example, the insulator layer of the SOI substrate may be composed of silicon dioxide and/or boron nitride. The topmost semiconductor layer of the SOI substrate is composed of a semiconductor material, as defined above.

(21) The material stack structure (12, 14, 16, 18), as defined above, is then formed on the semiconductor substrate 10. As mentioned above, the material stack structure includes a sacrificial semiconductor material layer 12, a first silicon channel material layer 14, an epitaxial oxide layer 16, and a second silicon channel material layer 18 stacked one atop the other.

(22) The sacrificial semiconductor material layer 12 is composed of a semiconductor material which differs in composition from at least an upper portion of the semiconductor substrate 10 and is other than silicon. In one embodiment, the sacrificial semiconductor material layer 12 is composed of a silicon germanium alloy. The sacrificial semiconductor material layer 12 can be formed utilizing an epitaxial growth (or deposition process) as defined in greater detail herein below.

(23) The first and second silicon channel material layers 14 and 18 have a different etch rate than the sacrificial semiconductor material layer 12. The first and second silicon channel material layers 14 and 18 can be formed utilizing an epitaxial growth (or deposition process) as defined in greater detail herein below.

(24) The epitaxial oxide layer 16, which is sandwiched between the first silicon channel material layer 14 and the second silicon channel material layer 18, is a dielectric material that can store positive charges upon use. The epitaxial oxide layer 16 may be selected to have a lattice dimension substantially similar (i.e., 5%) to the lattice dimension of the first and second silicon channel material layers (14, 16), thus the epitaxial oxide layer 16 is said to be lattice matched to the first and second silicon channel material layers (14, 18). The epitaxial oxide layer 16 is epitaxially deposited, as defined below. Examples of epitaxial oxides that are suitable for use as the epitaxial oxide layer 16 may include binary oxides, such as, e.g., lanthanum (II) oxide (La.sub.2O.sub.3) gadolinium(III)-oxide (Gd.sub.2O.sub.3), dysprosium(III)-oxide (Dy.sub.2O.sub.3), holmium(III) oxide (Ho.sub.2O.sub.3), erbium (III) oxide (Er.sub.2O.sub.3), thulium (III) oxide (Tm.sub.2O.sub.3), lutetium(III) oxide (Lu.sub.2O.sub.3) or cerium (IV) oxide (CeO.sub.2), ternary oxides including a rare earth metal, such as e.g., Gd, Er, Nd, La and Y forming oxides such as, e.g., lanthanum-yttrium oxide ((La.sub.xY.sub.1-x).sub.2O.sub.3), gadolinium-erbium oxide ((Gd.sub.xEr.sub.1-x).sub.2O.sub.3), neodymium-erbium oxide ((Nd.sub.xEr.sub.1-x).sub.2O.sub.3), neodymium-gadolinium oxide ((Nd.sub.xGd.sub.1-x).sub.2O.sub.3), lanthanum-erbium oxide ((La.sub.xEr.sub.1-x).sub.2O.sub.3), or any combination thereof. In one embodiment, the epitaxial oxide layer 16 is composed of (La.sub.xY.sub.1-x).sub.2O.sub.3 alloy in which x is 0.33.

(25) The thickness of the epitaxial oxide layer 16 can be determined by satisfying the requirement of negligible loss of stored charge by tunneling into the first and second silicon channel material layers 14 and 18. The tunneling between a silicon channel material layer and the epitaxial oxide layer 16 can be described by the Fowler-Nordheim model. According to this model, and to keep the tunneling current below a desired level, e.g., 1E.sup.8 Amperes/cm.sup.2, the epitaxial oxide field must be lower than about 6 MV/cm. In the present application, the thickness of the epitaxial oxide layer 16 is from 10 nm to 500 nm. In some embodiments, the thickness of the epitaxial oxide layer 16 is from 10 nm to 100 nm, while in other embodiments the thickness of the epitaxial oxide layer 16 is from 10 nm to 50 nm.

(26) Material stack structure (12, 14, 16, 18) can be formed by sequential epitaxial growth of the sacrificial semiconductor material layer 12, the first silicon channel material layer 14, the epitaxial oxide layer 16, and the second silicon channel material layer 18. Following epitaxial growth of the second silicon channel material layer 18, a patterning process may be used to provide the material stack structure (12, 14, 16, 18) shown in FIG. 1. Patterning may be performed by lithography and etching or any other patterning method known to those skilled in the art including, for example, a sidewall-image transfer (SIT) process.

(27) The terms epitaxially growing and/or depositing and epitaxially grown and/or deposited mean the growth of a material (e.g., semiconductor material or epitaxial oxide) on a growth surface of another material, in which the material being grown has the same crystalline characteristics as the material of the growth surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the growth surface of a material with sufficient energy to move around on the growth surface and orient themselves to the crystal arrangement of the atoms of the growth surface. Therefore, an epitaxial material has the same crystalline characteristics as the growth on surface on which it is formed.

(28) Examples of various epitaxial growth process apparatuses that can be employed in the present application include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from 550 C. to 900 C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. The epitaxial growth of the various material layers (i.e., the sacrificial semiconductor material layer 12, the first silicon channel material layer 14, the epitaxial oxide layer 16 and the second silicon channel material layer 18) can be performed utilizing any well known precursor gas or gas mixture. Carrier gases like hydrogen, nitrogen, helium and argon can be used.

(29) The term material stack structure denotes a continuous structure including a pair of vertical sidewalls that are parallel to each other. As used herein, a surface is vertical if there exists a vertical plane from which the surface does not deviate by more than three times the root mean square roughness of the surface. Each layer within the material stack structure (i.e., the sacrificial semiconductor material layer 12, the first silicon channel material layer 14, the epitaxial oxide layer 16 and the second silicon channel material layer 18) may have a thickness from 5 nm to 12 nm. The thickness of each layer within the material stack structure may be the same or different.

(30) Referring now to FIG. 2, there is illustrated the exemplary semiconductor radiation monitor of FIG. 1 after forming a sacrificial gate structure 20 and a dielectric spacer material layer 22 on a surface of the material stack structure (12, 14, 16, 18). The sacrificial gate structure 20 is located on a first side and a second side of the material stack structure, and spans across a topmost surface of a portion of the material stack structure. The sacrificial gate stack 20 thus straddles over a portion of the material stack structure. A dielectric spacer material layer 22 is present on the exposed surfaces of the sacrificial gate structure 20.

(31) The sacrificial gate structure 20 may include a single sacrificial material or a stack of two or more sacrificial materials (i.e., the sacrificial gate structure 20 includes at least one sacrificial material). In one embodiment, the at least one sacrificial material comprises, from bottom to top, a sacrificial gate dielectric material, a sacrificial gate material and a sacrificial dielectric cap. In some embodiments, the sacrificial gate dielectric material and/or the sacrificial dielectric cap can be omitted and only a sacrificial gate material is formed. The at least one sacrificial material can be formed by forming a blanket layer (or layers) of a material (or various materials) and then patterning the material (or various materials) by lithography and an etch. In one embodiment, the at least one sacrificial material can be formed by first depositing a blanket layer of a sacrificial gate dielectric material. The sacrificial gate dielectric material can be an oxide, nitride, and/or oxynitride. In one example, the sacrificial gate dielectric material can be a high k material having a dielectric constant greater than silicon dioxide. In some embodiments, a multilayered dielectric structure comprising different dielectric materials, e.g., silicon dioxide, and a high k dielectric can be formed and used as the sacrificial gate dielectric material. The sacrificial gate dielectric material can be formed by any deposition technique including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition.

(32) After forming the blanket layer of sacrificial gate dielectric material, a blanket layer of a sacrificial gate material can be formed on the blanket layer of sacrificial gate dielectric material. The sacrificial gate material can include any material including, for example, polysilicon, amorphous silicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals or multilayered combinations thereof. The sacrificial gate material can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes.

(33) After forming the blanket layer of sacrificial gate material, a blanket layer of a sacrificial gate cap material can be formed. The sacrificial gate cap material may include a hard mask material such as, for example, silicon dioxide and/or silicon nitride. The sacrificial gate cap material can be formed by any suitable deposition process such as, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition.

(34) After providing the above mentioned sacrificial material stack (or any subset of the sacrificial materials), lithography and etching can be used to pattern the sacrificial material stack (or any subset of the sacrificial materials) and to provide the sacrificial gate structure 20.

(35) The dielectric spacer material layer 22 can be formed by deposition of a dielectric spacer material and then etching the dielectric spacer material. One example of a dielectric spacer material that may be employed in the present application is silicon nitride. The deposition process that can be employed in providing the dielectric spacer material includes, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). The etch used to etch the deposited dielectric spacer material may comprise a dry etching process such as, for example, reactive ion etching.

(36) Referring now to FIG. 3, there is illustrated the exemplary semiconductor radiation monitor of FIG. 2 after removing physically exposed portions of the material stack structure (12, 14, 16, 18) that are not protected by the sacrificial gate structure 20 and the dielectric spacer material layer 22 to provide a nanosheet material stack of, and from bottom to top, a sacrificial semiconductor material nanosheet 12NS, a first silicon channel material nanosheet 14NS, an epitaxial oxide nanosheet 16NS, and a second silicon channel material nanosheet 18NS located beneath the sacrificial gate structure 20 and the dielectric spacer material layer 22. The sacrificial semiconductor material nanosheet 12NS, the first silicon channel material nanosheet 14NS, the epitaxial oxide nanosheet 16NS, and the second silicon channel material nanosheet 18NS represent non-removed material layer portions of the material stack structure (12, 14, 16, 18).

(37) The removal of the physically exposed portions of the material stack structure (12, 14, 16, 18) not covered by the sacrificial gate structure 20 and the dielectric spacer material layer 22 can be performed utilizing an anisotropic etching process such as, for example, reactive ion etching (RIE). A portion of the material stack structure (12, 14, 16, 18) remains beneath the sacrificial gate structure 20 and the dielectric spacer material layer 22. The remaining portion of the material stack structure (12, 14, 16, 18) that is presented beneath the sacrificial gate structure 20 and the dielectric spacer material layer 22 can be referred to as a nanosheet material stack. As stated above, the nanosheet material stack structure includes a sacrificial semiconductor material nanosheet 12NS, a first silicon channel material nanosheet 14NS, an epitaxial oxide nanosheet 16NS, and a second silicon channel material nanosheet 18NS.

(38) Each nanosheet, i.e., the sacrificial semiconductor material nanosheet 12NS, the first silicon channel material nanosheet 14NS, the epitaxial oxide nanosheet 16NS, and the second silicon channel material nanosheet 18NS, that constitutes the nanosheet material stack has a thickness as mentioned above for the individual layers of the material stack, and a width from 30 nm to 200 nm. At this point of the present application and as illustrated in FIG. 3, the sidewalls of the nanosheets (i.e., the sacrificial semiconductor material nanosheet 12NS, the first silicon channel material nanosheet 14NS, the epitaxial oxide nanosheet 16NS, and the second silicon channel material nanosheet 18NS) are vertically aligned to each other as well as to an outmost sidewall of the dielectric spacer material layer 22.

(39) Referring now to FIG. 4, there is illustrated the exemplary semiconductor radiation monitor of FIG. 3 after recessing the sacrificial semiconductor material nanosheet 12NS and forming an inner dielectric spacer 24S on exposed sidewalls of the recessed sacrificial semiconductor material nanosheet 12R. The recessed sacrificial semiconductor material nanosheet is designated as element 12R in the drawings of the present application. The recessed sacrificial semiconductor material nanosheet 12R has a width that is less than the original width of the sacrificial semiconductor material nanosheet 12NS. The recessing of the sacrificial semiconductor material nanosheet 12NS provides a gap (not specifically shown) between the first silicon channel material nanosheet 14NS and the semiconductor substrate 10. The recessing of the sacrificial semiconductor material nanosheet 12NS may be performed utilizing a lateral etching process that is selective in removing physically exposed end portions of the sacrificial semiconductor material nanosheet 12NS relative to the first and second silicon channel material nanosheet (14NS, 18NS), and the epitaxial oxide nanosheet 16NS.

(40) The inner dielectric spacer 24S is formed in the gap that is formed by the recessing of the sacrificial semiconductor material nanosheet 12NS. The inner dielectric spacer 24S is formed by deposition of a dielectric spacer material and etching the deposited dielectric spacer material. The dielectric spacer material that provides the inner dielectric spacer 24S may be the same as, or different from, the dielectric spacer material that provides the dielectric spacer material layer 22. As is shown, the inner dielectric spacer 24S has an innermost sidewall that directly contacts a sidewall of the recessed sacrificial semiconductor material nanosheet, and an outermost sidewall that is vertically aligned with the sidewalls of the first and second silicon channel material nanosheets (14NS, 18NS), the epitaxial oxide nanosheet 16NS, and the dielectric spacer material layer 22.

(41) Referring now to FIG. 5, there is illustrated the exemplary semiconductor radiation monitor of FIG. 4 after forming a source/drain structure 26 on each side of the nanosheet material stack. As is illustrated, the source/drain structure 26 is in direct physically contact with a physically exposed sidewall of the first silicon channel material nanosheet 14NS and a physically exposed sidewall of the second silicon channel material nanosheet 18NS. The source/drain structure 26 has a bottommost surface that may, or may not, be in direct physically contact with an exposed topmost surface of semiconductor substrate 10. In some embodiments and as shown in FIG. 5, the source/drain structure 26 may have a faceted (i.e., non-planar) topmost surface. In other embodiments (not shown), the source/drain structure 26 may have a planar topmost surface.

(42) The source/drain structure 26 can be formed by epitaxial growth of a semiconductor material on physically exposed sidewalls of the first and second silicon channel material nanosheet (14NS, 18NS) and, optionally, upwards from the semiconductor substrate 10. The source/drain structure 26 includes a semiconductor material and a dopant. The semiconductor material that provides source/drain structure 26 can be selected from one of the semiconductor materials mentioned above for the semiconductor substrate 10. In some embodiments of the present application, the semiconductor material that provides source/drain structure 26 may be composed of silicon.

(43) The dopant that is present in source/drain structure 26 can be either a p-type dopant or an n-type dopant. The term p-type refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium. N-type refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. In one example, the source/drain structure 26 may have a dopant concentration of from 410.sup.20 atoms/cm.sup.3 to 310.sup.21 atoms/cm.sup.3. In one embodiment, the source/drain structure 26 is composed of phosphorous doped silicon. In another embodiment, the source/drain structure 26 is composed of a boron doped silicon germanium alloy.

(44) In one embodiment, the dopant that can be present in the source/drain structure 26 can be introduced into the precursor gas that provides the source/drain structure 26. In another embodiment, the dopant can be introduced into an intrinsic semiconductor layer by utilizing one of ion implantation or gas phase doping.

(45) Referring now to FIG. 6, there is illustrated the exemplary semiconductor radiation monitor of FIG. 5 after forming an interlayer dielectric (ILD) material layer 30 on the source/drain structure 26. As is shown, the ILD material layer 30 has a topmost surface that is coplanar with a topmost surface of the dielectric spacer material layer 22.

(46) The interlayer dielectric (ILD) material layer 30 may be composed of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer or any combination thereof. The term low-k as used throughout the present application denotes a dielectric material that has a dielectric constant of less than silicon dioxide. In another embodiment, a self-planarizing material such as a spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK can be used as ILD material layer 30. The use of a self-planarizing dielectric material as the ILD material layer 30 may avoid the need to perform a subsequent planarizing step.

(47) In one embodiment, the ILD material layer 30 can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation or spin-on coating. In some embodiments, particularly when non-self-planarizing dielectric materials are used as the ILD material layer 30, a planarization process or an etch back process follows the deposition of the dielectric material that provides the ILD material layer 30.

(48) Referring now to FIG. 7, there is illustrated the exemplary semiconductor radiation monitor of FIG. 6 after removing the sacrificial gate structure 20. Prior to removing the sacrificial gate structure 20, a horizontal portion of dielectric spacer material layer 22 is removed from atop the sacrificial gate structure 20 to provide a topmost inner gate spacer 22S.

(49) The removal of the horizontal portion of the dielectric spacer material layer 22 and the sacrificial gate structure 20 can be performed utilizing one or more anisotropic etching processes. The removal of the sacrificial gate structure 20 provides an upper gate cavity 32.

(50) Referring now to FIG. 8, there is illustrated the exemplary semiconductor radiation monitor of FIG. 7 after removing the recessed sacrificial semiconductor material nanosheet 12R. The recessed sacrificial semiconductor material nanosheet 12R can be removed by utilizing an etching process that is selective in removing the recessed sacrificial semiconductor material nanosheet 12R. After removing the recessed sacrificial semiconductor material nanosheet, a portion of the first silicon channel material nanosheet is suspended above the semiconductor substrate 10 and a lower gate cavity 34 is formed.

(51) Referring now to FIG. 9, there is illustrated the exemplary semiconductor radiation monitor of FIG. 8 after forming a functional gate structure (38, 40) in an area previously containing the recessed sacrificial semiconductor material nanosheet 12R (i.e., within the lower gate cavity 34) and the area previously including the sacrificial gate structure 20 (i.e., with the upper gate cavity 32). By functional gate structure it is meant a permanent gate structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields.

(52) The functional gate structure (38, 40) may include a gate dielectric portion 38 and a gate conductor portion 40. The gate dielectric portion 38 may include a gate dielectric material. The gate dielectric material that provides the gate dielectric portion 38 can be an oxide, nitride, and/or oxynitride. In one example, the gate dielectric material that provides the gate dielectric portion 38 can be a high-k material having a dielectric constant greater than silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO.sub.2, ZrO.sub.2, La.sub.2O.sub.3, Al.sub.2O.sub.3, TiO.sub.2, SrTiO.sub.3, LaAlO.sub.3, Y.sub.2O.sub.3, HfO.sub.xN.sub.y, ZrO.sub.xN.sub.y, La.sub.2O.sub.xN.sub.y, Al.sub.2O.sub.xN.sub.y, TiO.sub.xN.sub.y, SrTiO.sub.xN.sub.y, LaAlO.sub.xN.sub.y, Y.sub.2O.sub.xN.sub.y, SiON, SiN.sub.x, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. In some embodiments, a multilayered gate dielectric structure comprising different gate dielectric materials, e.g., silicon dioxide, and a high-k gate dielectric, can be formed and used as the gate dielectric portion 38.

(53) The gate dielectric material used in providing the gate dielectric portion 38 can be formed by any deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. In one embodiment of the present application, the gate dielectric material used in providing the gate dielectric portion 38 can have a thickness in a range from 1 nm to 10 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate dielectric material that may provide the gate dielectric portion 38.

(54) The gate conductor portion 40 can include a gate conductor material. The gate conductor material used in providing the gate conductor portion 40 can include any conductive material including, for example, doped polysilicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicide (e.g., tungsten silicide, nickel silicide, and titanium silicide) or multilayered combinations thereof. In one embodiment, the gate conductor portion 34 may comprise an nFET gate metal. In another embodiment, the first gate conductor portion 40 may comprise a pFET gate metal.

(55) The gate conductor material used in providing the gate conductor portion 40 can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes. When a metal silicide is formed, a conventional silicidation process is employed. In one embodiment, the gate conductor material used in providing the gate conductor portion 40 can have a thickness from 50 nm to 200 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate conductor material used in providing the gate conductor portion 40.

(56) The functional gate structure (38, 40) can be formed by providing a functional gate material stack of the gate dielectric material, and the gate conductor material. A planarization process may follow the formation of the functional gate material stack, and a recess etch may be used to remove the functional gate structure (38, 40) from the upper and lower gate cavities (32, 34). In the present application, a first FET is formed that includes the first silicon channel material nanosheet 14NS and the functional gate structure (38, 40) that is formed in the lower gate cavity 34, and a second FET is formed that includes the second silicon channel material nanosheet 18NS and the functional gate structure (38, 40) that is present in upper gate cavity 32. These two FETs share a common source/drain structure.

(57) Referring now to FIG. 10, there is illustrated the exemplary semiconductor radiation monitor of FIG. 9 after forming contact structures 42. Contact structures 42 can be formed by first providing contact openings to expose each source/drain structure 26 of the structure. The contact openings can be formed by lithography and etching. Each contact opening is then filled with a contact metal or metal alloy. Examples of contact metals include, but are not limited to, tungsten (W), aluminum (Al), copper (Cu), or cobalt (Co). An example of a contact metal alloy is CuAl alloy. A planarization process may follow the filling of each contact opening with the contact metal or metal alloy. The contact structures 42 are embedded in the ILD material layer 30.

(58) FIG. 10 illustrates an exemplary semiconductor radiation monitor of the present application which includes nanosheet stack including a charge storage dielectric material nanosheet (i.e., the epitaxial oxide nanosheet 16NS) sandwiched between a first silicon channel material nanosheet 14NS and a second silicon channel material nanosheet 18NS, and suspended above a semiconductor substrate 10. A functional gate structure (38, 40) is located beneath the first silicon channel material nanosheet 14NS and above the second silicon channel material nanosheet 18NS. In this embodiment, the epitaxial oxide nanosheet 16NS, and the first and second silicon channel material nanosheets (14NS, 18NS) have a same width and thus the outermost sidewalls of each of epitaxial oxide nanosheet 16NS and the first and second silicon channel material nanosheets (14NS, 18NS) are vertically aligned to each other. In this embodiment, the first and second silicon channel material nanosheets (14NS, 18NS) share a common source/drain region 26. The radiation detection sensitivity of the semiconductor radiation monitor shown in FIG. 10 can be enhanced by varying the channel length (i.e., the width) of the silicon channel material nanosheets within the nanosheet stack.

(59) The semiconductor radiation monitor shown in FIG. 10 detects radiation using the same detection mechanism as prior art FDSOI radiation monitors. For example, the semiconductor radiation monitor shown in FIG. 10 detects radiation by the shift in threshold voltage of the nanosheet FETs (including elements 38/40/14NS and 38/40/18NS) caused by the positive charges, which are created by ionizing radiations and trapped in the dielectric material nanosheet (i.e., epitaxial oxide nanosheet 16NS) between the Si channel material nanosheets (14NS and 18NS). Such a layered nanosheet structure is capable of detecting lower radiation doses than the planar FDSOI counterpart as both the top and bottom Si channel material nanosheets (14NS and 18NS) can sense the existence of the positive charges trapped in the epitaxial oxide nanosheet 16NS.

(60) The semiconductor radiation monitor shown in FIG. 10 has the following additional benefits over prior art FDSOI radiation monitors. Firstly, the semiconductor radiation monitor shown in FIG. 10 has a tighter device density (larger surface area as compared to prior art FDSOI radiation monitors. Secondly, the semiconductor radiation monitor shown in FIG. 10 is capable of detecting a lower radiation dose (less than, or equal to 100 rads). Thirdly, the semiconductor radiation monitor shown in FIG. 10 can be fabricated at a lower cost than prior art FDSOI radiation monitors.

(61) Referring now to FIG. 11, there is illustrated another exemplary semiconductor radiation monitor in accordance with the present application. The exemplary semiconductor radiation monitor shown in FIG. 11 is similar to the exemplary semiconductor radiation monitor shown in FIG. 10 except that the epitaxial oxide nanosheet 14NS (i.e., the charge storage dielectric material nanosheet) is replaced with a dielectric oxide material nanosheet 44 that is capable of storing positive charge upon use. In this embodiment, the dielectric oxide material nanosheet 44 has a width that is less than a width of the first and second silicon channel material nanosheets, and wherein an inner spacer 24S is located at the end of the charge storage dielectric material nanosheet 44.

(62) The exemplary semiconductor radiation monitor shown in FIG. 11 can be formed by first forming a nanosheet material stack of, and from bottom to top, a first sacrificial silicon germanium alloy nanosheet having a first germanium content, a first silicon channel material nanosheet, a second sacrificial silicon germanium alloy nanosheet having a second germanium content that is greater than the first germanium content, and a second silicon channel material nanosheet on a surface of a semiconductor substrate and beneath a sacrificial gate structure and a dielectric spacer material layer. The second sacrificial silicon germanium alloy nanosheet replaces the epitaxial oxide nanosheet 16NS shown in FIG. 3, and such a nanosheet material stack can be formed utilizing the same processing steps as mentioned above in forming the structures shown in FIGS. 1-3 of the present application. In one embodiment, the first germanium content can be from 15 atomic percent germanium to 25 atomic percent germanium, while the second germanium content can be from 40 atomic percent germanium to 40 atomic percent germanium. As such, the sacrificial silicon germanium alloy nanosheets have different etch rates. Notably, the second sacrificial silicon germanium alloy nanosheet etches faster than the first sacrificial silicon germanium alloy nanosheet.

(63) Next, the first and second sacrificial silicon germanium alloy nanosheets are recessed, as described above for providing the exemplary structure shown in FIG. 4, and inner spacer 24S is formed, as also described above. It is noted that the recessing provides a first gap between the first silicon channel material nanosheet and the semiconductor substrate, and a second gap, which is larger than the first gap, between the first and second silicon channel material nanosheets. It is further noted that the inner spacer 24S formed adjacent to the recessed second sacrificial silicon germanium alloy nanosheet will be wider than the inner spacer 24S formed adjacent to the recessed first sacrificial silicon germanium alloy nanosheet.

(64) The source drain/structure 26 and the ILD material layer 30 are then formed as described above in providing the exemplary structures shown in FIGS. 5 and 6 of the present application. Next, the sacrificial gate structure is removed as described above in providing the exemplary structure shown in FIG. 7 of the present application. Following the removal of the sacrificial gate structure, the recessed second sacrificial silicon germanium alloy nanosheet is then removed, and thereafter the area previously occupied by the recessed second sacrificial silicon germanium alloy nanosheet is filled with a dielectric oxide such as, for example, SiO.sub.2, SiON, Al.sub.2O.sub.3, SiNx, and BN. forming the dielectric oxide material nanosheet 44. The filling with the dielectric oxide may include deposition and a recess etch.

(65) After providing the dielectric oxide material nanosheet 44, the recessed first silicon germanium alloy nanosheet is removed utilizing an etching process such that lower gate cavity is formed. Next, functional gate structure (38, 40) is formed as described above for providing the exemplary structure shown in FIG. 9, and thereafter contact structures 42 are formed as described above in providing the exemplary structure shown in FIG. 10.

(66) The exemplary semiconductor radiation monitor shown in FIG. 11 works the same as the exemplary semiconductor radiation monitor shown in FIG. 10. The exemplary semiconductor radiation monitor shown in FIG. 11 has the same advantages as the exemplary semiconductor radiation monitor shown in FIG. 10.

(67) While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.