Valley-fill PFC circuit with EMI protection

Abstract

A power control circuit includes an alternating current (AC) power source, a rectifier and a valley-fill circuit. The AC power source is configured to receive an AC voltage. The rectifier is configured to convert the AC voltage into a rectified voltage. The valley-fill circuit includes: an inductor, having a first terminal coupled to the rectifier, and a second terminal; a first resistor, having a first terminal coupled to the second terminal of the inductor, and a second terminal; a diode, having a cathode coupled to the second terminal of the inductor, and an anode; and a first capacitor, having a first terminal coupled to the second terminal of the first resistor and the anode of the diode, and a second terminal coupled to ground.

Claims

1. An power control circuit, comprising: an alternating current (AC) power source, configured to receive an AC voltage; a rectifier, configured to convert the AC voltage into a rectified voltage; a valley-fill circuit, comprising: an inductor, having a first terminal coupled to the rectifier, and a second terminal; a first resistor, having a first terminal coupled to the second terminal of the inductor, and a second terminal; a diode, having a cathode coupled to the second terminal of the inductor, and an anode; a first capacitor, having a first terminal coupled to the second terminal of the first resistor and the anode of the diode, and a second terminal coupled to ground; a second resistor, having a first terminal coupled to the first terminal of the inductor, and a second terminal coupled to the first terminal of the first resistor; and a second capacitor, having a first terminal coupled to the first terminal of the second resistor, and a second terminal coupled to ground.

2. The power control circuit of claim 1, wherein the rectifier is a diode-bridge rectifier.

3. The power control circuit of claim 1, wherein the valley-fill circuit is further coupled to an DC-to-DC converter to provide a constant current or a constant voltage output for an LED driving circuit.

4. The power control circuit of claim 3, wherein a switched-mode power supply (SMPS) is coupled between the valley-fill circuit and the LED driving circuit.

5. The power control circuit of claim 1, further comprising: a metal-oxide varistor (MOV) unit, coupled between the AC power source and the rectifier; and a fuse 220, coupled between the AC power source and the MOV unit.

6. The power control circuit of claim 1, wherein the valley-fill circuit further comprises: a third capacitor, having a first terminal coupled to the first terminal of the first resistor, and a second terminal coupled to ground.

7. The power control circuit of claim 1, wherein the output of the valley-fill circuit is in form of a rectified sinusoidal wave.

8. The power control circuit of claim 1, wherein the first capacitor is charged through the inductor and the first resistor, and the first capacitor is discharged through the diode.

9. An power control circuit, comprising: an alternating current (AC) power source, configured to receive an AC voltage; a rectifier, configured to convert the AC voltage into a rectified voltage; a valley-fill circuit, comprising: an inductor, having a first terminal coupled to the rectifier, and a second terminal; a first resistor, having a first terminal coupled to the second terminal of the inductor, and a second terminal; a diode, having a cathode coupled to the second terminal of the inductor, and an anode; and a first capacitor, having a first terminal coupled to the second terminal of the first resistor and the anode of the diode, and a second terminal coupled to ground; wherein the output of the valley-fill circuit is in form of a rectified sinusoidal wave, and the capacitance of the first capacitor meets following equations: $C_V\frac{I_{\mathrm{Load},\max }{t}_{\mathrm{Hold}}}{V_C};$ $t_{\mathrm{Hold}}=\frac{1}{2f}\left({\sin }^{-1}\frac{V_1}{V_{m,\min }}+{\sin }^{-1}\frac{V_2}{V_{m,\min }}\right);$ $\frac{1}{2f}-t_{\mathrm{Hold}}=t_{chg};$ $I_{chg}=\frac{V_{m,\min }-V_C}{R_V};$ $V_c=\frac{I_{chg}*t_{chg}}{C_V};$ $\frac{V_C}{V_{m,\min }}=\frac{t_{chg}}{R_V{C}_V+t_{chg}};$ $\frac{\left(\frac{V_{m,\min }}{V_c}-1\right)t_{chg}}{C_V}{R}_V;$ wherein C.sub.V represents the capacitance of the first capacitor, V.sub.C represents the voltage variation of the capacitance V.sub.C, I.sub.load,max represents the maximum current on the output load, f represents a cycle of the rectified sinusoidal wave, V.sub.1 represents an initial level of the rectified sinusoidal wave during a capacitor discharging time, V.sub.2 represents a final level of the rectified sinusoidal wave during the capacitor discharging time, V.sub.m,min represents the minimum of the peak value of the voltage amplitude V.sub.m, t.sub.Hold represents the capacitor discharging time, t.sub.chg represents the capacitor charging time, I.sub.chg represents the charging current, and R.sub.V represents the resistance of the first resistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a diagram illustrating the charging operation of a conventional PF control circuit.

(2) FIG. 1B is a diagram illustrating the discharging operation of the conventional PF control circuit shown in FIG. 1A.

(3) FIG. 2 is a diagram illustrating a PF control circuit according to an embodiment of the present invention.

(4) FIG. 3 is a diagram illustrating a PF control circuit according to another embodiment of the present invention.

(5) FIG. 4 is a diagram illustrating the output of the valley-fill circuit shown in FIG. 3.

(6) FIG. 5 is a diagram illustrating a PF control circuit according to yet another embodiment of the present invention.

DETAILED DESCRIPTION

(7) Some phrases in the present specification and claims refer to specific elements; however, please note that the manufacturer might use different terms to refer to the same elements. Further, in the present specification and claims, the term comprising is open type and should not be viewed as the term consists of. The term electrically coupled can refer to either direct connection or indirect connection between elements. Thus, if the specification describes that a first device is electrically coupled to a second device, the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or means.

(8) The aforementioned related art solution (or other conventional solutions) reaches the desired power controlling ability by sacrificing in higher cost, complicated design complexity, more passive elements (which causes the circuit area to be larger), etc.

(9) The embodiments of the present invention provide novel circuitry designs with reduced cost and complexity as follows.

(10) Please refer to FIG. 2, which is a diagram illustrating a PF control circuit 200 according to an embodiment of the present invention. As shown in FIG. 2, the inductor L, diode D, resistor R.sub.V and the capacitor C.sub.V in FIG. 2 can be jointly viewed as an integrated EMI-Valley circuit (i.e. the valley-fill circuit 270) for eliminating the above disadvantages while an ideal technical effect can still be achieved. In addition to the valley-fill circuit 270, the PF control circuit 200 further comprises an AC current source 210, a fuse 220, a metal-oxide varistor (MOV) unit 230, a rectifying circuit 240, a switched-mode power supply (SMPS) 250 and an LED array 260. As long as same/similar technical effects can be achieved, some elements depicted in FIG. 2 can be omitted based on actual design requirements.

(11) The MOV unit 230 is an electronic component with an electrical resistance that varies with the applied voltage. Also known as a voltage-dependent resistor (VDR), it has a nonlinear, non-ohmic current-voltage characteristics similar to those of a diode. In contrast to a diode, it has the same characteristic for both directions of traversing current. The MOV unit 230 can be used as a control or compensation element in the PF control circuit 200, either to provide optimal operating conditions or to protect against excessive transient voltages.

(12) The a rectifying circuit 240 can be a diode-bridge rectifier (also called as bridge rectifier). For illustrative purposes, a diode-bridge rectifier is an arrangement of four (or more) diodes in a bridge circuit configuration that provides the same polarity of output for either polarity of input. It is widely applied for conversion of an alternating-current (AC) input into a direct-current (DC) output.

(13) The SMPS 250 converts power using switching devices that are turned on and off at high frequencies, and storage components such as inductors or capacitors to supply power when the switching device is in its non-conduction state. The SMPS can be also used to power a wide variety of equipment such as computers, sensitive electronics, battery-operated devices and other equipment requiring high efficiency.

(14) Specifically, the configuration of the inductor L and the capacitor C.sub.V may provide the PF control circuit 200 with the EMI-suppressing ability, and the configuration of the diode D, the resistor R.sub.V and the capacitor C.sub.V may provide the PF control circuit 200 with the valley-filling ability, wherein the combination of the diode D, the resistor R.sub.V and the capacitor C.sub.V provides functions similar to the combination of the R.sub.V, the capacitor C.sub.V and the diode D3 shown in FIG. 1. Compared with the charging/discharging manners shown in FIG. 1/FIG. 2), the charging/discharging manners may improve the symmetry performance, thereby solving the problems faced in related art techniques.

(15) Please refer to FIG. 3, which is a diagram illustrating a PF control circuit 300 according to another embodiment of the present invention. The difference between the PF control circuits 200 and 300 is that the valley-fill circuit 370 further comprises the resistor R.sub.F and the capacitor C.sub.F1. The combination of the capacitor C.sub.F1, the inductor L and the capacitor C.sub.V forms a n-shape EMI circuit, which may provide better EMI-suppressing characteristics.

(16) To ensure the switched-mode power supply (SMPS) 250 receives the optimal input voltage, such as the rectified sinusoidal wave shown in FIG. 4 that outputted by the valley-fill circuit 370, the capacitance of the capacitor C.sub.V shall be specifically designed to meet certain conditions. Taking FIG. 4 as example, the dotted flat line denotes the voltage provided to the load of the LED array 260 with the magnitude being V.sub.LED_max. The ascending part of the dotted saw tooth line denotes the charging period, and the descending part of the dotted saw tooth line denotes the holding period. The constant (almost perfect) curve of V.sub.LED_max attributes to the carefully designed value of C.sub.V (shown in Italics for representing the capacitance of the capacitor C.sub.V), wherein the value of C.sub.V can be derived from following equations:

(17) $\begin{array}{cc}{C}_V\frac{I_{\mathrm{Load},\max }{t}_{\mathrm{Hold}}}{V_c}& \left(1\right)\\ t_{\mathrm{Hold}}=\frac{1}{2f}\left({\sin }^{-1}\frac{V_1}{V_{m,\min }}+{\sin }^{-1}\frac{V_2}{V_{m,\min }}\right)& \left(2\right)\\ \frac{1}{2f}-t_{\mathrm{Hold}}=t_{chg}& \left(3\right)\\ I_{chg}=\frac{V_{m,\min }-V_C}{R_V}& \left(4\right)\\ V_c=\frac{I_{chg}*t_{chg}}{C_V}& \left(5\right)\\ \frac{V_C}{V_{m,\min }}=\frac{t_{chg}}{R_V{C}_V+t_{chg}}& \left(6\right)\\ \frac{\left(\frac{V_{m,\min }}{V_c}-1\right)t_{chg}}{C_V}{R}_V& \left(7\right)\end{array}$

(18) Please refer to equation 1 (hereinafter Eq. 1), C.sub.V must be larger than or equal to the given condition so that the LED array 260 can get the desired supply voltage, wherein V.sub.C represents the voltage variation of the capacitance V.sub.C, I.sub.load,max represents the maximum current on the output load, V.sub.m,min represents the minimum of the peak value of the voltage amplitude V.sub.m, and t.sub.Hold represents the capacitor discharging time which can be calculated through Eq. 2. In Eq. 3, the capacitor charging time t.sub.chg can be obtained by deducting t.sub.Hold from the cycle f. I.sub.chg is defined in Eq. 4, and the result in Eq. 6 can be easily deducted from Eq. 4 and Eq. 5. In addition, I.sub.chg represents the charging current, and R.sub.V represents the resistance of the resistor R.sub.V. Finally, the result in Eq. 7 can be obtained by substituting Eq. 6 into Eq. 1.

(19) FIG. 5 is a diagram illustrating a PF control circuit 500 according to yet another embodiment of the present invention. The difference between the PF control circuits 300 and 500 is that the valley-fill circuit 570 further comprises the capacitor C.sub.F2, which also helps present an optimal output. Some elements in this embodiment are similar/identical to those in the previous embodiments, and detailed descriptions thereof are omitted here for brevity.

(20) In view of the above, embodiments of the present invention are able to improve the overall power factor of a power control circuit and also provide EMI suppressing ability, with reduced overall cost and simplified design complexity. For example, embodiments of the present invention adopt integrated EMI-valley circuit design, which requires less elements (compared with related art solutions shown in FIGS. 1A and 1B) without sacrificing any required technical effects.

(21) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.