Nonlinear receiver, asymmetric decision feedback equalization circuit and method

Abstract

The present disclosure provides a non-linear receiver, an asymmetric decision feedback equalization circuit and method, including: converting an optical signal emitted by a laser device into an electrical signal; obtaining a compensation amplitude of a current data in the electrical signal by obtaining an actual amplitude of the current data, and compensating the current data based on a logic value of k prior data of the current data and a feedback coefficient corresponding to the prior data; comparing the compensation amplitude of the current data with a decision threshold to determine the logic value of the current data; the feedback coefficient is an absolute value of an influence amount of the prior data on an amplitude of the current data, and k is a positive integer. The present disclosure can overcome the bit error problem of the receiver and reduce jitter of the clock recovered by the clock recovery circuit.

Claims

1. An asymmetric decision feedback equalization method, at least comprising: converting an optical signal emitted by a laser device into an electrical signal; obtaining a compensation amplitude of a current data in the electrical signal by obtaining an actual amplitude of the current data, and compensating the current data based on a logic value of k prior data of the current data and a feedback coefficient corresponding to the prior data, wherein the compensating of the current data comprises: sequentially acquiring the prior data of the current data to obtain the compensation amplitude of the current data, wherein when the prior data is at logic high, subtracting the feedback coefficient corresponding to the prior data from the actual amplitude of the current data, and when the prior data is at logic low, adding the feedback coefficient corresponding to the prior data to the actual amplitude of the current data; and comparing the compensation amplitude of the current data with a decision threshold to determine a logic value of the current data, wherein the feedback coefficient is an absolute value of an influence amount of the prior data on an amplitude of the current data, and k is a positive integer.

2. The asymmetric decision feedback equalization method according to claim 1, further comprising: acquiring a logic value of each prior data; obtaining a compensation value by multiplying the logic value of each prior data with a corresponding feedback coefficient, then inverting a product of the logic value of each prior data and the corresponding feedback coefficient; and adding each compensation value and adding the added compensation value to the actual amplitude of the current data, to obtain the compensation amplitude of the current data.

3. The asymmetric decision feedback equalization method according to claim 1, wherein obtaining the feedback coefficient comprises: when the laser device emits a logic high pulse, obtaining the absolute value of the influence amount of the prior data on the amplitude of the current data when the prior data is at logic high based on a waveform of the logic high pulse; and when the laser device emits a logic low pulse, obtaining the absolute value of the influence amount of the prior data on the amplitude of the current data when the prior data is at logic low based on a waveform of the logic low pulse.

4. An asymmetric decision feedback equalization circuit, at least comprising: a data input module to receive input data and output a differential signal of each data; k compensation modules respectively connected to an output end of the data input module, to obtain a compensation amplitude of a current data by compensating the current data based on the logic value of a prior data of the current data and an feedback coefficient corresponding to the prior data; a comparison module connected to an output end of the data input module, to compare the compensation amplitude of current data with a decision threshold, to determine a logic value of the current data; and k trigger modules in one-to-one correspondence with the compensation modules, sequentially connected in series to an output end of the comparison module to sequentially obtain a logic value of each prior data of the current data, wherein k is a positive integer.

5. The asymmetric decision feedback equalization circuit according to claim 4, wherein the compensation module comprises a first compensation unit and a second compensation unit, wherein the first compensation unit is connected to an inverted output of the data input module; the second compensation unit is connected to a positive output of the data input module; and the first compensation unit and the second compensation unit are connected to the same prior data, and the first compensation unit or the second compensation unit is selectively turned on based on the logic value of the prior data.

6. The asymmetric decision feedback equalization circuit according to claim 5, wherein the first compensation unit comprises a first switch, one end of the first switch is connected to an inverted output of the data input module, the other end of the first switch is connected to a first compensation current; and the second compensation unit comprises a second switch, one end of the second switch is connected to the positive output of the data input module, and the other end of the second switch is connected to a second compensation current.

7. The asymmetric decision feedback equalization circuit according to claim 5, wherein the first compensation unit comprises a first NMOS transistor and a second NMOS transistor, wherein sources of the first NMOS transistor and the second NMOS transistor are connected to the first compensation current, a drain of the first NMOS transistor is connected to the inverted output of the data input module, a gate of the first NMOS transistor is connected to an inverted output signal of the prior data, a drain of the second NMOS transistor is connected to supply, and a gate of the second NMOS transistor is connected to a reference signal; and the second compensation unit comprises a third NMOS transistor and a fourth NMOS transistor, wherein sources of the third NMOS transistor and the fourth NMOS transistor are connected to the second compensation current, a drain of the third NMOS transistor is connected to supply, a gate of the third NMOS transistor is connected to the reference signal, a drain of the fourth NMOS transistor is connected a positive output of the data input module, and a gate of the fourth NMOS transistor is connected to a positive output signal of the prior data; wherein the reference signal is between an inverted signal and a positive signal of the prior data.

8. An asymmetric decision feedback equalization circuit, at least comprising: a compensation module to respectively compensate an amplitude of a current data based on a combination of different feedback coefficients corresponding to a sequence of k prior data, and latch the compensation data as a prior data of a next current data; and a selection module connected to an output of the compensation module, to determine feedback coefficients corresponding to each prior data, thereby determining the amplitude of the current data after compensation; wherein k is a positive integer.

9. The asymmetric decision feedback equalization circuit according to claim 8, wherein the selection module comprises k level alternative units and triggers connected to each alternative unit; a number of alternative units at each level is decreasing exponentially by 2; and feedback coefficients corresponding to the sequence of the prior data are different.

10. A non-linear receiver, at least comprising: a continuous time linear equalization circuit to receive an electrical signal converted by an optical signal emitted by a laser device, and improve performance of the electrical signal; an asymmetric decision feedback equalization circuit according to claim 8, connected to an output of the continuous time linear equalization circuit, to compensate a signal after continuous time linear equalization circuit; and a clock data recovery circuit connected to an output of the asymmetric decision feedback equalization circuit, to recover a sampling clock and data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram illustrating an asymmetric PAM-2 (or NRZ) eye diagram of optical signal generated by nonlinearity of laser device in the prior art.

(2) FIG. 2 is a diagram illustrating an asymmetric PAM-4 eye diagram of optical signal with nonlinearity of laser device, noise, and inter-symbol interference in the prior art.

(3) FIG. 3 is a diagram illustrating the generation of inter-symbol interference.

(4) FIG. 4 is a diagram illustrating a flow chart of an asymmetric decision feedback equalization method according to the present disclosure.

(5) FIG. 5 is a diagram illustrating the principle of determining the feedback coefficient when the prior data is at logic high according to the present disclosure.

(6) FIG. 6 is a diagram illustrating the principle of determining the feedback coefficient when the prior data is at logic low according to the present disclosure.

(7) FIG. 7 is a diagram illustrating the principle of asymmetric eye diagram according to the present disclosure.

(8) FIG. 8 is a diagram illustrating the logic blocks of asymmetric decision feedback equalization method according to the present disclosure.

(9) FIG. 9 is a diagram illustrating an example of the asymmetric decision feedback equalization according to the present disclosure.

(10) FIG. 10 is a diagram illustrating another example of the asymmetric decision feedback equalization according to the present disclosure.

(11) FIG. 11 is a diagram illustrating another example of the asymmetric decision feedback equalization according to the present disclosure.

(12) FIG. 12 is a diagram illustrating architecture of nonlinear receiver according to the present disclosure.

(13) FIG. 13 is a diagram illustrating an eye diagram after compensation according to the present disclosure.

DESCRIPTION OF COMPONENT MARK NUMBERS

(14) 1 Asymmetric decision feedback equalization circuit

(15) 11 Data input module

(16) 12a-12c Compensation module

(17) 13 Comparison module

(18) 14a-14b Trigger module

(19) 2 Asymmetric decision feedback equalization circuit

(20) 21 Compensation module

(21) 211 First compensation unit

(22) 211a First comparator

(23) 211b First trigger

(24) 22 Selection module

(25) 221 First alternative unit

(26) 222 Second alternative unit

(27) 223 Fifth trigger

(28) 224 Sixth trigger

(29) 225 Third alternative unit

(30) 226 Seventh trigger

(31) 3 Nonlinear receiver

(32) 4 Continuous time linear equalization circuit

(33) 5 Asymmetric decision feedback equalization circuit

(34) 6 Clock data recovery circuit

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(35) The embodiments of the present disclosure will be described below. Those skilled can easily understand other advantages and effects of the present disclosure according to contents disclosed by the specification. The present disclosure can also be implemented or applied through other different specific embodiments. Various modifications or changes can also be made to all details in the specification based on different points of view and applications without departing from the spirit of the present disclosure.

(36) It needs to be stated that the drawings provided in the following embodiments are just used for schematically describing the basic concept of the present disclosure, thus only illustrating components only related to the present disclosure and are not drawn according to the numbers, shapes and sizes of components during actual implementation, the configuration, number and scale of each component during actual implementation thereof may be freely changed, and the component layout configuration thereof may be more complex.

Embodiment 1

(37) As shown in FIG. 3, due to nonlinear characteristics of the laser, signals passing through the channel are distorted. By observing the asymmetric signal waveform, it can be found that the asymmetry is caused by unequal rise time and fall time of different data sequences. Taking the current data D.sub.n as an example, the waveform of the current data D.sub.n has a characteristic of rising fast (compared to falling) and falling slow (compared to rising). Therefore, when the waveform of the current data D.sub.n extends to the adjacent data, the adjacent data will be affected. When data are continuously transmitted, the mutual influence between the data causes inter-symbol interference. Once the interference causes the sampled data to exceed the decision threshold range, bit error happens.

(38) As shown in FIG. 4, the present embodiment provides an asymmetric decision feedback equalization method for compensating the asymmetry of data and solving the bit error problem. The asymmetric decision feedback equalization method includes:

(39) 1) Converting an optical signal emitted by a laser device into an electrical signal.

(40) Specifically, the optical signal emitted by the laser device is transmitted to the receiver through a channel, and is converted into a corresponding electrical signal by a photoelectric conversion device at the receiver side.

(41) 2) Obtaining an actual amplitude AMP.sub.actual of current data D.sub.n in the electrical signal, and compensating the current data D.sub.n based on k prior data of the current data D.sub.n and feedback coefficient corresponding to the k prior data, to obtain a compensated amplitude AMP.sub.compensation of the current data D.sub.n, k is a positive integer.

(42) Specifically, the electrical signal is sampled based on a sampling clock of the current data D.sub.n to obtain an actual amplitude AMP.sub.actual of the current data D.sub.n.

(43) Specifically, the current data D.sub.n is further compensated based on a logical value of the prior data and a feedback coefficient corresponding to the prior data. When the prior data is at logic high, the feedback coefficient corresponding to the prior data is subtracted from the actual amplitude AMP.sub.actual of the current data D.sub.n. When the prior data is at logic low, the feedback coefficient corresponding to the prior data is added to the actual amplitude AMP.sub.actual of the current data D.sub.n. In this embodiment, taking the first two prior data of the current data D.sub.n as an example, in actual use, the number k of prior data for compensation may be set according to the impulse response characteristic of the channel.

(44) More specifically, the method for obtaining the feedback coefficient in this embodiment is as follows. As shown in FIG. 5, a logic high pulse is transmitted by the laser, and data . . . 0001000 . . . is input, the data D.sub.n is at logic high. The sampling clock samples the amplitude of h.sub.0 after passing the channel (the position of each dotted line in the figure corresponds to each sampling clock). For the data D.sub.n1, when its subsequent data D.sub.n is at logic high, the amplitude is increased by h.sub.1. For the data D.sub.n+1, when its prior data D.sub.n is at logic high, the amplitude is increased by h.sub.1. For the data D.sub.n+2, when the prior data D.sub.n is at logic high, the amplitude is increased by h.sub.2. According to this, the influence on the amplitude of the current data can be obtained when the prior data is at logic high based on the waveform of the logic high pulse, and the absolute value of the influence is taken as the feedback coefficient of the current data when the prior data is at logic high. Similarly, as shown in FIG. 6, a logic low pulse is transmitted through the laser, and data . . . 1110111 . . . is input, where the data D.sub.n is at logic low, and the sampling clock samples the amplitude of h.sub.n after passing the channel. For the data D.sub.n1, when its subsequent data D.sub.n is at logic low, the amplitude is decreased by h.sub.1. For the data D.sub.n+2, when its prior data D.sub.n is at logic low, the amplitude is decreased by h.sub.1. For the data D.sub.n+2, when its prior data D.sub.n is at logic low, the amplitude is decreased by h.sub.2. According to this, the influence on the amplitude of the current data can be obtained when the prior data is at logic low based on the waveform of the logic low pulse, and the absolute value of the influence is taken as the feedback coefficient of the current data when the prior data is at logic low.

(45) Further, as shown in FIG. 7, in the asymmetric eye diagram, the high and low amplitudes of the signal at the sampling clock (sc1 and sc3 are signal edge sampling clock, and sc2 and sc4 are signal amplitude sampling clock) are not symmetrical in regard to decision threshold of the comparator. Therefore, in general, the values of the feedback coefficients corresponding to the sequence of the same prior data are not equal (the case where the two are equal is not excluded), that is, h.sub.1h.sub.1, h.sub.2h.sub.2.

(46) It should be noted that, in order to explain the principle, the present embodiment only takes a logic high pulse and a logic low pulse as an example. In actual use, the feedback coefficient can be adjusted according to other characteristics of the laser, which will not be described in detail herein.

(47) 3) Comparing the compensation magnitude AMP.sub.compensation of the current data D.sub.n with a decision threshold Vth to determine the logic value of the current data D.sub.n.

(48) Specifically, when the compensation amplitude AMP.sub.compensation of the current data D.sub.n is less than the decision threshold Vth, determining that the current data D.sub.n is at logic low. When the compensation amplitude AMP.sub.compensation of the current data D.sub.n is greater than the decision threshold Vth, determining that the current data D.sub.n is at logic high.

(49) As shown in FIG. 8, as an implementation example of this embodiment, the principle of the asymmetric decision feedback equalization method of the present disclosure is as follows:

(50) Specifically, the logic value of each prior data is acquired by comparison module and delay, multiplying the logic value of each prior date with corresponding feedback coefficient and then inverting the product to obtain a compensation value. W.sub.1,0h.sub.1 . . . W.sub.i1,0=h.sub.i1, W.sub.j,0=h.sub.j, W.sub.1,1=h.sub.1 . . . W.sub.j1,1=h.sub.j1, W.sub.j,1=h.sub.j.

(51) Specifically, the compensation values are added, and the added value is added to the original signal X.sub.k of the current data D.sub.n, thereby obtaining the compensated signal Z.sub.k of the current data D.sub.n. The compensated signal Z.sub.k of the current data D.sub.n is compared with the decision threshold Vth to obtain the data value d.sub.k, thereby determining the logic value of the current data. The logic value of the current data is used as the prior data of the next data.

(52) Examples before and after compensation are given in the following table to illustrate the effects of the present disclosure:

(53) TABLE-US-00001 D.sub.n.sub.2 D.sub.n1 D.sub.n D.sub.n+1 h.sub.1 h.sub.1 h.sub.2 h.sub.2 AMP.sub.actual AMP.sub.compensation Data 1 1 1 1 0.35 0.5 0.165 0.125 1 0.485 1 1 1 1 1 0.35 0.5 0.165 0.125 0.14 0.485 0 1 1 1 1 0.35 0.5 0.165 0.125 0.03 0.485 1 1 1 1 1 0.35 0.5 0.165 0.125 1.11 0.485 0

(54) (1) Assuming that the data transmitted from the transmitter side is 1111, and the logic value of each data is 1111 (where 1 indicates logic high). For the current data D.sub.n, the actual amplitude AMP.sub.actual after passing the channel is 1. Because the decision threshold is 0, the uncompensated decision result is correct. After compensation, the compensation amplitude AMP.sub.compensation satisfies:
AMP.sub.compensation=AMP.sub.actual+D.sub.n1(h.sub.1)+D.sub.n2(h.sub.2)=11>0.3510.165=0.485,

(55) Then, since the decision threshold Vth is 0, the final decision data is 1, and the compensated decision result is correct.

(56) (2) Assuming that the data transmitted from the transmitter side is 1101, the logic value of each data is 11-11 (where 1 indicates logic high, and 1 indicates logic low). For the current data D.sub.n, the actual amplitude AMP.sub.actual after passing the channel is 0.14. Because the decision threshold Vth is 0, the uncompensated decision result is wrong. After compensation, the compensation amplitude AMP.sub.compensation satisfies:
AMP.sub.compensation=AMP.sub.actual+D.sub.n1(h.sub.1)+D.sub.n2(h.sub.2)=0.1410.510.125=0.485

(57) Then, since the decision threshold Vth is 0, the final decision data is 0, and the compensated decision result is correct.

(58) (3) Assuming that the data transmitted from the transmitter side is 0010, the logic value of each data is 1111 (where 1 indicates logic high, and 1 indicates logic low), and for the current data D.sub.n, the actual amplitude AMP.sub.actual after passing through the channel is 0.03. Since the decision threshold Vth is 0, the uncompensated decision result is wrong. After compensation, the compensation amplitude AMP.sub.compensation satisfies:
AMP.sub.compensation=AMP.sub.actual+D.sub.n1(h.sub.1)+D.sub.n2(h.sub.2)=0.03+10.35+10.165=0.485,

(59) Then, since the decision threshold Vth is 0, the final decision data is 1, and the compensated decision result is correct.

(60) (4) Assuming that the data transmitted from the transmitter side is 0000, the logic value of each data is 1111 (where 1 indicates logic low), and for the current data D.sub.n, the actual amplitude AMP.sub.actual after passing the channel is 1.11. Since the decision threshold Vth is 0, the uncompensated decision result is correct. After compensation, the compensation amplitude AMP.sub.compensation satisfies:
AMP.sub.compensation=AMP.sub.actual+D.sub.n1(h.sub.1)+D.sub.n2(h.sub.2)=1.11+10.5+10.125=0.485,

(61) Then, since the decision threshold Vth is 0, the final decision data is 0, and the compensated decision result is correct.

(62) It can be seen from the above example that the actual amplitude of the signal before compensation is asymmetric, for AMP.sub.actual, the maximum is 1, and the minimum is 1.11. After compensation, the signal amplitude is symmetric, for AMP.sub.compensation, the maximum is 0.485 and the minimum is 0.485.

(63) It can be seen that the error rate of uncompensated data is much higher than the error rate of compensated data. After being compensated by the asymmetric decision feedback equalization method of the present disclosure, the receiver side can recover distorted data with less errors, and the problem of reduced sampling timing margin caused by asymmetric eye diagram can be solved, thus improving the system robustness under different processes, power supply voltages and temperatures, and reducing the jitter of the sampling clock recovered by the clock recovery circuit, thereby reducing the system error rate.

(64) It should be noted that the present embodiment is only used as an example. In actual applications, the impact amplitude of the current data on the data before and after it and the amount of the impacted data are based on the actual laser device and channel characteristics, and are not limited to this embodiment.

(65) It should be noted that the present disclosure is applicable to any pulse amplitude modulation (PAM-N) coding scheme (such as PAM-2, PAM-4, PAM-8, etc.), and is applicable to a receiver framework of any sampling rate, such as full-rate sampling, half-rate sampling and quarter-rate sampling.

Embodiment 2

(66) As shown in FIG. 9 and FIG. 10, the present embodiment provides an asymmetric decision feedback equalization circuit 1 for implementing the asymmetric decision feedback equalization method of the first embodiment. The asymmetric decision feedback equalization circuit 1 includes:

(67) A data input module 11, k compensation modules, a comparison module 13 and k trigger modules 14.

(68) As shown in FIG. 9 and FIG. 10, the data input module 11 receives input data Vin and outputs a differential signal of each data.

(69) Specifically, the data input module 11 includes a first differential input pair transistor N.sub.dif1 and a second differential input pair transistor N.sub.dif2. Gates of the first differential input pair transistor N.sub.dif1 and the second differential input pair transistor N.sub.dif2 are connected to the input data Vin. The sources of the first differential input pair transistor N.sub.dif1 and the second differential input pair transistor N.sub.dif2 are respectively connected to a current source, the sources of the first differential input pair transistor N.sub.dif1 and the second differential input pair transistor N.sub.dif2 are connected through the first resistor R1. The drains of the first differential input pair transistor N.sub.dif1 and the second differential input pair transistor N.sub.dif2 are respectively connected to a load (respectively denoted as RL1 and RL2). The first differential input pair transistor N.sub.dif1 and the second differential input pair transistor N.sub.dif2 output a differential signal of each output.

(70) As shown in FIG. 9 and FIG. 10, each compensation module is respectively connected to an output of the data input module 11, and the current data is compensated based on a logic value of the prior data of the current data D.sub.n and a feedback coefficient corresponding to the prior data, to obtain a compensation magnitude for the current data.

(71) Specifically, in this embodiment, the number of the compensation module is three, which are referred to as a first compensation module 12a, a second compensation module 12b, and a third compensation module 12c, compensation is performed respectively based on three prior data adjacent to the current data D.sub.n. The compensation modules have the same structure and provide different feedback coefficients. In this embodiment, the structure of each compensation module is described by taking the first compensation module 12a as an example. The first compensation module 12a includes a first compensation unit and a second compensation unit. The first compensation unit is connected to an inverted output of the data input module 11, the second compensation unit is connected to a positive output of the data input module 11. The first compensation unit and the second compensation are connected to the third prior data D.sub.n3 of the current data D.sub.n, and the first compensation unit or the second compensation unit is selectively turned on based on a logic value of the third prior data D.sub.n3, so that the feedback coefficient is compensated to the original signal of the current data D.sub.n.

(72) More specifically, as an implementation example of this embodiment, as shown in FIG. 9, the first compensation unit includes a first switch k1, one node of the first switch k1 is connected to the inverted output of the data input module 11, and the other node is connected to the first compensation current I.sub.3,0, the first compensation current I.sub.3,0 is the compensation current corresponding to the feedback coefficient when the third prior data D.sub.n3 is at logic low. The second compensation unit includes a second switch k2, one node of the second switch k2 is connected to the positive output of the data input module 11, and the other node of the second switch k2 is connected to a second compensation current I.sub.3,1, the second compensation current I.sub.3,1 is the compensation current corresponding to the feedback coefficient when the third prior data D.sub.n3 is at logic high.

(73) More specifically, as another implementation manner of this embodiment, as shown in FIG. 10, the first compensation unit includes a first NMOS transistor N1 and a second NMOS transistor N2, and sources of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the first compensation current I.sub.3,0, drain of the first NMOS transistor N1 is connected to an inverted output of the data input module 11, and gate of the first NMOS transistor N1 is connected to an inverted output signal of the third prior data D.sub.n3. Drain of the second NMOS transistor N2 is connected to supply, and gate of the second NMOS transistor N2 is connected to a reference signal VCM. The second compensation unit includes a third NMOS transistor N3 and a fourth NMOS transistor N4. Sources of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to a second compensation current I.sub.3,1. Drain of the third NMOS transistor N3 is connected to supply. Gate of the third NMOS transistor N3 is connected to the reference signal VCM. Drain of the fourth NMOS transistor N4 is connected to a positive output of the data input module 11, gate of the fourth NMOS transistor N4 is connected to a positive output signal of the third prior data D.sub.n3. The structure of each compensation module is the same, and will not be described in detail herein.

(74) As shown in FIG. 9 and FIG. 10, the comparison module 13 is connected to an output of the data input module 11, and compares the compensation amplitude AMP.sub.compensation of the current data with a decision threshold Vth to determine the logic value of the current data D.sub.n.

(75) Specifically, when the compensation amplitude AMP.sub.compensation of the current data D.sub.n is less than the decision threshold Vth, determining that the current data D.sub.n is at logic low, and when the compensation amplitude AMP.sub.compensation of the current data D.sub.n is greater than the decision threshold Vth, determining that the current data D.sub.n is at logic high.

(76) Specifically, the current data D.sub.n after passing through the comparison module 13 is used as the first prior data of the subsequent data.

(77) As shown in FIG. 9 to FIG. 10, each trigger module is in one-to-one correspondence with each compensation module, and is sequentially connected in series to the output end of the comparison module 13 to obtain the logic value of each prior data of the current data D.sub.n.

(78) Specifically, in this embodiment, including the first trigger module 14a and the second trigger module 14b, after successively passing each trigger module, the compensated data is used as the prior data of the subsequent data, and is used for compensation of the subsequent data.

Embodiment 3

(79) As shown in FIG. 11, the present embodiment provides an asymmetric decision feedback equalization circuit 2 for implementing the asymmetric decision feedback equalization method of the embodiment 1, and the asymmetric decision feedback equalization circuit 2 includes: a compensation module 21 and a selection module 22.

(80) As shown in FIG. 11, the compensation module 21 receives the input data Vin, compensates the amplitude of the current data based on the combination of different feedback coefficients corresponding to k prior data sequence, and latches the compensated data as the first prior data of the next current data.

(81) Specifically, the compensation module 21 includes 2.sup.k compensation units, each of the compensation units includes a comparator and a trigger. Each comparator receives the input data Vin and a combination of feedback coefficients corresponding to the sequence of each prior data, thus realizing compensation. In this embodiment, the first compensation unit 211 is taken as an example, and the compensation is performed based on two prior data. As shown in FIG. 11, the first compensation unit 211 includes a first comparator 211a and a first trigger 211b, the first comparator receives the input data Vin, the first prior data is an opposite number W.sub.1,1 of a feedback coefficient corresponding to logic high, and the second prior data is an opposite number W.sub.2,1 of a feedback coefficient corresponding to logic high (in actual use, the opposite number of the feedback coefficient can be replaced with each feedback coefficient, the same logical relationship is realized by the adjustment of the internal symbols), and the current data D.sub.n is compensated accordingly, thus obtaining the compensation signal D.sub.n,1,1 when the adjacent two prior data are at logic high. After passing the first trigger 211b, the compensation signal is used as the first prior data of the subsequent data. The feedback coefficients received by the other compensation units are different combinations of the feedback coefficients of two prior data, which are not described in detail herein.

(82) As shown in FIG. 11, the selection module 22 is connected to an output of the compensated module 21, and determines a feedback coefficient corresponding to each prior data step by step based on logic value of prior data of each output signal of the compensated module 21, thereby determining logic value of a current data after compensation.

(83) Specifically, the selection module 22 includes k level alternative units and a trigger connected to each alternative unit, a number of alternative units at each level is decreasing exponentially by 2, and a feedback coefficient corresponding to a sequence of first prior data of data received by any alternative unit is different. In this embodiment, the selection module 22 includes 2 level alternative units, the first level alternative unit includes a first alternative unit 221 and a second alternative unit 222, the second level alternative unit includes a third alternative unit 225. The feedback coefficient corresponding to the sequence of the first prior data of the input data received by the first alternative unit 221 is the same, and the feedback coefficient corresponding to the sequence of the second prior data is different. The feedback coefficient corresponding to the sequence of the second prior data is determined based on the logic values of the second prior data of the input data received by the first alternative unit 221, and is output by a fifth trigger 223. Similarly, the data selected by the second alternative unit 222 is output by a sixth trigger 224. The third alternative unit 225 is connected to the output of the fifth trigger 223 and the sixth trigger 224. A feedback coefficient corresponding to the sequence of the first prior data is determined based on the logic value of the first prior data of the input data received by the third alternative unit 225, and is output by a seventh trigger 226, to obtain a compensation signal determined by each feedback coefficient.

(84) It should be noted that the implementation mode of the asymmetric decision feedback equalization method in the first embodiment includes but is not limited to the modes of embodiment 2 and embodiment 3, and details are not described herein.

Embodiment 4

(85) As shown in FIG. 12, this embodiment provides a non-linear receiver 3, including:

(86) A continuous time linear equalization (CTLE) circuit 4, an asymmetric decision feedback equalization (ADFE) circuit 5 and a clock data recovery (CDR) circuit 6.

(87) As shown in FIG. 12, the continuous time linear equalization circuit 4 receives an electrical signal converted from an optical signal emitted by a laser device and improves the performance of the electrical signal.

(88) Specifically, the continuous time linear equalization circuit 4 can effectively improve the performance of the eye diagram of the receiver side in a link with a large transmission loss.

(89) As shown in FIG. 12, the asymmetric decision feedback equalization circuit 5 is connected to the output of the continuous time linear equalization circuit 4 to compensate the signal output by the continuous time linear equalization circuit 4.

(90) Specifically, the asymmetric decision feedback equalization circuit 5 compensates the data based on the method of embodiment 1, and the implementation thereof includes, but is not limited to, the second embodiment and the third embodiment.

(91) As shown in FIG. 13, in the compensated signal eye diagram output by the asymmetric decision feedback equalization circuit 5 of the present disclosure, the effective eye height and eye width are increased, and the signal deterministic jitter is reduced, which is advantageous for the sampling judgment and locking of the clock recovery circuit, thus reducing the error of the receiver and improving the robustness of the entire optical to electrical conversion system.

(92) As shown in FIG. 12, the clock data recovery circuit 6 is connected to the output end of the asymmetric decision feedback equalization circuit 5 for recovering the sampling clock and data in the output signal of the asymmetric decision feedback equalization circuit 5.

(93) In summary, the present disclosure provides the nonlinear receiver, the asymmetric decision feedback equalization circuit and method, the method includes: converting the optical signal emitted by the laser device into the electrical signal; obtaining the actual amplitude of current data in the electrical signal, and compensating the current data based on the logic value of k prior data of the current data and the feedback coefficient corresponding to the prior data, to obtain the compensation amplitude of the current data; comparing the compensation amplitude of the current data with the decision threshold to determine the logic value of the current data; the feedback coefficient is the absolute value of the influence amount of the prior data on the amplitude of the current data, and k is a positive integer.

(94) The nonlinear receiver and the asymmetric decision feedback equalization circuit and method of the present disclosure overcome the problem of reduced sampling timing margin due to the asymmetric optical eye diagram by adjusting the feedback coefficient compensated data under different data sequences, thus improving the system robustness under different processes, supply voltages and temperatures, reducing the jitter of the sampling clock recovered by the clock recovery circuit at the same time, thereby reducing the system error rate. Therefore, the present disclosure effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

(95) The above-mentioned embodiments are just used for exemplarily describing the principle and effects of the present disclosure instead of limiting the present disclosure. Those skilled can make modifications or changes to the above-mentioned embodiments without going against the spirit and the range of the present disclosure. Therefore, all equivalent modifications or changes made by those who have common knowledge in the art without departing from the spirit and technical concept disclosed by the present disclosure shall be still covered by the claims of the present disclosure.