STARTING CIRCUIT

Abstract

A starting circuit capable of further reducing an influence of a variation in the threshold voltage of a transistor is proposed. The starting circuit includes an N-type first MOS transistor whose threshold voltage is near 0 V, a resistor interposed between a source terminal of the first MOS transistor and a ground, and a control circuit controlling a gate voltage of the first MOS transistor. An amount of first current transmitted to a device to be driven and starting the device is controlled according to the control of the gate voltage.

Claims

1. A starting circuit comprising: an N-type first MOS transistor whose threshold voltage is near 0 V; a resistor interposed between a source terminal of the first MOS transistor and a ground; and a control circuit controlling a gate voltage of the first MOS transistor, wherein an amount of first current transmitted to a device to be driven and starting the device is controlled according to the control of the gate voltage.

2. The starting circuit according to claim 1, wherein the control circuit controls the gate voltage of the first MOS transistor according to a threshold voltage of the first MOS transistor, and the amount of first current is controlled according to the control of the gate voltage.

3. The starting circuit according to claim 1, wherein the control circuit includes an N-type second MOS transistor in which a gate terminal and a drain terminal are electrically connected, the gate terminal is electrically connected to a gate terminal of the first MOS transistor, and a threshold voltage is near 0 V, and a current mirror circuit configured by P-type MOS transistors, a second current is output from the current mirror circuit to a drain terminal of the first MOS transistor, and a third current obtained by replicating the second current is output from the current mirror circuit to a drain terminal of the second MOS transistor.

4. The starting circuit according to claim 3, wherein the current mirror circuit includes a P-type third MOS transistor and a P-type fourth MOS transistor, in the third MOS transistor, a gate terminal and a drain terminal are electrically connected and the drain terminal is electrically connected to the drain terminal of the first MOS transistor, and in the fourth MOS transistor, a drain terminal is electrically connected to the drain terminal of the second MOS transistor and a source terminal is electrically connected to the ground.

5. The starting circuit according to claim 4, wherein a potential of the drain terminal of the first MOS transistor is controlled according to the supply of a fourth current from the device to the gate terminal of each of the third MOS transistor and the fourth MOS transistor, and the transmission of the first current is controlled according to the potential of the drain terminal.

6. The starting circuit according to claim 5, wherein the current mirror circuit includes a P-type fifth MOS transistor, and according to the potential of the drain terminal of the first MOS transistor, a current obtained by replicating the second current by the fifth MOS transistor is supplied as the first current from a drain terminal of the fifth MOS transistor to the device.

7. The starting circuit according to claim 5, further comprising: a first diode whose anode side is electrically connected to a source terminal of the third MOS transistor and whose cathode side is electrically connected to the drain terminal of the third MOS transistor; and a second diode whose cathode side is electrically connected to the source terminal of the fourth MOS transistor and whose cathode side is electrically connected to the drain terminal of the fourth MOS transistor, wherein in each of the third MOS transistor and the fourth MOS transistor, a back gate terminal and the drain terminal are electrically connected, and extraction of the first current to the side of the source terminal of each of the third MOS transistor and the fourth MOS transistor is controlled according to the potential of the drain terminal of the first MOS transistor.

8. The starting circuit according to claim 5, wherein the source terminal of the fourth MOS transistor is electrically connected to the ground via an N-type N-type sixth MOS transistor whose threshold voltage is near 0 V.

9. The starting circuit according to claim 5, wherein the device is a current source circuit.

10. The starting circuit according to claim 9, wherein the device is a self-bias type current source circuit, and a part of a current flowing through the current source circuit is supplied to the gate terminal of each of the third MOS transistor and the fourth MOS transistor as the fourth current.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is an explanatory diagram for explaining an example of a schematic configuration of a starting circuit according to a comparative example.

[0011] FIG. 2 is an explanatory diagram for explaining an example of a circuit configuration of a starting circuit according to a comparative example.

[0012] FIG. 3 is an explanatory diagram for explaining an outline of a relation between a source voltage and a drain current of a Native-NMOS whose gate is grounded.

[0013] FIG. 4 is an explanatory diagram for explaining an outline of a relation between a resistor to which a voltage is applied and a current flowing through the resistor.

[0014] FIG. 5 is an explanatory diagram for explaining characteristics of a starting circuit according to a comparative example.

[0015] FIG. 6 is an explanatory diagram for explaining an outline of an operation principle of a starting circuit according to an embodiment of the present disclosure.

[0016] FIG. 7 is an explanatory diagram for explaining a first configuration example of the starting circuit according to the embodiment.

[0017] FIG. 8 is a timing chart for explaining an operation of the starting circuit according to the first configuration example.

[0018] FIG. 9 is an explanatory diagram for explaining characteristics of the starting circuit according to the first configuration example.

[0019] FIG. 10 is an explanatory diagram for explaining characteristics of the starting circuit according to the first configuration example.

[0020] FIG. 11 is an explanatory diagram for explaining a second configuration example of the starting circuit according to the embodiment.

[0021] FIG. 12 is an explanatory diagram for explaining a third configuration example of the starting circuit according to the embodiment.

DESCRIPTION OF EMBODIMENTS

[0022] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that same reference numerals are given to components having substantially a same functional configuration, and redundant description will be omitted in the present specification and the drawings.

[0023] Note that the description will be given in the following order.

[0024] 1. Outline of starting circuit

[0025] 2. Technical problems

[0026] 3. Technical Features

[0027] 3.1. Operation principle

[0028] 3.2. First configuration example

[0029] 3.3. Second configuration example

[0030] 3.4. Third configuration example

[0031] 3.5. Supplement

[0032] 4. Conclusion

1. Outline of Starting Circuit

[0033] First, an outline of a starting circuit will be described with an example. As described above, in recent years, with the diversification of electronic apparatuses, electronic apparatuses with low power consumption have also been proposed. Among element circuits configuring the electronic apparatuses with the low power consumption, there are also element circuits with nW power consumption. A starting circuit is exemplified as one of the element circuits. As the starting circuit, there are various types of starting circuits according to the required specifications. In recent years, particularly, a starting circuit of a type using an N-type MOS transistor whose threshold voltage is adjusted to be near 0 V, which is called a Native-NMOS, has also been proposed.

[0034] As described above, since the threshold voltage is near 0 V, the Native-NMOS has a characteristic that a channel leak current flows to some extent even in a state in which a gate terminal is connected to a ground (GND). In other words, the Native-NMOS has a characteristic that a source and a drain are held in a conductive state with a voltage not applied to the gate terminal. The starting circuit of the type using the Native-NMOS has attracted attention because it can achieve both area saving and low current consumption as compared with other types of starting circuits, by using the characteristics of the Native-NMOS as described above.

[0035] Here, as a comparative example, an example of the starting circuit of the type using the Native-NMOS will be described. For example, FIG. 1 is an explanatory diagram for explaining an example of a schematic configuration of the starting circuit according to the comparative example, and illustrates an example of a configuration of a starting circuit 190 in which a current source circuit 200 is a drive target.

[0036] As illustrated in FIG. 1, the starting circuit 190 includes a transistor NM.sub.10 configured as the Native-NMOS, a resistor R.sub.STUP, and a starting current generation circuit 191. In the transistor NM.sub.10, a gate terminal is electrically connected to the ground (GND) and a source terminal is electrically connected to the ground (GND) via the resistor R.sub.STUP. Further, the starting current generation circuit 191 is connected to the side of a drain terminal of the transistor NM.sub.10. In FIG. 1, reference symbol I.sub.D schematically indicates a drain current of the transistor NM.sub.10. Further, reference symbol V.sub.s schematically indicates a potential of the source terminal of the transistor NM.sub.10. With the above configuration, a starting current (starting signal) generated in the starting current generation circuit 191 is transmitted to the current source circuit 200, so that the current source circuit 200 starts.

[0037] Specifically, whether or not the starting current generated in the starting current generation circuit 191 is transmitted to the current source circuit 200 is controlled according to either a conductive state in which the source and the drain of the transistor NM.sub.10 are conductive or a non-conductive state in which the source and the drain are non-conductive. The transistor NM.sub.10 enters the conductive state, so that the drain current I.sub.D flows through the starting current generation circuit 191, and the starting current is generated by the starting current generation circuit 191. The starting current generated by the starting current generation circuit 191 is transmitted to the current source circuit 200, so that the current source circuit 200 starts.

[0038] Here, an example of a circuit configuration of the starting circuit according to the comparative example will be described. For example, FIG. 2 is an explanatory diagram for explaining an example of a circuit configuration of the starting circuit according to the comparative example, and illustrates an example of a circuit configuration of the starting circuit 190 in a case where the current source circuit 200 illustrated in FIG. 1 is configured as a so-called self-bias type current source circuit.

[0039] As described above, the current source circuit 200 illustrated in FIG. 2 is configured as the self-bias type power supply circuit. Specifically, the current source circuit 200 includes transistors M.sub.101 and M.sub.103 configured as N-type MOS transistors and transistors M.sub.105, M.sub.107, and M.sub.109 configured as P-type MOS transistors.

[0040] The transistors M.sub.101 and M.sub.103 configure a current source circuit using a subthreshold characteristic of a MOSFET. Specifically, gate terminals of the transistors M.sub.101 and M.sub.103 are electrically connected to each other. A gate and a drain of the transistor M.sub.103 are electrically connected. A source terminal of the transistor M.sub.101 is electrically connected to the ground (GND) via a resistor R.sub.0. Further, a source terminal of the transistor M.sub.103 is electrically connected to the ground (GND). As a result, a current having a value obtained by dividing a gate-source voltage difference between the transistors M.sub.101 and M.sub.103 by a resistance value of the resistor R.sub.0 is generated as a drain current of M.sub.101.

[0041] Further, the transistors M.sub.105, M.sub.107, and M.sub.109 configure a current mirror circuit. Specifically, gate terminals of the transistors M.sub.105, M.sub.107, and M.sub.109 are electrically connected to each other. A gate and a drain of the transistor M.sub.105 are electrically connected. Source terminals of the transistors M.sub.105, M.sub.107, and M.sub.109 are electrically connected to a power supply voltage M.sub.101.

[0042] Further, the drain terminal of the transistor M.sub.101 and the drain terminal of the transistor M.sub.105 are electrically connected. Further, the drain terminal of the transistor M.sub.103 and the drain terminal of the transistor M.sub.107 are electrically connected.

[0043] With the above configuration, for example, a starting current I.sub.STUP generated by the starting circuit 190 is supplied to the side of the drain terminal of the transistor M.sub.103, and the current source circuit 200 starts. At this time, the starting current I.sub.STUP is supplied to the gate terminals of the transistors M.sub.101 and M.sub.103 configuring the current source circuit.

[0044] Next, a circuit configuration of the starting circuit 190 will be described. The starting circuit 190 includes a transistor NM.sub.10, a resistor R.sub.STUP, and transistors M.sub.191 and M.sub.193. The transistor NM.sub.10 corresponds to the transistor NM.sub.10 illustrated in FIG. 1. That is, the transistor NM.sub.10 is configured as, for example, a Native-NMOS, and a gate terminal thereof is electrically connected to the ground (GND) and a source terminal thereof is electrically connected to the ground (GND) via the resistor R.sub.STUP.

[0045] The transistors M.sub.191 and M.sub.193 configure a current mirror circuit. In a starting circuit 130, a current obtained by replicating a drain current of the transistor NM.sub.10 by the current mirror circuit is supplied to the current source circuit 200 as the starting current I.sub.STUP.

[0046] Specifically, the transistors M.sub.191 and M.sub.193 are configured as P-type MOS transistors and gate terminals thereof are electrically connected to each other. The gate and the drain of the transistor M.sub.191 are electrically connected. The source terminals of the transistors M.sub.191 and M.sub.193 are electrically connected to the power supply voltage VDD. Further, the drain terminal of the transistor M.sub.191 and the drain terminal of the transistor NM.sub.10 are electrically connected.

[0047] Further, the side of the drain terminal of the transistor M.sub.109 is electrically connected to the gate terminals of the transistors M.sub.191 and M.sub.193 configuring the current mirror circuit. That is, the drain terminal of the transistor M.sub.109 and the drain terminal of the transistor NM.sub.10 are electrically connected. Further, the drain terminal of the transistor M.sub.193 and the drain terminal of the transistor M.sub.103 (that is, the drain terminal of the transistor M.sub.107) are electrically connected. That is, the drain terminal of the transistor M.sub.193 and the gate terminals of the transistors M.sub.101 and M.sub.103 configuring the current mirror circuit are electrically connected.

[0048] With the above configuration, when the power supply voltage VDD is applied and the starting circuit 190 is turned on, a drain current flows through the transistor NM.sub.10 in a conductive state, and a current obtained by replicating the drain current by the current mirror circuit of the starting circuit 190 is supplied to the current source circuit 200 as the starting current I.sub.STUP.

[0049] The starting current I.sub.STUP from the starting circuit 190 is supplied to the gate terminal (that is, a node N.sub.VGN) of each of the transistors M.sub.101 and M.sub.103 configuring the current source circuit in the current source circuit 200, and the transistors M.sub.101 and M.sub.103 transition to the conductive state. As a result, the gate terminal (that is, a node N.sub.VGP) of each of the transistors M.sub.105, M.sub.107, and M.sub.109 configuring the current mirror circuit is electrically connected to the ground (GND) via the transistor M.sub.101 and the resistor R.sub.0, so that the transistors M.sub.105, M.sub.107, and M.sub.109 configuring the current mirror circuit transition to the conductive state. As described above, with the supply of the starting current I.sub.STUP from the starting circuit 190, the current source circuit configured by the N-type MOS transistors M.sub.101 and M.sub.103 first starts and the current mirror circuit configured by the P-type MOS transistors M.sub.105, M.sub.107, and M.sub.109 then starts, so that starting of the current source circuit 200 is completed.

[0050] Further, when the current source circuit 200 starts, a part of the current output from the current source circuit 200 (in other words, an output signal) is supplied as a bias current I.sub.BIAS to the gate terminal of each of the transistors M.sub.191 and M.sub.193 configuring the current mirror circuit. As a result, the potential of the gate terminal of each of the transistors M.sub.191 and M.sub.193 increase, so that the potential of the drain terminal of the transistor NM.sub.10 electrically connected to the gate terminal also increases. At this time, a current value of the bias current I.sub.BIAS set by an aspect ratio (W/L ratio) of the transistors M.sub.105 and M.sub.109 is set to a value sufficiently larger than a current value of the drain current of the transistor NM.sub.10 to be a value obtained by dividing a gate-source voltage V.sub.gs of the transistor NM.sub.10 by the resistor R.sub.STUP, so that the drain voltage of the transistor NM.sub.10 (that is, the gate voltage of each of the transistors M.sub.191 and M.sub.193) can be increased to the power supply voltage VDD.

[0051] Then, in each of the transistors M.sub.191 and M.sub.193, when a gate-source voltage is sufficiently lower than a threshold voltage, each of the transistors M.sub.191 and M.sub.193 transitions to a non-conductive state. As described above, the transistor M.sub.193 transitions to the non-conductive state, so that the supply of the starting current I.sub.STUP from the starting circuit 190 to the current source circuit 200 is interrupted. Further, the current value of the bias current I.sub.BIAS supplied from the current source circuit 200 to the side of the drain terminal of the transistor NM.sub.10 at this time is limited to a value substantially equal to the current value of the drain current of the transistor NM.sub.10, which is a minimum current required to maintain the starting circuit 190 in an off state.

[0052] The outline of the starting circuit has been described above with an example with reference to FIGS. 1 and 2.

2. Technical Problems

[0053] Next, technical problems of the starting circuit according to the comparative example described above will be described.

[0054] Like the starting circuit 190 illustrated in FIG. 1, in the starting circuit of the type using the N-type MOS transistor (that is, the Native-NMOS) whose threshold voltage is near 0 V, the drain current may change according to a variation or a change in the threshold voltage of the MOS transistor. As a specific example, in the starting circuit 190 illustrated in FIG. 1, the drain current I.sub.D of the transistor NM.sub.10 is given by a formula of a drain current in a subthreshold region of the MOSFET, which is shown as (Formula 1) below.

[00001]$\begin{array}{cc}{I}_D=I_0.Math.\exp \left(\frac{-V_s-V_{\mathrm{th}}}{\mathrm{nkT}/q}\right)& \left(\mathrm{Formula}.Math..Math.1\right)\end{array}$

[0055] In the above (Formula 1), V.sub.s indicates a potential of the source terminal of the transistor NM.sub.10 whose gate terminal is connected to GND, which is illustrated in FIG. 1. Further, V.sub.th indicates a threshold voltage, n indicates a slope factor, k indicates a Boltzmann constant, T indicates a temperature, and q indicates elementary charge. Further, a coefficient I.sub.0 is represented by a calculation formula shown as (Formula 2) below.

[00002]$\begin{array}{cc}{I}_0=.Math..Math.C_{\mathrm{ox}}.Math.\frac{W}{L}.Math.\left(-1\right).Math.{\left(\frac{\mathrm{kT}}{q}\right)}^2& \left(\mathrm{Formula}.Math..Math.2\right)\end{array}$

[0056] In the above (Formula 2), indicates mobility, Cox indicates capacitance per unit area of a gate oxide film, W indicates a channel width, L indicates a channel length, and indicates a constant derived from a device structure due to the gate oxide film capacitance and the depletion layer capacitance.

[0057] Further, the drain current I.sub.D is represented by a relational expression shown as (Formula 3) below in order to generate the source voltage V.sub.s in the resistor R.sub.STUP.

I.sub.D=V.sub.sR.sub.STUP(Formula 3)

[0058] From the above, the drain current I.sub.D of the transistor NM.sub.10 is a value solved for I.sub.D by combining the above formulas (1) and (3). It can be seen from (Formula 1) that the drain current I.sub.D includes the threshold voltage V.sub.th of the transistor NM.sub.10 as an argument of an exponential function and is greatly affected by the variation or the change in the threshold voltage V.sub.th.

[0059] Here, the influence of the variation or the change in the threshold voltage V.sub.th will be described numerically. For example, FIG. 3 is an explanatory diagram for explaining an outline of a relation between a source voltage and a drain current of a Native-NMOS whose gate is grounded. A transistor NM.sub.10 illustrated in FIG. 3 corresponds to the transistor NM.sub.10 applied to the starting circuit 190 illustrated in FIG. 1. The characteristic of the drain current represented by the above (Formula 1) can be confirmed by sweeping the source voltage V.sub.s and monitoring the drain current I.sub.D, in a circuit illustrated in FIG. 3.

[0060] Further, FIG. 4 is an explanatory diagram for explaining an outline of a relation between a resistor to which a voltage is applied and a current flowing through the resistor. In FIG. 4, when the current flowing through the resistor is set to I.sub.R, a characteristic of the current flowing through the resistor represented by (Formula 3) described above can be confirmed by sweeping the applied voltage V.sub.s and monitoring the current I.sub.R, in a circuit illustrated in FIG. 4.

[0061] For example, FIG. 5 is an explanatory diagram for explaining characteristics of a starting circuit according to a comparative example. Specifically, FIG. 5 shows an example of simulation results of the drain current I.sub.D of the Native-NMOS based on the circuit illustrated in FIG. 3 and the current I.sub.R flowing through the resistor based on the circuit illustrated in FIG. 4. In FIG. 5, a horizontal axis represents a voltage value of each of the source voltage V.sub.s illustrated in FIG. 3 and the applied voltage V.sub.s illustrated in FIG. 4. Further, a vertical axis represents a current value of each of the drain current I.sub.D illustrated in FIG. 3 and the current I.sub.R illustrated in FIG. 4. In FIG. 5, a graph shown as reference symbol I.sub.D shows an example of the simulation result of the drain current I.sub.D illustrated in FIG. 3. Further, a graph shown as reference symbol I.sub.R shows an example of the simulation result of the current I.sub.R illustrated in FIG. 4. In the example illustrated in FIG. 5, for each of the drain current I.sub.D illustrated in FIG. 3 and the current I.sub.R illustrated in FIG. 4, simulation results of a maximum value, a representative value, and a minimum value in which a process variation of the threshold voltage V.sub.TH of the transistor NM.sub.10 or a temperature change of the threshold voltage V.sub.TH is considered are shown.

[0062] As a result of combining the above (Formula 1) and (Formula 3), that is, in FIG. 5, an intersection of the graph of the drain current I.sub.D and the graph of the current I.sub.R corresponding to the same condition becomes the drain current I.sub.D of the transistor NM.sub.10 in the power supply circuit 190 according to the comparative example illustrated in FIG. 1. As illustrated in FIG. 5, it can be seen that the drain current I.sub.D of the transistor NM.sub.10 is less affected by the variation in the resistance or the temperature change, but is greatly affected by the variation in the threshold voltage V.sub.TH of the transistor NM.sub.10. More specifically, in the case of the example illustrated in FIG. 5, the drain current I.sub.D of the transistor NM.sub.10 changes from about 15 pA to about 2500 pA by two digits or more.

[0063] As the drain current I.sub.D of the transistor NM.sub.10 changes, the starting current determined according to the drain current I.sub.D also changes, and the change in the starting current can affect a starting time of a device to be driven (for example, the current source circuit 200 illustrated in FIG. 1). For this reason, for example, when there is a constraint on the starting time of the device to be driven, it is necessary to design a starting circuit so that a maximum value of the starting time that can be assumed is less than a design target. In other words, it is necessary to design the starting circuit so that a minimum value of the drain current I.sub.D of the transistor NM.sub.10 according to the starting time that can be assumed becomes larger than the design target. On the other hand, an increase in the drain current I.sub.D leads to an increase in current consumption. From the background described above, it is required to introduce technology capable of further suppressing the change in the starting current (in particular, the influence of the variation in the threshold voltage of the transistor NM.sub.10) in the starting circuit described above.

[0064] In view of the above situation, the present disclosure proposes an example of a starting circuit capable of further reducing the influence of the variation in the threshold voltage of the transistor.

3. Technical Features

[0065] Technical features of a starting circuit according to an embodiment of the present disclosure will be described below.

3.1. Operation Principle

[0066] First, a basic operation principle of the starting circuit according to the embodiment of the present disclosure will be described. For example, FIG. 6 is an explanatory diagram for explaining an outline of the operation principle of the starting circuit according to the embodiment of the present disclosure, and illustrates an example of a configuration in which the starting circuit is abstracted as functional blocks. In the following description, features of a starting circuit 100 according to the embodiment of the present disclosure will be described by focusing on a case where a current source circuit 200 is set to a driving target, similarly to the example described with reference to FIG. 1. That is, since the current source circuit 200 illustrated in FIG. 6 is substantially the same as the current source circuit 200 illustrated in FIG. 1, detailed description thereof will be omitted.

[0067] As illustrated in FIG. 6, the starting circuit 100 includes a transistor NM.sub.11, a resistor R.sub.STUP, a starting current generation circuit 101, and a gate voltage control circuit 103. Since the starting current generation circuit 101 corresponds to the starting current generation circuit 191 in the example described with reference to FIG. 1, detailed description thereof will be omitted.

[0068] The transistor NM.sub.11 is an N-type MOS transistor whose threshold voltage is adjusted to be near 0 V. In other words, the transistor NM.sub.11 has a characteristic that a source and a drain are held in a conductive state with a voltage not applied to a gate terminal. As a specific example, the transistor NM.sub.11 can be configured as a Native-NMOS. The source terminal of the transistor NM.sub.11 is electrically connected to the ground (GND) via the resistor R.sub.STUP. Further, the gate voltage control circuit 103 is electrically connected to the gate terminal of the transistor NM.sub.11, and a gate voltage applied to the transistor NM.sub.11 is controlled by the gate voltage control circuit 103. Further, the starting current generation circuit 101 is connected to the side of the drain terminal of the transistor NM.sub.11. Note that the transistor NM.sub.11 corresponds to an example of a first MOS transistor.

[0069] The gate voltage control circuit 103 controls the gate voltage applied to the transistor NM.sub.11 (in other words, the potential of the gate terminal of the transistor NM.sub.11). Specifically, the gate voltage control circuit 103 controls the gate voltage applied to the transistor NM.sub.11, according to a threshold voltage V.sub.TH of the transistor NM.sub.11. As a more specific example, the gate voltage control circuit 103 performs correction so that the generated drain current I.sub.D becomes larger, when the threshold voltage V.sub.TH of the transistor NM.sub.11 is a predetermined threshold or more (for example, 0 V or more). By the control described above, for example, it is possible to further reduce the influence of the variation in the threshold voltage V.sub.TH of the transistor NM.sub.11 or the change in the threshold voltage V.sub.TH due to the temperature change and the like. Details of the above control will be described later together with an example of the circuit configuration of the starting circuit 100.

[0070] The basic operation principle of the starting circuit according to the embodiment of the present disclosure has been described above with reference to FIG. 6.

3.2. First Configuration Example

[0071] Subsequently, a first configuration example of the starting circuit according to the embodiment of the present disclosure will be described.

[0072] (Circuit Configuration)

[0073] First, an example of a circuit configuration of the starting circuit according to the first configuration example will be described with reference to FIG. 7. FIG. 7 is an explanatory diagram for explaining the first configuration example of the starting circuit according to the embodiment of the present disclosure, and illustrates an example of the circuit configuration of the starting circuit illustrated in FIG. 6. Since the circuit configuration of a current source circuit 200 illustrated in FIG. 7 is substantially the same as the circuit configuration of the current source circuit 200 described with reference to FIG. 2, detailed description thereof will be omitted. Further, a starting circuit 110 illustrated in FIG. 7 corresponds to the example of the starting circuit 100 in the example illustrated in FIG. 6.

[0074] As illustrated in FIG. 7, the starting circuit 110 includes transistors NM.sub.111 and NM.sub.113, a resistor R.sub.STUP, and transistors M.sub.111, M.sub.113, and Min. Each of the transistors NM.sub.111 and NM.sub.113 is configured as an N-type MOS transistor whose threshold voltage is adjusted to be near 0 V. In other words, each of the transistors NM.sub.111 and NM.sub.113 has a characteristic that a source and a drain are held in a conductive state with a voltage not applied to a gate terminal. As a specific example, each of the transistors NM.sub.111 and NM.sub.113 can be configured as a Native-NMOS. Note that the transistor NM.sub.111 and the resistor R.sub.STUP correspond to the transistor NM.sub.111 and the resistor R.sub.STUP illustrated in FIG. 6. That is, the source terminal of the transistor NM.sub.111 is electrically connected to the ground (GND) via the resistor R.sub.STUP. Further, the transistors M.sub.111, M.sub.113, and M.sub.115 and the transistor NM.sub.113 function as the starting current generation circuit 101 and the gate voltage control circuit 103 illustrated in FIG. 6. More specifically, particularly, the transistor NM.sub.113 contributes to the role of the gate voltage control circuit 103.

[0075] The gate terminal and the drain terminal of the transistor NM.sub.113 are electrically connected (that is, diode-connected), and the gate terminal thereof is electrically connected to the gate terminal of the transistor NM.sub.111. Further, the source terminal of the transistor NM.sub.113 is electrically connected to the ground (GND). Note that the transistor NM.sub.113 corresponds to an example of a second MOS transistor.

[0076] The transistors M.sub.111, M.sub.113, and M.sub.115 configure a current mirror circuit. Specifically, the transistors M.sub.111, M.sub.113, and M.sub.115 are configured as P-type MOS transistors and gate terminals thereof are electrically connected to each other. The gate terminal and the drain terminal of the transistor M.sub.111 are electrically connected (that is, diode-connected). The source terminals of the transistors M.sub.111, M.sub.113, and M.sub.115 are electrically connected to the power supply voltage VDD. With the above configuration, the drain terminal of the transistor M.sub.111 and the drain terminal of the transistor NM.sub.111 are electrically connected. Further, the drain terminal of the transistor M.sub.113 and the drain terminal of the transistor NM.sub.113 are electrically connected.

[0077] Further, the side of the drain terminal of the transistor M.sub.109 is electrically connected to the gate terminal of each of the transistors M.sub.111, M.sub.113, and M.sub.115 configuring the current mirror circuit. That is, the drain terminal of the transistor M.sub.109 and the drain terminal of the transistor NM.sub.111 are electrically connected. Further, the drain terminal of the transistor M.sub.115 and the drain terminal of the transistor M.sub.103 (that is, the drain terminal of the transistor M.sub.107) are electrically connected. That is, the drain terminal of the transistor M.sub.115 and the gate terminal of each of the transistors M.sub.101 and M.sub.103 configuring the current mirror circuit in the current source circuit 200 are electrically connected.

[0078] Note that, in the following description, for convenience, a terminal indicated by reference symbol IN in FIG. 7, that is, the drain terminal of the transistor M.sub.111 is also referred to as an input terminal IN of the current mirror circuit configured by the transistors M.sub.111, M.sub.113, and M.sub.115. Further, in FIG. 7, terminals indicated by reference symbols OUT1 and OUT2, that is, the drain terminal of the transistor Mus and the drain terminal of the transistor M.sub.113 are also referred to as a first output terminal OUT1 and a second output terminal OUT2 of the current mirror circuit, respectively. In addition, in the starting circuit 110 according to the first configuration example, the transistors M.sub.111, M.sub.113, and M.sub.115 correspond to examples of a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor, respectively.

[0079] With the above configuration, when the power supply voltage VDD is applied and the starting circuit 110 is turned on, a current output from the input terminal IN of the current mirror circuit flows through the transistor NM.sub.111 in a conductive state. As a result, a current obtained by replicating the drain current of the transistor NM.sub.111 (that is, the current output from the input terminal IN) by the current mirror circuit is supplied as a starting current I.sub.STUP from the first output terminal OUT1 of the current mirror circuit to the current source circuit 200. That is, the current source circuit 200 starts in response to the supply of the starting current I.sub.STUP. Note that the drain current of the transistor NM.sub.111 corresponds to an example of a second current, and the starting current I.sub.STUP corresponds to an example of a first current.

[0080] At this time, a current obtained by replicating the drain current of the transistor NM.sub.111 by the current mirror circuit flows through the transistor NM.sub.113 in the conductive state from the second output terminal OUT2 of the current mirror circuit. That is, the current output from the second output terminal OUT2 is supplied to the gate terminal of each of the transistors NM.sub.111 and NM.sub.113 according to the threshold voltage V.sub.TH of the transistor NM.sub.113, and the drain current flowing through the transistor NM.sub.111 is controlled. Details of the above control will be described later. Further, the current flowing through the transistor NM.sub.113, which is the replication of the drain current of the transistor NM.sub.111, corresponds to an example of a third current.

[0081] Next, when the current source circuit 200 starts, a part of the current (in other words, the output signal) output from the current source circuit 200 is supplied as the bias current I.sub.BIAS to the gate terminal of each of the transistors M.sub.111, M.sub.113, and M.sub.115 configuring the current mirror circuit. As a result, the potential of the gate terminal of each of the transistors M.sub.111, M.sub.113, and M.sub.115 increases, so that the potential of the drain terminal of the transistor NM.sub.111 electrically connected to the gate terminal also increases. At this time, a current value of the bias current I.sub.BIAS set by an aspect ratio (W/L ratio) of the transistors M.sub.105 and M.sub.109 is set to a value sufficiently larger than a current value of the drain current of the transistor NM.sub.111 to be a value obtained by dividing a gate-source voltage V.sub.gs of the transistor NM.sub.111 by the resistor R.sub.STUP, so that the drain voltage of the transistor NM.sub.111 (that is, the gate voltage of each of the transistors M.sub.111, M.sub.113, and M.sub.115) can be increased to the power supply voltage VDD. Note that the bias current I.sub.BIAS corresponds to an example of a fourth current.

[0082] Then, in each of the transistors M.sub.111, M.sub.113, and M.sub.115, when a gate-source voltage is sufficiently lower than a threshold voltage, each of M.sub.111, M.sub.113, and M.sub.115 transitions to a non-conductive state. As described above, the transistor M.sub.115 transitions to the non-conductive state, so that the supply of the starting current I.sub.STUP from the starting circuit 110 to the current source circuit 200 is interrupted. Further, the current value of the bias current I.sub.BIAS supplied from the current source circuit 200 to the side of the drain terminal of the transistor NM.sub.111 at this time is limited to a value substantially equal to the current value of the drain current of the transistor NM.sub.111, which is a minimum current required to maintain the starting circuit 110 in an off state.

[0083] (Operation)

[0084] Here, an operation of the starting circuit 110 illustrated in FIG. 7, that is, an operation related to the starting of the current source circuit 200 will be described in more detail with reference to FIG. 8. FIG. 8 is a timing chart for explaining an operation of the starting circuit 110 according to the first configuration example. A horizontal axis of FIG. 8 indicates a time. VDD indicates a voltage value of the power supply voltage VDD illustrated in FIG. 7. VGP indicates the potential of the node N.sub.VGP in FIG. 7, that is, the potential of the gate terminal of each of the transistors M.sub.105, M.sub.107, and M.sub.109 configuring the current mirror circuit in the current source circuit 200. VGN indicates the potential of the node N.sub.VGN in FIG. 7, that is, the potential of the gate terminal of each of the transistors M.sub.101 and M.sub.103 configuring the current mirror circuit in the current source circuit 200. I.sub.STUP indicates a current value of the starting current I.sub.STUP illustrated in FIG. 7. I.sub.BIAs indicates a current value of the bias current I.sub.BIAS illustrated in FIG. 7. VGP0 indicates the potential of the node N.sub.VGP0 in FIG. 7, that is, the potential of the gate terminal of each of the transistors M.sub.111, M.sub.113, and M.sub.115 configuring the current mirror circuit in the starting circuit 110. VGN0 indicates the potential of the node N.sub.VGN0 in FIG. 7, that is, the potential of the gate terminal of each of the transistors NM.sub.111 and NM.sub.113.

[0085] In the example illustrated in FIG. 8, the power supply voltage VDD is applied at the timing t11, and the voltage value of the power supply voltage VDD increases in a period from the timing t11 to the timing t13.

[0086] When the power supply voltage VDD is applied, the starting circuit 110 is turned on, and the drain current flows from the input terminal IN to the transistor NM.sub.111 in a conductive state. As a result, a current obtained by replicating the drain current by the current mirror circuit is supplied as the starting current I.sub.STUP, from the first output terminal OUT1 to the current source circuit 200. Further, the current obtained by replicating the drain current by the current mirror circuit flows through the side of the drain terminal of the transistor NM.sub.113 from the second output terminal OUT2. As described above, the gate terminal and the drain terminal of the transistor NM.sub.113 are electrically connected, and the current flowing through the side of the drain terminal of the transistor NM.sub.113 is supplied to the node N.sub.VGN0 (that is, the gate terminal of each of the transistors NM.sub.111 and NM.sub.113). With the above configuration, the gate voltage of each of the transistors NM.sub.111 and NM.sub.113 (that is, the potential of the node N.sub.VGN0) is controlled to a voltage according to the threshold voltage of the transistor NM.sub.113.

[0087] Specifically, when the threshold voltage of the transistor NM.sub.111 is 0 V or less, the current value of the starting current I.sub.STUP is determined by the gate-source voltage of the transistor NM.sub.111 when the gate voltage of the transistor NM.sub.111 is set to 0 V. At this time, the threshold voltage is 0 V or less. For this reason, even if a current obtained by replicating the drain current of the transistor NM.sub.111 flows through the transistor NM.sub.113, the gate voltage does not become 0 V or more.

[0088] On the other hand, in a case where the threshold voltage is higher than 0 V, if a current obtained by replicating the drain current of the transistor NM.sub.111 flows through the transistor NM.sub.113, the transistor NM.sub.113 is diode-connected, so that the gate voltage of each of the transistors NM.sub.111 and NM.sub.113 becomes higher than 0 V. By the above effect, the current value of the drain current of the transistor NM.sub.111 becomes larger than that when the gate voltage of the transistor NM.sub.111 is 0 V.

[0089] As a specific example, in the example illustrated in FIG. 8, as the voltage value of the power supply voltage VDD increases, a current value of each of the drain current of the transistor NM.sub.111 and a current obtained by replicating the drain current (that is, the starting current I.sub.STUP and the drain current of the transistor NM.sub.113) increases.

[0090] The starting current I.sub.STUP from the starting circuit 110 is supplied to the gate terminal (that is, the node N.sub.VGN) of each of the transistors M.sub.101 and M.sub.103 configuring the current mirror circuit in the current source circuit 200, and the transistors M.sub.101 and M.sub.103 transition to the conductive state. As a result, the gate terminal (that is, the node N.sub.VGP) of each of the transistors M.sub.105, M.sub.107, and M.sub.109 configuring the current mirror circuit in the current source circuit 200 is electrically connected to the ground (GND) via the transistor M.sub.101 and the resistor R.sub.0, and the potential of the node N.sub.VGP decreases in accordance with the increase in the potential VGN of the node N.sub.VGN. Then, as the potential VGP of the node N.sub.VGP decreases, at the timing t17, the transistors M.sub.105, M.sub.107, and M.sub.109 configuring the current mirror circuit transition to the conductive state, and the increase in the potential VGN and the decrease in the potential VGP are stopped. As described above, the starting of the current source circuit 200 is completed, and a signal (drain current) flows between the source and the drain of each of the transistors M.sub.101, M.sub.103, M.sub.105, M.sub.107, and M.sub.109 configuring the current source circuit 200.

[0091] Further, as the power supply voltage VDD is applied, a current flows through the resistor R.sub.STUP via the transistors M.sub.111 and NM.sub.111. At this time, since the gate and the drain of the transistor M.sub.111 are electrically connected, the potential VGP0 of the node N.sub.VGP0 (that is, the gate voltage of each of the transistors M.sub.111 and M.sub.113) also increases as the power supply voltage VDD increases. As a specific example, in the example illustrated in FIG. 8, the potential VGP0 of the node N.sub.VGP0 increases during the period of the timings t11 to t13.

[0092] Further, a current obtained by replicating the current flowing through the transistor M.sub.111 (that is, the current output from the input terminal IN) by the current mirror circuit flows through the side of the drain terminal of the transistor NM.sub.113 from the second output terminal OUT. At this time, as described above, when the threshold voltage of the transistor NM.sub.111 is higher than 0 V, the transistor NM.sub.113 is diode-connected, so that the potential VGN0 of the node N.sub.VGN0 (that is, the gate voltage of each of the transistors NM.sub.111 and NM.sub.113) becomes higher than 0 V. As a specific example, in the example illustrated in FIG. 8, the potential VGN0 of the node N.sub.VGN0 increases during the period of the timings t11 to t15. That is, the current value of the drain current of the transistor NM.sub.111 also increases as the gate voltage of the transistor NM.sub.111 increases. On the other hand, the increase in the potential of the power supply voltage VDD is stopped at the timing t13, and in the period of the timings t13 to t15, the potential VGP0 of the node N.sub.VGP0 decreases as the potential VGN0 of the node N.sub.VGN0 increases (that is, the current value of the drain current of the transistor NM.sub.111 increases).

[0093] Further, when the starting of the current source circuit 200 is completed at the timing t17, the current (signal) transmitted between the source and the drain of the transistor M.sub.109 is supplied as the bias current I.sub.BIAS to the gate terminal (that is, the node N.sub.VGP0) of each of the transistors M.sub.111, M.sub.113, and M.sub.115 configuring the current mirror circuit in the starting circuit 110. As a result, the potential of the gate terminal of each of the transistors M.sub.111, M.sub.113, and M.sub.115 increases, so that the potential of the drain terminal of the transistor NM.sub.111 electrically connected to the gate terminal also increases. At this time, a current value of the bias current I.sub.BIAS set by an aspect ratio (W/L ratio) of the transistors M.sub.105 and M.sub.109 is set to a value sufficiently larger than a current value of the drain current of the transistor NM.sub.111 to be a value obtained by dividing a gate-source voltage V.sub.gs of the transistor NM.sub.111 by the resistor R.sub.STUP, so that the drain voltage of the transistor NM.sub.111 (that is, the gate voltage of each of the transistors M.sub.111, M.sub.113, and M.sub.115) can be increased to the power supply voltage VDD. Specifically, in the example illustrated in FIG. 8, during a period of the timings t17 to t19, as the current value of the bias current I.sub.BIAS increases, the potential VPG0 of the node N.sub.VGP0 (that is, the gate voltage of each of the transistors M.sub.111, M.sub.113, and M.sub.115) increases.

[0094] Then, in each of the transistors M.sub.111, M.sub.113, and M.sub.115, when the gate-source voltage is sufficiently lower than the threshold voltage, each of the transistors M.sub.111, M.sub.113, and M.sub.115 transitions to the non-conductive state. As described above, the transistor M.sub.115 transitions to the non-conductive state, so that the supply of the starting current I.sub.STUP from the starting circuit 110 to the current source circuit 200 is interrupted. Further, the transistor M.sub.111 transitions to the non-conductive state, so that the inflow of the current from the input terminal IN to the side of the drain terminal of the transistor M.sub.111 is also limited. Similarly, the transistor M.sub.113 transitions to the non-conductive state, so that the inflow of the current from the second output terminal OUT2 to the side of the drain terminal of the transistor M.sub.113 is also limited. Therefore, in the example illustrated in FIG. 8, during the period of the timings t17 to t19, as the potential VGP0 of the node N.sub.VGP0 increases, the potential VGN0 of the node N.sub.VGN0 decreases.

[0095] In this way, after the timing t19, the starting circuit 110 transitions to an off state. Note that the current value of the bias current I.sub.BIAS supplied from the current source circuit 200 to the side of the drain terminal of the transistor NM.sub.111 at this time is limited to a value substantially equal to the current value of the drain current of the transistor NM.sub.111, which is a minimum current required to maintain the starting circuit 110 in an off state.

EMBODIMENT

[0096] Next, as an embodiment of the first configuration example, characteristics of the starting circuit according to the first configuration example will be described with reference to FIGS. 9 and 10. FIG. 9 is an explanatory diagram for explaining the characteristics of the starting circuit according to the first configuration example, and illustrates an example of a circuit for simulating the characteristic of the transistor NM.sub.111 self-biased, in the starting circuit 110 illustrated in FIG. 7. The transistors NM.sub.111, NM.sub.113, M.sub.111, and M.sub.113 in FIG. 9 correspond to the transistors NM.sub.111, NM.sub.113, M.sub.111, and M.sub.113 in the starting circuit 110 illustrated in FIG. 7, respectively. Further, a DC power supply V.sub.s illustrated in FIG. 9 imitates the source voltage of the transistor NM.sub.111. Note that, in the example illustrated in FIG. 9, a size ratio between the transistor NM.sub.111 and the transistor NM.sub.113 is adjusted so that the voltage is more likely to be generated on the side of the transistor NM.sub.113. Specifically, in the example illustrated in FIG. 9, the size ratio between the transistor NM.sub.111 and the transistor NM.sub.113 is 1:0.25.

[0097] In the circuit illustrated in FIG. 9, by sweeping the source voltage V.sub.s of the transistor NM.sub.111 and monitoring the drain current I.sub.D of the transistor NM.sub.111, the characteristic of the drain current of the transistor NM.sub.111 can be confirmed. Further, as described above with reference to FIG. 4, the characteristic of the current I.sub.R flowing through the resistor (that is, the characteristic of the current represented by (Formula 3) described above) can be confirmed by sweeping the applied voltage V.sub.S and monitoring the current I.sub.R in the circuit illustrated in FIG. 4.

[0098] For example, FIG. 10 is an explanatory diagram for explaining characteristics of the starting circuit according to the first configuration example. Specifically, FIG. 10 shows an example of simulation results of the drain current I.sub.D of the transistor NM.sub.111 based on the circuit illustrated in FIG. 9 and the current I.sub.R flowing through the resistor based on the circuit illustrated in FIG. 4. In FIG. 10, a horizontal axis represents a voltage value of each of the source voltage V.sub.s illustrated in FIG. 9 and the applied voltage V.sub.s illustrated in FIG. 4. Further, a vertical axis represents a current value of each of the drain current I.sub.D illustrated in FIG. 9 and the current I.sub.R illustrated in FIG. 4. In FIG. 10, a graph shown as reference symbol I.sub.D shows an example of the simulation result of the drain current I.sub.D illustrated in FIG. 9. Further, a graph shown as reference symbol I.sub.R shows an example of the simulation result of the current I.sub.R illustrated in FIG. 4. Note that, in the example illustrated in FIG. 10, for each of the drain current I.sub.D illustrated in FIG. 9 and the current I.sub.R illustrated in FIG. 4, simulation results of a maximum value, a representative value, and a minimum value in which a process variation of the threshold voltage V.sub.TH of the transistor NM.sub.111 or a temperature change of the threshold voltage V.sub.TH is considered are shown.

[0099] In FIG. 10, an intersection of the graph of the drain current I.sub.D and the graph of the current I.sub.R corresponding to the same condition becomes the drain current I.sub.D of the transistor NM.sub.111 in the power supply circuit 110 according to the first configuration example illustrated in FIG. 9. Note that, in the power supply circuit 110 illustrated in FIG. 9, a current obtained by replicating the drain current I.sub.D of the transistor NM.sub.111 by the current mirror circuit is supplied as the starting current I.sub.STUP to a device to be started (for example, the current source circuit 200). That is, the drain current I.sub.D of the transistor NM.sub.111 derived on the basis of FIG. 10 corresponds to the current value of the starting current I.sub.STUP supplied from the power supply circuit 110 to the current source circuit 200 in the example illustrated in FIG. 9.

[0100] Here, when the characteristics of the starting circuit according to the first configuration example illustrated in FIG. 10 and the characteristics of the starting circuit according to the comparative example illustrated in FIG. 5 are compared, both the maximum values of the starting currents are 2500 pA. On the other hand, the minimum value of the starting current is 15 pA in the starting circuit according to the comparative example, whereas it is 300 pA in the starting circuit according to the first configuration example. Further, the representative value of the starting current is 700 pA in the starting circuit according to the comparative example, whereas it is 750 pA in the starting circuit according to the first configuration example. As described above, the starting circuit according to the first configuration example has a smaller change width of the drain current I.sub.D (in other words, the change width of the starting current) than the starting circuit according to the comparative example. From this, it can be seen that the starting circuit according to the first configuration example is more suppressed in the influence of the variation in the threshold voltage V.sub.TH of the transistor NM.sub.111 than the starting circuit according to the comparative example.

[0101] As described above, according to the starting circuit according to the embodiment of the present disclosure, the influence of the variation in the threshold voltage V.sub.TH of the transistor (for example, the transistor NM.sub.111 illustrated in FIG. 7) configuring the starting circuit can be further reduced, and the change in the source voltage or the drain current can be further suppressed. That is, by applying the starting circuit, the change of the starting current can be further suppressed as compared with the starting circuit according to the comparative example described above. Therefore, for example, the change in the starting time of the device to be driven (for example, the current source circuit 200 illustrated in FIG. 7) can be further suppressed. In particular, in the case of the conventional starting circuit, when there is a constraint on the starting time, it is necessary to perform designing so that the maximum value of the starting time is less than the design target. In other words, it is necessary to perform designing with a margin so that the minimum value of the drain current of the transistor configuring the starting circuit is larger than the design target. On the other hand, since the starting circuit according to the embodiment of the present disclosure can suppress the change of the drain current as described above, for example, as compared with the conventional starting circuit, it is possible to suppress an increase in the current consumption according to a design considering the margin according to the change in the drain current, and it is possible to limit a design value (representative value) of the current consumption to a smaller value.

[0102] The first configuration example of the starting circuit according to the embodiment of the present disclosure has been described above with reference to FIGS. 7 to 10.

3.3. Second Configuration Example

[0103] Subsequently, a second configuration example of the starting circuit according to the embodiment of the present disclosure will be described. For example, FIG. 11 is an explanatory diagram for explaining the second configuration example of the starting circuit according to the embodiment of the present disclosure, and illustrates another example of the circuit configuration of the starting circuit illustrated in FIG. 6. Since a circuit configuration of a current source circuit 200 illustrated in FIG. 11 is substantially the same as the circuit configuration of the current source circuit 200 described with reference to FIG. 2, detailed description thereof will be omitted. Further, a starting circuit 120 illustrated in FIG. 11 corresponds to the example of the starting circuit 100 in the example illustrated in FIG. 6.

[0104] As illustrated in FIG. 11, the starting circuit 120 according to the second configuration example is different from the starting circuit 110 according to the first configuration example described with reference to FIG. 9 in that the starting circuit 120 includes a transistor NM.sub.115, and the other configuration is substantially the same as that of the starting circuit 110. Therefore, in the following description, the starting circuit 120 according to the second configuration example will be described, particularly focusing on a part different from the starting circuit 110 according to the first configuration example, and detailed description of substantially the same part as that of the starting circuit 110 will be omitted.

[0105] As illustrated in FIG. 11, in the starting circuit 120, the transistor NM.sub.115 is interposed between the side of the source terminal of the transistor NM.sub.113 of which the gate terminal and the drain terminal are electrically connected (that is, diode-connected) and the ground. The drain terminal of the transistor NM.sub.115 is electrically connected to the source terminal of the transistor NM.sub.113, and the source terminal thereof is electrically connected to the ground. Further, in the transistor NM.sub.115, the gate terminal and the drain terminal are electrically connected (that is, diode-connected).

[0106] Like the transistors NM.sub.111 and NM.sub.113, the transistor NM.sub.115 is configured as an N-type MOS transistor whose threshold voltage is adjusted to be near 0 V. In other words, the transistor NM.sub.115 has a characteristic that the source and the drain are held in a conductive state with a voltage not applied to the gate terminal. As a specific example, the transistor NM.sub.115 can be configured as a Native-NMOS. Note that the transistor NM.sub.115 corresponds to an example of a sixth MOS transistor.

[0107] With the above configuration, according to the starting circuit 120 according to the second configuration example, when the threshold voltage of the transistor NM.sub.111 is 0 V or more, it is possible to generate a higher gate voltage for the transistor NM.sub.111.

[0108] The second configuration example of the starting circuit according to the embodiment of the present disclosure has been described above with reference to FIG. 11.

3.4. Third Configuration Example

[0109] Subsequently, a third configuration example of the starting circuit according to the embodiment of the present disclosure will be described. For example, FIG. 12 is an explanatory diagram for explaining the third configuration example of the starting circuit according to the embodiment of the present disclosure, and illustrates another example of the circuit configuration of the starting circuit illustrated in FIG. 6. Since a circuit configuration of a current source circuit 200 illustrated in FIG. 12 is substantially the same as the circuit configuration of the current source circuit 200 described with reference to FIG. 2, detailed description thereof will be omitted. Further, a starting circuit 130 illustrated in FIG. 12 corresponds to the example of the starting circuit 100 in the example illustrated in FIG. 6.

[0110] As illustrated in FIG. 12, the starting circuit 130 includes transistors NM.sub.111 and NM.sub.113, a resistor R.sub.STUP, transistors M.sub.121 and M.sub.123, and diodes D.sub.121 and D.sub.123. Since the transistors NM.sub.111 and NM.sub.113 and the resistor R.sub.STUP are substantially the same as the transistors NM.sub.111 and NM.sub.113 and the resistor R.sub.STUP in the starting circuit 110 according to the first configuration example described with reference to FIG. 7, detailed description thereof will be omitted.

[0111] The transistors M.sub.121 and M.sub.123 configure a current mirror circuit. Specifically, the transistors M.sub.121 and M.sub.123 are configured as P-type MOS transistors and gate terminals thereof are electrically connected to each other. The gate terminal and the drain terminal of the transistor M.sub.121 are electrically connected (that is, diode-connected).

[0112] A back gate terminal of each of the transistors M.sub.121 and M.sub.123 is electrically connected to the drain terminal. Further, the source terminal and the drain terminal of each of the transistors M.sub.121 and M.sub.123 are electrically connected via a parasitic diode. Specifically, the source terminal and the drain terminal of the transistor M.sub.121 are electrically connected via the diode D.sub.121. More specifically, in the diode D.sub.121, the anode side is electrically connected to the source terminal of the transistor M.sub.121 and the cathode side is electrically connected to the drain terminal of the transistor M.sub.121. Similarly, the source terminal and the drain terminal of the transistor M.sub.123 are electrically connected via the diode D.sub.123. More specifically, in the diode D.sub.123, the anode side is electrically connected to the source terminal of the transistor M.sub.123 and the cathode side is electrically connected to the drain terminal of the transistor M.sub.123.

[0113] The drain terminal of the transistor M.sub.121 and the drain terminal of the transistor NM.sub.111 are electrically connected. Further, the drain terminal of the transistor M.sub.123 and the drain terminal of the transistor NM.sub.113 are electrically connected. Note that, in the starting circuit 130 according to the second configuration example, the transistors M.sub.121 and M.sub.123 correspond to examples of a third MOS transistor and a fourth MOS transistor, respectively.

[0114] Further, the source terminals of the transistors M.sub.121 and M.sub.123 are electrically connected to a signal line branched from the side of the drain terminal of the transistor M.sub.105 of the current source circuit 200. Further, the side of the drain terminal of the transistor M.sub.109 is electrically connected to the gate terminal of each of the transistors M.sub.121 and M.sub.123 configuring the current mirror circuit. That is, the drain terminal of the transistor M.sub.109 and the drain terminal of the transistor NM.sub.111 are electrically connected.

[0115] Here, the operation of the starting circuit 130, that is, the operation related to the starting of the current source circuit 200 will be described.

[0116] When the power supply voltage VDD is applied, the starting circuit 130 is turned on, and the starting current I.sub.STUP flows so as to be extracted from the current source circuit 200 toward the starting circuit 130. Specifically, the starting current I.sub.STUP flows from the side of the drain terminal of the transistor M.sub.105 toward the source terminal of each of the transistors M.sub.121 and M.sub.123. At this time, as the voltage value of the power supply voltage VDD increases, the current value of the starting current I.sub.STUP increases, and as the current value of the starting current I.sub.STUP increases, the potential of the node N.sub.VGP1 (that is, the gate voltage of each of the transistors M.sub.121 and M.sub.123) increases. Then, in each of the transistors M.sub.121 and M.sub.123, when the gate-source voltage sufficiently exceeds the threshold voltage, each of the transistors M.sub.121 and M.sub.123 transitions to the conductive state, and the increase in the power supply voltage VDD stops.

[0117] When each of the transistors M.sub.121 and M.sub.123 transitions to the conductive state, a drain current according to the starting current I.sub.STUP flows through the transistor NM.sub.121 from the drain terminal of the transistor M.sub.121. At this time, a current obtained by replicating the drain current by the current mirror circuit configured by the transistors M.sub.121 and M.sub.123 flows toward the side of the drain terminal of the transistor NM.sub.123.

[0118] As described above, the gate terminal and the drain terminal of the transistor NM.sub.113 are electrically connected, and the current flowing through the side of the drain terminal of the transistor NM.sub.113 is supplied to the node N.sub.VGN1 (that is, the gate terminal of each of the transistors NM.sub.111 and NM.sub.113). With the above configuration, the gate voltage of each of the transistors NM.sub.111 and NM.sub.113 (that is, the potential of the node N.sub.VGN0 is controlled to a voltage according to the threshold voltage of the transistor NM.sub.111. The present operation is the same as that of the starting circuit 110 according to the first configuration example described with reference to FIGS. 7 and 8.

[0119] In the current source circuit 200, when the transistor M.sub.107 transitions to the conductive state, the potential of the node N.sub.VGN electrically connected to the side of the drain terminal of the transistor M.sub.107 increases, and the potential of the node N.sub.VGP (that is, the gate voltage of each of the transistors M.sub.105, M.sub.107, and M.sub.109) decreases in conjunction with the increase in the potential. Further, as the potential of the node N.sub.VGN increases, the transistors M.sub.101 and M.sub.103 transition to the conductive state, and the increase in the potential of the node N.sub.VGN and the decrease in the potential of the node N.sub.VGP stop. As described above, the starting of the current source circuit 200 is completed, and a signal (drain current) flows between the source and the drain of each of the transistors M.sub.101, M.sub.103, M.sub.105, M.sub.107, and M.sub.109 configuring the current source circuit 200.

[0120] When the starting of the current source circuit 200 is completed, the signal transmitted between the source and the drain of the transistor M.sub.109 is supplied as the bias current I.sub.BIAS to the node N.sub.VGP1 (that is, the gate terminal of each of the transistors M.sub.121 and M.sub.123). As a result, the potential of the gate terminal of each of the transistors M.sub.121 and M.sub.123 increases, so that the potential of the drain terminal of the transistor NM.sub.111 electrically connected to the gate terminal also increases. At this time, a current value of the bias current I.sub.BIAS set by an aspect ratio (W/L ratio) of the transistors M.sub.105 and M.sub.109 is set to a value sufficiently larger than a current value of the drain current of the transistor NM.sub.111 to be a value obtained by dividing a gate-source voltage V.sub.gs of the transistor NM.sub.111 by the resistor R.sub.STUP, so that the drain voltage of the transistor NM.sub.111 (that is, the gate voltage of each of the transistors M.sub.121 and M.sub.123) can be increased to the power supply voltage VDD.

[0121] Then, in each of the transistors M.sub.121 and M.sub.123, when the gate-source voltage is sufficiently lower than the threshold voltage, each of the transistors M.sub.121 and M.sub.123 transitions to the non-conductive state. At this time, a potential difference between the source terminal side and the drain terminal side of each of the transistors M.sub.121 and M.sub.123 corresponds to a potential difference between the anode side and the cathode side of each of the diodes D.sub.121 and D.sub.123. In each of the diodes D.sub.121 and D.sub.123, the anode side is electrically connected to the drain terminal side of the transistor M.sub.109 of the current source circuit 200, and the cathode side is electrically connected to the drain terminal side of the transistor M.sub.105 of the current source circuit 200. For this reason, in each of the diodes D.sub.121 and D.sub.123, when the potential on the cathode side increases with the supply of the bias current I.sub.BIAS, the potential difference between the anode side and the cathode side becomes smaller, and the flow of the starting current I.sub.STUP is limited. In each of the diodes D.sub.121 and D.sub.123, when the potential of the cathode side increases more than the potential of the anode side (in other words, the potential of the node N.sub.VGP), reverse bias is applied to each of the diodes D.sub.121 and D.sub.123. That is, the flow of the starting current I.sub.STUP from the current source circuit 200 to the starting circuit 130 is interrupted, and the starting circuit 130 transitions to the off state.

[0122] The third configuration example of the starting circuit according to the embodiment of the present disclosure has been described above with reference to FIG. 12.

3.5. Supplement

[0123] The configurations described above as the first to third configuration examples are merely examples, and if the operation principle described with reference to FIG. 6 can be realized, the circuit configuration of the starting circuit according to the embodiment of the present disclosure is not limited. As a specific example, in the starting circuit 130 according to the third configuration example, similarly to the starting circuit 120 according to the second configuration example, a configuration corresponding to the transistor NM.sub.115 in the starting circuit 120 may be interposed between the source terminal of the transistor NM.sub.113 and the ground. As described above, the circuit configuration of the starting circuit according to the embodiment of the present disclosure may be appropriately changed without departing from the basic ideas of the operation principle described with reference to FIG. 6.

4. Conclusion

[0124] As described above, the starting circuit according to the embodiment of the present disclosure includes the N-type first MOS transistor whose threshold voltage is near 0 V, the resistor interposed between the source terminal of the first MOS transistor and the ground, and the control circuit controlling the gate voltage of the first MOS transistor. With the above configuration, the amount of starting current transmitted to the device to be driven and starting the device is controlled according to the control of the gate voltage by the control circuit. More specifically, the control circuit controls the gate voltage of the first MOS transistor, according to the threshold voltage of the first MOS transistor.

[0125] With the above configuration, according to the starting circuit according to the embodiment of the present disclosure, the influence of the variation in the threshold voltage of the first MOS transistor can be further reduced, and the change in the source voltage or the drain current can be further suppressed. That is, the amount of starting current transmitted to the device to be driven is also controlled according to the drain current. As described above, according to the starting circuit according to the embodiment of the present disclosure, since the change in the starting current can be further suppressed, for example, the change in the starting time of the device to be driven can be further suppressed. Therefore, for example, even in a situation where there is a constraint on the starting time of the device to be driven, it is possible to suppress an increase in the current consumption according to a design considering the margin according to the change in the starting current, and it is possible to limit a design value of the current consumption to a smaller value.

[0126] The preferred embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, but the technical scope of the present disclosure is not limited to such examples. It is obvious that a person with an ordinary skill in a technological field of the present disclosure could conceive of various alterations or corrections within the scope of the technical ideas described in the appended claims, and it should be understood that such alterations or corrections will naturally belong to the technical scope of the present disclosure.

[0127] Furthermore, the effects described in the present specification are merely illustrative or exemplary and are not restrictive. That is, the technology according to the present disclosure can exhibit other effects obvious to those skilled in the art from the description of the present specification in addition to or in place of the above-described effects.

[0128] Note that the following configurations also belong to the technical scope of the present disclosure.

(1)

[0129] A starting circuit comprising:

[0130] an N-type first MOS transistor whose threshold voltage is near 0 V;

[0131] a resistor interposed between a source terminal of the first MOS transistor and a ground; and

[0132] a control circuit controlling a gate voltage of the first MOS transistor, wherein

[0133] an amount of first current transmitted to a device to be driven and starting the device is controlled according to the control of the gate voltage.

(2)

[0134] The starting circuit according to (1), wherein

[0135] the control circuit controls the gate voltage of the first MOS transistor according to a threshold voltage of the first MOS transistor, and

[0136] the amount of first current is controlled according to the control of the gate voltage.

(3)

[0137] The starting circuit according to (1) or (2), wherein

[0138] the control circuit includes

[0139] an N-type second MOS transistor in which a gate terminal and a drain terminal are electrically connected, the gate terminal is electrically connected to a gate terminal of the first MOS transistor, and a threshold voltage is near 0 V, and

[0140] a current mirror circuit configured by P-type MOS transistors,

[0141] a second current is output from the current mirror circuit to a drain terminal of the first MOS transistor, and

[0142] a third current obtained by replicating the second current is output from the current mirror circuit to a drain terminal of the second MOS transistor.

(4)

[0143] The starting circuit according to (3), wherein

[0144] the current mirror circuit includes a P-type third MOS transistor and a P-type fourth MOS transistor,

[0145] in the third MOS transistor, a gate terminal and a drain terminal are electrically connected and the drain terminal is electrically connected to the drain terminal of the first MOS transistor, and

[0146] in the fourth MOS transistor, a drain terminal is electrically connected to the drain terminal of the second MOS transistor and a source terminal is electrically connected to the ground.

(5)

[0147] The starting circuit according to (4), wherein

[0148] a potential of the drain terminal of the first MOS transistor is controlled according to the supply of a fourth current from the device to the gate terminal of each of the third MOS transistor and the fourth MOS transistor, and

[0149] the transmission of the first current is controlled according to the potential of the drain terminal.

(6)

[0150] The starting circuit according to (5), wherein

[0151] the current mirror circuit includes a P-type fifth MOS transistor, and

[0152] according to the potential of the drain terminal of the first MOS transistor, a current obtained by replicating the second current by the fifth MOS transistor is supplied as the first current from a drain terminal of the fifth MOS transistor to the device.

(7)

[0153] The starting circuit according to (5), further comprising:

[0154] a first diode whose anode side is electrically connected to a source terminal of the third MOS transistor and whose cathode side is electrically connected to the drain terminal of the third MOS transistor; and

[0155] a second diode whose cathode side is electrically connected to the source terminal of the fourth MOS transistor and whose cathode side is electrically connected to the drain terminal of the fourth MOS transistor, wherein

[0156] in each of the third MOS transistor and the fourth MOS transistor, a back gate terminal and the drain terminal are electrically connected, and

[0157] extraction of the first current to the side of the source terminal of each of the third MOS transistor and the fourth MOS transistor is controlled according to the potential of the drain terminal of the first MOS transistor.

(8)

[0158] The starting circuit according to any one of (5) to (7), wherein the source terminal of the fourth MOS transistor is electrically connected to the ground via an N-type N-type sixth MOS transistor whose threshold voltage is near 0 V.

(9)

[0159] The starting circuit according to any one of (5) to (8), wherein the device is a current source circuit.

(10)

[0160] The starting circuit according to (9), wherein

[0161] the device is a self-bias type current source circuit, and

[0162] a part of a current flowing through the current source circuit is supplied to the gate terminal of each of the third MOS transistor and the fourth MOS transistor as the fourth current.

REFERENCE SIGNS LIST

[0163] 100, 110, 120, 130 STARTING CIRCUIT [0164] 101 STARTING CURRENT GENERATION CIRCUIT [0165] 103 GATE VOLTAGE CONTROL CIRCUIT [0166] 200 CURRENT SOURCE CIRCUIT [0167] NM.sub.11 N-TYPE MOS TRANSISTOR [0168] R.sub.STUP RESISTOR