Phase-change memory cell with vanadium oxide based switching layer

Abstract

A phase-change memory cell, including, in sequence in the following order: a first electrode layer, a switching layer comprising vanadium oxide (VO.sub.x) material, a phase-change material layer, and a second electrode layer, is provided. The switching layer is adapted to control the phase-change material layer to switch between a crystalline state and an amorphous state when a voltage is applied to the first electrode layer and the second electrode layer.

Claims

1. A device, comprising, in sequence in the following order: 1) a first electrode layer; 2) a switching layer comprising vanadium oxide (VO.sub.x) material; 3) a phase-change material layer; and 4) a second electrode layer; wherein: the switching layer is adapted to control the phase-change material layer to switch between a crystalline state and an amorphous state when a voltage is applied to the first electrode layer and the second electrode layer, wherein the device is configured to 1) apply an electric pulse greater than a threshold voltage Vth of the switching layer between the first electrode layer and the second electrode layer, so that a temperature of the switching layer rises to be higher than its phase transition temperature, and the VOx material switches from a monoclinic crystal system in an insulating state to a tetragonal crystal system in a metallic state: 2) apply an electric pulse less than a holding voltage VoI.sub.d of the switching layer between the first electrode layer and the second electrode layer, so that the temperature of the switching layer decreases to be lower than its phase transition temperature, and the VOx material returns to the monoclinic crystal system in the insulating state; 3) apply a resetting pulse having a voltage greater than a write operation threshold voltage V.sub.Reset and a falling edge of 10 ns between the first electrode layer and the second electrode layer, so that the temperature of the phase-change material layer rises beyond melting temperature, the long-range order of the crystalline state is destroyed, and the phase-change material rapidly cools down below the crystallization temperature under the falling edge; there is no time for the phase-change material to crystallize; the phase-change material is in the amorphous state, and the phase-change material layer is in a low resistance state, to achieve a write operation; and 4) apply a setting pulse having a voltage between the phase transition voltage V.sub.set of the phase-change material layer and the write operation threshold voltage V.sub.Reset and a pulse width of 200 ns between the first electrode layer and the second electrode layer, so that the temperature of the phase-change material rises between the crystallization temperature and the melting temperature for 200 ns to ensure the crystallization of the phase-change material; the phase-change material changes from an amorphous state to a crystalline state, and the phase-change material layer is in a high resistance state, to achieve an erase operation.

2. The device of claim 1, wherein the phase-change material layer comprises a compound selected from GeTe, SbTe, BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, GeSbTe, and AgInSbTe, or a mixture of the compound and a dopant selected from S, N, O, Cu, Si and Au.

3. The device of claim 1, wherein the first electrode layer and the second electrode layer comprise TiW, Pt, Au, W or an inert electrode.

4. The device of claim 2, wherein the first electrode layer and the second electrode layer comprise TiW, Pt, Au, W or an inert electrode.

5. The device of claim 1, wherein X of the VO.sub.x material ranges from 1.9 to 2.1.

6. The device of claim 2, wherein X of the VO.sub.x material ranges from 1.9 to 2.1.

7. The device of claim 3, wherein X of the VO.sub.x material ranges from 1.9 to 2.1.

8. The device of claim 4, wherein X of the VO.sub.X material ranges from 1.9 to 2.1.

9. The device of claim 1, wherein a threshold voltage of the switching layer is less than a phase transition voltage V.sub.set of the phase-change material layer.

10. The device of claim 2, wherein a threshold voltage of the switching layer is less than a phase transition voltage V.sub.set of the phase-change material layer.

11. The device of claim 8, wherein a threshold voltage of the switching layer is less than a phase transition voltage V.sub.set of the phase-change material layer.

12. The device of claim 1, wherein an area of the switching layer is 100 nm.sup.2-30 m.sup.2.

13. The device of claim 2, wherein an area of the switching layer is 100 nm.sup.2-30 m.sup.2.

14. The device of claim 11, wherein an area of the switching layer is 100 nm.sup.2-30 m.sup.2.

15. The device of claim 1, wherein an insulation resistance of the VO.sub.X material of the switching layer is greater than a resistance thereof in the metallic state, and the ratio of the insulation resistance to the resistance in the metallic state is greater than 60.

16. The device of claim 2, wherein an insulation resistance of the VO.sub.x material of the switching layer is greater than a resistance thereof in the metallic state, and the ratio of the insulation resistance to the resistance in the metallic state is greater than 60.

17. The device of claim 14, wherein an insulation resistance of the VO.sub.x material of the switching layer is greater than a resistance thereof in the metallic state, and the ratio of the insulation resistance to the resistance in the metallic state is greater than 60.

18. An operation method of the device of claim 1, the method comprising: 1) applying an electric pulse greater than a threshold voltage V.sub.th of the switching layer between the first electrode layer and the second electrode layer, so that a temperature of the switching layer rises to be higher than its phase transition temperature, and the VO.sub.x, material switches from a monoclinic crystal system in an insulating state to a tetragonal crystal system in a metallic state; 2) applying an electric pulse less than a holding voltage V.sub.hoid of the switching layer between the first electrode layer and the second electrode layer, so that the temperature of the switching layer decreases to be lower than its phase transition temperature, and the VO.sub.x material returns to the monoclinic crystal system in an insulating state; 3) applying a resetting pulse having a voltage greater than a write operation threshold voltage V.sub.Reset and a falling edge of 10 ns between the first electrode layer and the second electrode layer, so that the temperature of the phase-change material layer rises beyond the melting temperature, the long-range order of the crystalline state is destroyed, and the phase-change material rapidly cools down below the crystallization temperature under the falling edge; there is no time for the phase-change material to crystallize; the phase-change material is in an amorphous state, and the phase-change material layer is in a low resistance state, to achieve a write operation; and 4) applying a setting pulse having a voltage between the phase transition voltage Vse.sub.t of the phase-change material layer and the write operation threshold voltage V.sub.Reset and a pulse width of 200 ns between the first electrode layer and the second electrode layer, so that the temperature of the phase-change material rises between the crystallization temperature and the melting temperature for 200 ns to ensure the crystallization of the phase-change material; the phase-change material changes from an amorphous state to a crystalline state, and the phase-change material layer is in a high resistance state, to achieve an erase operation.

19. The method of claim 18, wherein the threshold voltage V.sub.th of the switching layer is less than the phase transition voltage Vse.sub.t of the phase-change material layer.

20. A method for preparing the switching layer of the device of claim 1, the method comprising: forming a layer of vanadium oxide by ion beam sputtering or magnetron sputtering, annealing the layer of vanadium oxide in a nitrogen or argon atmosphere, and cooling to room temperature to obtain the switching layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a structure diagram of a phase-change memory cell of a MOS tube in a conventional 1T1R.

(2) FIG. 2 is a structure diagram of a phase-change memory cell according to one embodiment of the disclosure.

(3) FIG. 3 is an I-V characteristic curve of a vanadium oxide (VO.sub.x) material of the disclosure, which comprises a step-up curve and a step-down curve showing the current variation of a phase-change memory cell according to one embodiment of the disclosure.

(4) FIG. 4 is an R-V characteristic curve of a vanadium oxide (VO.sub.x) material of the disclosure, which comprises a step-up curve and a step-down curve showing the resistance variation of a phase-change memory cell according to one embodiment of the disclosure.

(5) FIG. 5 is an I-V characteristic of a phase-change memory cell without a vanadium oxide-based switching layer.

(6) FIG. 6 is an I-V characteristic curve of a phase-change memory cell according to one embodiment of the disclosure.

(7) FIG. 7 is a graph showing the function testing of a phase-change memory cell according to one embodiment of the disclosure. FIG. 8 is an R-T characteristic curve of a vanadium oxide (VO.sub.x) material of the disclosure.

(8) In the drawings, the following reference numbers are used: 1. First electrode layer, 2. Switching layer, 3. Phase-change material layer, 4. Second electrode layer, 5. Phase-change resistor, and 6. Transistor.

DETAILED DESCRIPTION

(9) To further illustrate, embodiments detailing a phase-change memory cell are described below. It should be noted that the following embodiments are intended to describe and not to limit the disclosure.

(10) The disclosure provided a phase-change memory cell comprising a vanadium oxide (VO.sub.x)-based switching layer. The on and off state of the VO.sub.x-based switching layer can be controlled by an external voltage, thus to control the switching of the phase-change memory cell. The VO.sub.x is used as a switching material of the phase-change memory cell.

(11) As shown in FIG. 2, a phase-change memory cell, comprises, in sequence in the following order: a first electrode layer 1, a switching layer 2 comprising vanadium oxide (VO.sub.x), a phase-change material layer 3 and a second electrode layer 4. When a voltage is applied to the first electrode layer and the second electrode layer, the switching layer is adapted to control the phase-change material layer to switch between in a crystalline state and in an amorphous state.

(12) Specifically, as shown in FIG. 8, when a voltage is applied to the first electrode layer and the second electrode layer, the switching layer can switch between a high resistance state and a low resistance state. When a high-intensity electric pulse greater than a threshold voltage V.sub.th of the switching layer is applied, the generated heat raises the temperature of the switching layer above its phase transition temperature and therefore transform the VO.sub.x, material from an insulating monoclinic crystal system to a metallic tetragonal crystal system. When an electrical pulse less than the holding voltage V.sub.hold id of the switching layer is applied, the temperature of the switching layer falls below the phase transition temperature and the VO.sub.x material therefore returns to high-resistance insulating state. In other words, the VO.sub.x material achieves a reversible phase transformation under thermal energy. The phase-change material layer uses its different resistance states to store data. The phase-change material layer is in a low resistance state in the presence of a write operation pulse; and the phase-change material layer is in a high resistance state in the presence of an erase operation pulse.

(13) To prepare a VO.sub.x layer having a phase-change characteristic, a vanadium oxide thin film is first sputtered on a substrate by ion beam sputtering, DC magnetron sputtering or RF magnetron sputtering, followed by an annealing in a protective gas atmosphere such as nitrogen or argon and then naturally cooled to room temperature to obtain the VO.sub.x material. Comparing the sputtering method with the conventional evaporation method, (1) the energy of atoms deposited by the sputtering method is high, forming a dense film structure and displaying good adhesion; (2) it is easy to control the composition when preparing a VO.sub.x film; (3) metal vanadium has a melting point of 1890 10 C. The evaporation deposition method only evaporated vanadium at a very high base temperature, but the sputtering method is convenient for sputtering materials having high melting points. Compared with PLD method, although the PLD method has the ability to obtain high-quality films, it is difficult to form large-area and uniform films and related equipment is expensive, leading to the PLD method is not suitable for going into production, but the sputtering method is well suited. Compared with other methods: (1) the sol-gel method can form films on a large-area and non-planar substrate, while it has the difficulty in preparing a high-quality VO.sub.x film with high orientation and good switching characteristics. The produced films, whose characteristics are difficult to control and the density is inferior, is easy to have defects such as bubbles or cracks, and easy to cause pollution; (2) due to the use of noble gases and toxic gases, chemical vapor deposition is harmful to the health of workers and unfavorable to environmental protection; (3) equipment used for molecular beam epitaxy and atomic layer deposition are relatively expensive and difficult to operate, which is not conducive to mass and industrial production.

(14) FIG. 3 is a graph showing a V-I curve of a VO.sub.x layer. Gradually increasing the applied voltage on the VON, when the voltage reaches to the threshold voltage V.sub.th, the current through the VO.sub.x sharply increases, and the VO.sub.x changes from a semiconducting high resistance state to a metallic low resistance state. The switching layer is thus turned on. Conversely, gradually reducing the applied voltage on the VO.sub.x, when the voltage reduces to the holding voltage V.sub.hold, the current through the VO.sub.x sharply reduces, and the VO.sub.x returns to the semiconducting high resistance state. The switching layer is thus closed.

(15) The phase-change memory cell uses a 1D1R structure without a transistor, and is smaller in size and more advantageous for the 3D stacking compared with 1T1R structure. The preparation process of the VO.sub.x comprises sputtering and annealing at room temperature, which is simple and low-cost compared with diodes prepared at high temperatures. The threshold voltage of the VO.sub.x is much less than the phase-change threshold voltage V.sub.pc of the phase-change cell, leading to a larger operation window for the phase-change memory cell. The on-off current ratio of the VO.sub.x is up to 10.sup.4. This can reduce the leakage current and provide a large drive current.

(16) FIG. 3 shows a typical I-V characteristic curve of the VO.sub.x material, and FIG. 4 is a typical R-V curve. The two figures show that the VO.sub.x changes from high resistance to low resistance when an applied voltage on the VO.sub.x reaches to 2.2 V, and the ratio of the on-state current to the off-state current is close to three orders of magnitude, which is called a threshold voltage Vth.

(17) In certain examples of the disclosure, the threshold voltage V.sub.th of the VO.sub.x is related to the specific parameters of the VO.sub.x preparation process. The value of the threshold voltage V.sub.th is positively correlated with the oxygen concentration during the sputtering process of the VO.sub.x, but the size of the switching layer is negatively correlated with the threshold voltage V.sub.th.

(18) In certain examples of the disclosure, the insulation resistance of the VO.sub.x material is larger than the resistance in the metallic state, and the ratio of the insulation resistance to the resistance in the metallic state is greater than 100, especially greater than 10000. The ratio of the two resistance is related to the specific parameters in the preparation process, and the resistance ratio decreases as the oxygen concentration increases. The resistance is also related to the size of the VO.sub.x layer, the smaller the size, the smaller the on-off resistance of the switching layer, and the larger the on-off current ratio. Therefore, the phase-change memory cell has better switching properties in a small-sized and high-density memory array.

(19) In certain examples of the disclosure, the phase-change temperature of the VO.sub.x material is about 68 C., especially from 60 C. to 80 C.

(20) FIG. 5 shows a typical I-V characteristic curve of phase-change material GeSbTe (GST). The figure shows that when the applied voltage reaches to the phase-change voltage V.sub.Set of the phase-change material, the heat generated by the phase-change material can rise beyond the crystallization temperature. Hold the temperature for an atomic relaxation time, the material changes from a disordered amorphous state to an ordered crystalline state.

(21) In certain examples of the disclosure, the ratio of the amorphous resistance to the crystalline resistance is larger than 10, especially greater than 100,000.

(22) In certain examples of the disclosure, the phase-change voltage V.sub.Set of the phase-change material is related to the doping concentration of the phase-change material. To improve the phase transition voltage V.sub.Set of the phase-change cell, the phase-change material is doped with N and Si.

(23) FIG. 6 shows an I-V characteristic curve of the phase-change memory cell. The current increases as the applied voltage gradually increases from zero, and the current sharply jumps when the applied voltage reaches to the threshold voltage V.sub.th, indicating that the VO.sub.x changes from off-state to on-state, the overall resistance sharply reduces and the switching layer is thus turned on. With the switching layer being on, gradually increases the applied voltage, the circuit jumps sharply once again when the applied voltage reaches to the phase-change voltage V.sub.Set. Because the applied voltage reaches to the phase-change voltage of the phase-change material GST, the GST changes from an amorphous state to a crystalline state and the resistance is reduced, realizing the erase operation of the phase-change memory cell. In addition, the threshold voltage V.sub.th of the switching layer is much less than the phase-change voltage V.sub.Set of the phase-change cell, leading to a larger operation windows for the phase-change cell.

(24) FIG. 7 shows a graph showing the function testing of the phase-change memory cell. To study the read function of TiWGST/VO.sub.2/TiW, an erase pulse (setting pulse) is applied to the cell. The erase pulse having an amplitude of 6 V and a pulse width of 500 ns is applied considering the phase-change voltage of GST is 4.6 V. Comparing the two curves in the figures, the scanning voltage ranges from 0-2V, and GST changes from an amorphous state to a crystalline state after applying the erase pulse. The storage state can be distinguished by the resistance value as long as read voltage is slightly larger than the threshold voltage (0.9V).

(25) It will be obvious to those skilled in the art that changes and modifications may be made, and therefore, the aim in the appended claims is to cover all such changes and modifications.