Microfabricated ion trap chip with in situ radio-frequency sensing

Abstract

A radio-frequency (RF) surface ion trap chip includes an RF electrode and an integrated capacitive voltage divider in which an intermediate voltage node is capacitively connected between the RF electrode and a ground. A sensor output trace is connected to the intermediate voltage node.

Claims

1. Apparatus comprising an ion trap chip of the kind in which a radio-frequency (RF) surface ion trap including an RF electrode is disposed on a substrate having a plurality of metallization levels including a top metallization level N, N a positive integer, wherein: the ion trap chip further comprises a capacitive voltage divider integrated on the ion trap chip; the capacitive voltage divider includes a sensor plate, wherein the sensor plate is sandwiched between and parallel to at least a portion of the RF electrode and at least a portion of a ground plane electrode situated at a lower metallization level than the RF electrode and sensor plate, capacitively connected between the RF electrode and said ground plane electrode, and situated on at least a first metallization level lower than the top metallization level; the ion trap chip further comprises a sensor output trace connected to the sensor plate, formed at least in part in a different metallization layer than the first metallization layer, and adapted for conveying an RF voltage signal from the sensor plate to a connection to off-chip sensing circuitry; the sensor plate is coupled through a first capacitance to the RF electrode and through a second capacitance to the ground plane electrode; and the first capacitance is less than the second capacitance.

2. The apparatus of claim 1, wherein the RF electrode is formed in the top metallization layer.

3. The apparatus of claim 2, wherein the sensor plate is situated at least in part on a metallization layer N1 that is next below the top metallization layer.

4. The apparatus of claim 3, wherein the sensor output trace is formed in a metallization layer N2 that is next below the N1 metallization layer.

5. The apparatus of claim 4, wherein the sensor output trace is connected by vertical electrical connections to a portion of the N1 metallization layer.

6. The apparatus of claim 5, wherein the sensor output trace is shielded, at least in part, by a ground plane in the N1 metallization layer next above it and by a ground plane in a metallization layer N3 next below it.

7. The apparatus of claim 1, wherein the capacitive voltage divider has a divider ratio of about 200:1.

8. The apparatus of claim 1, further comprising an off-chip signal processor connected to the sensor output trace for receiving signals indicative of RF amplitude.

9. The apparatus of claim 8, wherein the off-chip signal processor is connected to an RF source for controlling the RF source, and wherein the RF source has an RF output connected to the RF electrode.

10. The apparatus of claim 1, further comprising a temperature-sensing metal wire affixed to, and in thermal contact with, the substrate.

11. The apparatus of claim 10, further comprising one or more capacitors that are integrated on the substrate and connected to the temperature-sensing metal wire as RF shunts from the said wire to ground.

12. Apparatus comprising an ion trap chip of the kind in which a radio-frequency (RF) surface ion trap including an RF electrode is disposed on a substrate having a plurality of metallization levels including a top metallization level N, N a positive integer, wherein: the ion trap chip further comprises a capacitive voltage divider integrated on the ion trap chip; and the capacitive voltage divider includes an intermediate voltage node capacitively connected between the RF electrode and a ground on a metallization level lower than the top metallization level; and wherein the ion trap chip further comprises: a sensor output trace connected to the intermediate voltage node; a temperature-sensing metal wire affixed to, and in thermal contact with, the substrate; one or more capacitors that are integrated on the substrate and connected to the temperature-sensing metal wire as RF shunts from the said wire to ground; and a four-probe resistance sensor connected to the temperature-sensing metal wire for sensing its electrical resistance.

13. The apparatus of claim 12, further comprising an off-chip signal processor connected to the four-probe resistance sensor so as to receive from it a signal indicating the electrical resistance of the temperature-sensing metal wire.

14. The apparatus of claim 13, further comprising a heating wire and a heating current source, wherein the heating source is connected so as to be controlled by the signal processor and so as to drive a controllable heating current through the heating wire.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional cartoon view of an example ion trap that uses two metallization layers.

(2) FIG. 2 is an overhead view of the ion trap of FIG. 1.

(3) FIG. 3 is an overhead view of a fabricated prototype similar to the ion trap of FIGS. 1 and 2. The loading hole and part of the electrode layout are visible in the figure.

(4) FIG. 4 is a detail of the prototype of FIG. 3, shown in perspective view. Visible features in the figure include portions of the loading hole, the two inner dc electrodes bracketing the loading hole, and the RF electrode.

(5) FIG. 5 is a notional cartoon view, in cross-section, of an example ion trap that uses four metallization layers. The figure is highly simplified, and its scale is grossly distorted for clarity of presentation.

(6) FIGS. 6A and 6B provide a cross-sectional view, approximately to scale, of the slotted quantum region of an ion trap fabricated in four metallization layers. FIG. 6B is a detail of FIG. 6A.

(7) FIG. 7 is an elevational sectional view of an amplitude sensor according to the principles discussed here.

(8) FIG. 8 is a cutaway perspective view of the sensor of FIG. 6.

(9) FIG. 9 is a graph of the output voltage from a sensor such as the sensor of FIGS. 6 and 7 as a function of frequency. The output voltage is expressed as a voltage ratio. Three plots are shown, each for a respective value of the load resistance that terminates the sensor output circuit.

(10) FIG. 10 is a plan view of a complete ion trap chip, in an illustrative example.

DETAILED DESCRIPTION

(11) FIGS. 1 and 2 provide schematic views of an example ion trap of the kind reported in D. Stick et al. (16 Nov. 2010), cited above. The ion trap described here is offered solely for illustrative purposes and is not meant to be limiting.

(12) FIG. 1 is a cross-sectional view of the ion trap, and FIG. 2 is an overhead view. FIG. 3 is an overhead view of a fabricated prototype, showing the loading hole and part of the electrode layout. FIG. 4 is a detail in perspective view, showing portions of the loading hole, the two inner dc electrodes bracketing the loading hole, and the RF electrode.

(13) The device is fabricated on an SOI wafer 100 using known photolithographic techniques and other techniques of CMOS and MEMS processing. It includes two metal layers 102, 104 (M1 and M2) separated by an insulating layer 106 of silicon dioxide. Geometrically, the trap has a symmetric six-rail design with a 100-m-wide slot 108 (the loading hole) etched through the substrate to allow for backside ion loading and optical access.

(14) Adjacent to the slot, as best seen in FIG. 3, are split central control electrodes 110, 112, two electrodes 114, 116 with RF voltages applied, and forty outer segmented control electrodes 118, 120. The control electrodes (also referred to as dc electrodes) have quasistatic voltages applied to them.

(15) As best seen in FIG. 1, the oxide layer 106, 14 m thick, separates the top metal layer from the bottom metal layer. Each metal layer is aluminum, 2.4 m thick.

(16) Turning back to FIG. 3, the two RF rails 114, 116 are each 60 m thick and are separated by 140 m. The combined capacitance of the RF rails is about 7 pF to RF ground.

(17) The equilibrium trapping position is about 80 m above the trap surface.

(18) Turning again to FIG. 1, the oxide insulating layer 106 is controllably etched back to expose the RF ground plane 102 in M1 directly beneath the electrodes, and to recess the oxide support walls for the electrodes in M2. Because of this recess 130, the electrode metal overhangs the oxide, thus reducing the amount of insulator exposed to a line-of-sight from the trapping region. One benefit of this overhang is that it enables a metal of choice to be evaporated onto the top electrodes without causing short circuits.

(19) The electrical connections 132 between metallization layers, as seen in FIG. 1, are made by 2.7-m via technology.

(20) Optionally, the exposed silicon surfaces can be evaporatively coated with a ground layer, for example a 500-nm layer of gold.

(21) The implementation shown in FIGS. 1 and 2 is readily modified by adding additional metallization layers, using conventional CMOS fabrication techniques. In particular, it may be advantageous for at least some applications to add a ground plane on a new M1 layer beneath the top metal layer (i.e., beneath the layer shown in FIGS. 1 and 2 as the M1 layer in the illustrated implementation).

(22) For example, FIG. 5 provides a notional cross-sectional view of a more recent fabrication technology for ion traps that uses four metallization layers 501, 502, 503, 504, i.e., M1-M4. The respective layers are separated by oxide pillars. Connections are made among the layers with tungsten via interconnects. FIG. 5 is not drawn to scale, and various simplifications have been made for clarity of presentation.

(23) The electrodes in the top metal (M4) overhang their supporting oxide walls 506, as described above. These overhangs are beneficial for, among other things, shielding the trapped ions from stray charges on the dielectric surfaces.

(24) The DC and RF trap electrodes 508, 510 are fed by buried metal lines on M2. Microwave signals for controlling state transitions may be delivered by buried transmission lines on M3 and shielded by a surface ground plane 512 on M4.

(25) FIGS. 6A and 6B provide a more realistic drawing, approximately to scale, of the slotted quantum region of an ion trap fabricated in four metallization layers. FIG. 6B is a detail of FIG. 6A. The metallization layer M1A is a diffusion barrier of titanium nitride. The other metallization layers (i.e., M1B, M2, M3, and M4) are composed of aluminum alloyed with 0.5% copper. The non-limiting example that is illustrated has a 60-m-wide slot 600 in the quantum region. In sequence from the center of the slot, the electrodes shown in the drawing are: DC control electrodes 602 in M3, RF electrodes 604 in M4, DC control electrodes 606 in M4, and a ground plane 608 in M3. Each inner DC electrode 602 is seen to be connected by tungsten vias 610 to the M1 level, and each outer DC electrode 606 is seen to be connected by tungsten vias 612 to the M2 level. Typical thicknesses are indicated on the drawing, including the height of the trapped ion 614 above the M4 level. The metallization levels and the exposed dielectric surfaces are overcoated with gold.

(26) A still more recent advance in fabrication technology for ion traps uses six metallization layers. The additional metal layers provide more routing space to connect electrodes, which may be densely distributed, to the bond pads situated near the edges of the trap chip. By adding more metal layers, we can also increase the dielectric thickness between the RF electrodes and the ground planes. This has the benefit of reducing the overall capacitance of the RF electrode without sacrificing chip area that might be needed for the lithographic definition of structural features such as silicon dioxide support pillars for the electrodes.

(27) In a non-limiting example, electrodes are provided on the top metal (M6) layer, shielding is provided by ground planes on the next two layers (M5 and M4), signal routing is provided by traces on the next two layers (M3 and M2), and a ground plane is provided on the bottom layer (M1).

(28) As explained above, a stable RF amplitude is an important condition for RF Paul traps to be useful in quantum information processing. Feedback stabilization is a useful approach for satisfying this condition. Feedback stabilization, however, requires a sensor that can supply a control signal indicative of the RF amplitude. Desirably, the sensor is thermally stable and adds no significant capacitance.

(29) FIG. 7 is an elevational sectional view, and FIG. 8 is a cutaway perspective view, of a new RF amplitude sensor that we have designed for a microfabricated surface electrode ion trap. The new sensor uses a capacitive voltage divider 700 between the RF electrode 701 and ground 702. This capacitive voltage divider is integrated into the ion trap.

(30) The path from the RF electrode to ground includes a capacitance 703 between the RF electrode 701 and a sensor plate 706 (referred to here as the upper capacitance with reference to its position in the drawings), and a capacitance 708 between the sensor plate 706 and ground 702 (referred to here as the lower capacitance with reference to its position in the drawings). The upper capacitance is realized by two parallel metal plates separated by silicon dioxide interlayer dielectric. One of these plates is constituted by a portion of the RIF electrode 701 of the ion trap. The other plate is the sensor plate 706.

(31) In the example of FIGS. 7 and 8, the RE electrode is fabricated in the top metal layer, i.e. the layer M4. The sensor plate is fabricated in the M3 and M2 metal layers. The upper capacitance, i.e. the capacitance between the RF electrode and the sensor plate, is the capacitance that obtains between M4 and M3, and the sensor signal is passed vertically through vias from M3 to M2 and extracted on a lead fabricated in M2. The upper capacitance is designed in the present, non-limiting, example to be about 80 fF. The vias between M3 and M2 can be fabricated, for example, by conventional CMOS back-end-of-line processing.

(32) As noted, the signal from the sensor plate is routed out of the device on a trace on M2 that passes through a ground channel between ground planes. The pertinent ground planes in the example of FIGS. 7 and 8 are formed in M1 and M3. The lower capacitance is realized by the sensor routing trace and its surrounding ground planes.

(33) The lower capacitance is determined by the width of the trace for sensor routing and by the separation between that trace and its surrounding ground planes. The chosen value for the lower capacitance in the present, non-limiting, example is about 16 pF. The combination of about 80 fF for the upper capacitance and about 16 pf for the lower capacitance yields a divider ratio of about 200:1. (It will be understood that the upper capacitance is the smaller of these two quantities.)

(34) One notable feature of our sensor is that it exploits the capacitance from RE electrode to ground that is already present in the ion trap. Hence, there is no need to add to the capacitance that is already present.

(35) For a given RF amplitude, the output voltage from the sensor will depend on frequency and on the load resistance R.sub.LOAD that terminates the sensor output circuit. FIG. 9 is a graph showing that dependence (expressed as a voltage ratio) for three example values of the load resistance, namely, 50 , 1000, and 5000. The three plots in FIG. 8 were simulated from equivalent circuit models. A processor situated off chip can be used to make the conversions necessary for interpreting the sensor output signal.

(36) As is desirable, our capacitive voltage divider can operate over the range from liquid helium cryogenic temperatures to room temperature. It is important in this regard that the upper capacitance and the lower capacitance will both scale the same way with temperature, so that the voltage at the sensor output will be temperature-independent.

(37) As explained above, temperature stabilization is another important condition for RF Paul traps that are to be used in quantum information processing. Hence, a temperature sensor is another useful feature of an ion trap.

(38) We have provided a temperature sensor in the form of a thin, meandering aluminum wire. In a nonlimiting example, the aluminum wire is 2 m wide and 140 mm long and has a room-temperature resistance of about 1 k. This resistance drops to about 70, when the temperature is reduced to 4 K.

(39) In an example configuration, the meandering aluminum wire follows a course along the perimeter of the ion trap die, folds back on itself, and follows a parallel course for several repetitions. For the purpose of thermal sensing, the precise placement of the sensor wire on the die is not believed to be critical.

(40) The resistance of the meandering aluminum wire is an indicator of the temperature. Using the well-known four-probe technique, the resistance can be accurately measured over a temperature range from about 4 K to 500 K, which is the maximum operating temperature of our example device.

(41) To reduce noise in the temperature-sensing circuit, capacitors are provided to provide a path to ground for RF drive voltage that might be picked up by the sensor wire. In example implementations, these capacitors are integrated directly on the chip.

(42) A typical example of a suitable total capacitance value for this purpose is about 1 nF.

(43) A heating wire can also be provided. In examples, the heating wire is a meandering aluminum wire having the same dimensions as the wire for the temperature sensor. The heating wire does not need to be capacitively, shunted. In fact, it is preferably isolated from any trench capacitors so that it can early voltages exceeding the capacitor breakdown voltages.

(44) FIG. 10 is an illustrative example of a complete ion trap chip with a linear trap, shown in plan view. Features shown in the figure include the loading region 1000 and the quantum region 1002 of the chip, the RF amplitude sensor 1004 as described above, and a bank 1006 of onboard RF shunt capacitors, which are integrated directly on the chip. Wirebond blocks 1008 for input and output are also shown. Also indicated on the figure is a possible position 1010, near the periphery of the chip, for the temperature-sensing wire and for a resistive heating wire.