GUARANTEED BANDWIDTH FOR SEGMENT ROUTED (SR) PATHS

Abstract

At least one bandwidth-guaranteed segment routing (SR) path through a network is determined by: (a) receiving, as input, a bandwidth demand value; (b) obtaining network information; (c) determining a constrained shortest multipath (CSG.sub.i); (d) determining a set of SR segment-list(s) (S.sub.i=[sl.sub.1.sup.i, sl.sub.2.sup.i . . . sl.sub.n.sup.i]) a that are needed to steer traffic over CSG.sub.i; and (e) tuning the loadshares in L.sub.i, using S.sub.i and the per segment-list loadshare (L.sub.i=[l.sub.1.sup.i, l.sub.2.sup.i . . . l.sub.n.sup.i]), the per segment equal cost multipath (ECMP), and the per link residual capacity, such that the bandwidth capacity that can be carried over CSG.sub.i is maximized.

Claims

1. A computer-implemented method for determining at least one bandwidth-guaranteed segment routing (SR) path through a network, the computer-implemented method comprising: a) receiving, as input, a bandwidth demand value; b) obtaining network information; c) determining a constrained shortest multipath (CSG.sub.i); d) determining a set of SR segment-list(s) (S.sub.i=[sl.sub.1.sup.i, sl.sub.2.sup.i . . . sl.sub.n.sup.i]) that are needed to steer traffic over CSG.sub.i; and e) tuning the loadshares in L.sub.i, using S.sub.i and the per segment-list loadshare (L.sub.i=[l.sub.1.sup.i, l.sub.2.sup.i . . . l.sub.n.sup.i]), the per segment equal cost multipath (ECMP), and the per link residual capacity, such that the bandwidth capacity that can be carried over CSG.sub.i is maximized.

2. The computer-implemented method of claim 1 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric.

3. The computer-implemented method of claim 1 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric after excluding link(s) due to any topological constraints.

4. The computer-implemented method of claim 1 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric after pruning out zero residual bandwidth links.

5. The computer-implemented method of claim 1 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric.

6. The computer-implemented method of claim 1 wherein the act of obtaining network information is performed by accessing information in a traffic engineering database (TED), the computer-implemented method further comprising: f) updating the TED or a workspace including information from the TED, to deduct bandwidth capacity used on CSG.sub.i.

7. The computer-implemented method of claim 6 further comprising: g) determining whether or not the (remaining) bandwidth demand can be satisfied by CSG.sub.i; and h) responsive to a determination that the capacity of CSG.sub.i is smaller than the (remaining) demand, repeating acts (a)-(e).

8. The computer-implemented method of claim 1 wherein the act of tuning the loadshares in L.sub.i, using S.sub.i and the per segment-list loadshare (L.sub.i=[l.sub.1.sup.i, l.sub.2.sup.i . . . l.sub.n.sup.i]), the per segment equal cost multipath (ECMP), and the per link residual capacity, such that the bandwidth capacity that can be carried over CSG.sub.i is maximized, uses a sequential least squares programming procedure.

9. A router serving as an ingress of a SR path and comprising: a) at least one routing processor; and b) a non-transitory computer readable medium storing processor executable instructions which, when executed by the at least one routing processor, cause the at least one routing processor to determine at least one bandwidth-guaranteed segment routing (SR) path through a network, by performing a method comprising: a) receiving, as input, a bandwidth demand value; b) obtaining network information; c) determining a constrained shortest multipath (CSG.sub.i); d) determining a set of SR segment-list(s) (S.sub.i=[sl.sub.1.sup.i, sl.sub.2.sup.i . . . sl.sub.n.sup.i]) that are needed to steer traffic over CSG.sub.i; and e) tuning the loadshares in L.sub.i, using S.sub.i and the per segment-list loadshare (L.sub.i=[l.sub.1.sup.i, l.sub.2.sup.i . . . l.sub.n.sup.i]), the per segment equal cost multipath (ECMP), and the per link residual capacity, such that the bandwidth capacity that can be carried over CSG.sub.i is maximized.

10. The router of claim 9 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric.

11. The router of claim 9 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric after excluding link(s) due to any topological constraints.

12. The router of claim 9 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric after pruning out zero residual bandwidth links.

13. The router of claim 9 wherein the CSG.sub.i is formed of paths of equal cost of minimum accumulative path metric.

14. The router of claim 9 wherein the act of obtaining network information is performed by accessing information in a traffic engineering database (TED), the method further comprising: f) updating the TED or a workspace including information from the TED, to deduct bandwidth capacity used on CSG.sub.i.

15. The router of claim 14 wherein the method further comprises: g) determining whether or not the (remaining) bandwidth demand can be satisfied by CSG.sub.i; and h) responsive to a determination that the capacity of CSG.sub.i is smaller than the (remaining) demand, repeating acts (a)-(e).

16. The router of claim 9 wherein the act of tuning the loadshares in L.sub.i, using S.sub.i and the per segment-list loadshare (L.sub.i=[l.sub.1.sup.i, l.sub.2.sup.i . . . l.sub.n.sup.i]), the per segment equal cost multipath (ECMP), and the per link residual capacity, such that the bandwidth capacity that can be carried over CSG.sub.i is maximized, uses a sequential least squares programming procedure.

17. A server in communication with a router serving as an ingress of a SR path, the server comprising: a) at least one path computation element (PCE); and b) a non-transitory computer readable medium storing processor executable instructions which, when executed by the at least one PCE, cause the at least one PCE to determine at least one bandwidth-guaranteed segment routing (SR) path through a network, by performing a method comprising: a) receiving, as input, a bandwidth demand value; b) obtaining network information; c) determining a constrained shortest multipath (CSG.sub.i); d) determining a set of SR segment-list(s) (S.sub.i=[sl.sub.1.sup.i, sl.sub.2.sup.i . . . sl.sub.n.sup.i]) that are needed to steer traffic over CSG.sub.i; and e) tuning the loadshares in L.sub.i, using S.sub.i and the per segment-list loadshare (L.sub.i=[l.sub.1.sup.i, l.sub.2.sup.i . . . l.sub.n.sup.i]), the per segment equal cost multipath (ECMP), and the per link residual capacity, such that the bandwidth capacity that can be carried over CSG.sub.i is maximized.

Description

4.2.1 EXAMPLES OF OPERATIONS OF EXAMPLE METHODS

4.2.1.1 First Example

[0086] Referring to FIG. 8, consider the following incoming traffic demand D=12 U from H destined to T. In the first iteration, H runs the example method 700 to find CSG.sub.1 and succeeds to steer 10U over CSG.sub.1:

[00003]${\mathrm{CSG}}_1.Math.\{\begin{array}{c}\mathrm{Cost}.Math..Math.c_1=.Math.30\\ \mathrm{Capacity}.Math..Math.X_1=10.Math.U\\ S_1=\left[{\mathrm{sl}}_1^1,.Math.{\mathrm{sl}}_2^1.Math..Math.\mathrm{.Math.}.Math..Math.{\mathrm{sl}}_n^1\right]\\ L_1=\left[l_1^1,.Math.l_2^1,\mathrm{.Math.}.Math..Math.l_n^1\right]\end{array}$

[0087] Since, however the bandwidth demand is not yet satisfied (Recall, e.g., 780, NO) (10 U<12 U), the method 700 performs a second iteration. In the second iteration, H runs the example method 700 to find CSPG.sub.2 and consequently steer the remainder 2 U over CSG.sub.2:

[00004]${\mathrm{CSG}}_2.Math.\{\begin{array}{c}\mathrm{Cost}.Math..Math.c_2=.Math.40\\ \mathrm{Capacity}.Math..Math.X_2=10.Math.U\\ S_2=\left[{\mathrm{sl}}_1^2,.Math.{\mathrm{sl}}_2^2.Math..Math.\mathrm{.Math.}.Math..Math.{\mathrm{sl}}_n^2\right]\\ L_2=\left[l_1^2,.Math.l_2^2,\mathrm{.Math.}.Math..Math.l_n^2\right]\end{array}$

H updates the weight distribution as:

[0088] WL, where W=[w1, w2] and w1=10/12 and w2=2/12 and L=[L.sub.1, L.sub.2] and S=[S.sub.1, S.sub.2] describe the set of segment-list(s) found for each iteration.

4.2.1.2 Second Example

[0089] FIG. 9A depicts an example network topology. The residual bandwidth (e.g., available from TED or a workspace) of each link is marked. For example, the link connecting node (R1) with node (R2), and the link connecting node(R1) to node(R3) have residual bandwidths of 3 units, and 4 units respectively.

[0090] The example method 700 is performed to determine the maximum capacity X that node (R1) can send to node (R8) over the most optimal path(s). The steps involved include:

TABLE-US-00001 STEP DESCRIPTION 1 Compute CSG.sub.1 (Recall 740 of FIG. 7.) 2 Determine S1, the set of segment-list(s) to steer traffic over CSG.sub.1 (Recall 750 of FIG. 7.): sl.sub.1.sup.1 = {node-SID(6), node-SID(8)} sl.sub.2.sup.1 = {node-SID(2), node-SID(5), node-SID(8)} and, S.sub.1 = {sl.sub.1.sup.1, sl.sub.2.sup.1} L.sub.1 = {l.sub.1, l.sub.2} 3 Formulate the set of constraint equalities and inequalities 4 Solve the optimization problem to maximize the capacity of CSG.sub.1 and find: L, and W (Recall 760 of FIG. 7.)

[0091] The set of constraints equations can be derived as:

[00005]$\begin{array}{cc}{e}_{1.Math.2}.fwdarw.\frac{l_2.Math.x}{3}+l_1.Math.x3& \left(1\right)\\ e_{1.Math.3}.fwdarw.\frac{l_2.Math.x}{3}4& \left(2\right)\\ e_{1.Math.4}.fwdarw.\frac{l_2.Math.x}{3}5& \left(3\right)\\ e_{2.Math.5}.fwdarw.l_1.Math.x3& \left(4\right)\\ e_{2.Math.6}.fwdarw.\frac{l_2.Math.x}{3}6& \left(5\right)\\ e_{3.Math.6}.fwdarw.\frac{l_2.Math.x}{3}3& \left(6\right)\\ e_{4.Math.6}.fwdarw.\frac{l_2.Math.x}{3}6& \left(7\right)\\ e_{5.Math.8}.fwdarw.l_1.Math.x6& \left(8\right)\\ e_{6.Math.8}.fwdarw.l_2.Math.x4& \left(9\right)\end{array}$

[0092] Where e.sub.xy is the unidirectional edge (or link) connecting node(x) to node(y). Inequalities (1)-(3) are derived from the three (3) links exiting node R1. The denominator 3 indicates ECMP over the three links. Inequalities (5)-(7) are derived from the three (3) links entering node R6. Again, the denominator 3 indicates ECMP over the three links.

[0093] The inequalities or equations above can be simplified further to:

l.sub.1+l.sub.2=1 (10)

l.sub.1x3 (11)

l.sub.2x<4 (12)

l.sub.2x+3l.sub.1x9 (13)

[0094] Equation (10) is derived from the fact that the sum of the loads is always 1. Inequality (11) corresponds to inequality (6), and inequality (12) corresponds to inequality (9). Inequality (13) is derived from inequality (1). Expressions (10)-(14) can be programmatically solved (e.g., using non-linear programming such as Sequential Least SQuares Programming (SLSQP)). The example below uses python. ($python compute_cap_weigths.py). In the example of FIGS. 9A-9C, the following values are generated:

Capacity (X)=6.333333327495734

l.sub.2=0.7894736842874963

l.sub.1=0.21052631571250358

[0095] That is, in this example, the maximum capacity is 6.333333327495734 units, the first segment-list (e.g., the left side of FIG. 9C) receives about 79% of the traffic, while the second segment-list (e.g., the right side of FIG. 9C) receives about 21% of the traffic.

4.3 EXAMPLE ARCHITECTURES AND APPARATUS

[0096] The nodes may be forwarding devices such as routers for example. FIG. 10 illustrates two data forwarding systems 1010 and 1020 coupled via communications links 1030. The links may be physical links or wireless links. The data forwarding systems 1010,1020 may be routers for example. If the data forwarding systems 1010,1020 are example routers, each may include a control component (e.g., a routing engine) 1014,1024 and a forwarding component 1012,1022. Each data forwarding system 1010,1020 includes one or more interfaces 1016,1026 that terminate one or more communications links 1030.

[0097] As just discussed above, and referring to FIG. 11, some example routers 1100 include a control component (e.g., routing engine) 1110 and a packet forwarding component (e.g., a packet forwarding engine) 1190.

[0098] The control component 1110 may include an operating system (OS) kernel 1120, routing protocol process(es) 1130, label-based forwarding protocol process(es) 1140, interface process(es) 1150, user interface (e.g., command line interface) process(es) 1160, and chassis process(es) 1170, and may store routing table(s) 1139, label forwarding information 1145, and forwarding (e.g., route-based and/or label-based) table(s) 1180. As shown, the routing protocol process(es) 1130 may support routing protocols such as the routing information protocol (RIP) 1131, the intermediate system-to-intermediate system protocol (IS-IS) 1132, the open shortest path first protocol (OSPF) 1133, the enhanced interior gateway routing protocol (EIGRP) 1134 and the boarder gateway protocol (BGP) 1135, and the label-based forwarding protocol process(es) 1140 may support protocols such as BGP 1135, the label distribution protocol (LDP) 1136 and the resource reservation protocol (RSVP) 1137. One or more components (not shown) may permit a user 1165 to interact with the user interface process(es) 1160. Similarly, one or more components (not shown) may permit an outside device to interact with one or more of the router protocol process(es) 1130, the label-based forwarding protocol process(es) 1140, the interface process(es) 1150, and the chassis process(es) 1170, via SNMP 1185, and such processes may send information to an outside device via SNMP 1185. Example embodiments consistent with the present description may be implemented in one or more routing protocol processes 1130.

[0099] The packet forwarding component 1190 may include a microkernel 1192, interface process(es) 1193, distributed ASICs 1194, chassis process(es) 1195 and forwarding (e.g., route-based and/or label-based) table(s) 1196.

[0100] In the example router 1100 of FIG. 11, the control component 1110 handles tasks such as performing routing protocols, performing label-based forwarding protocols, control packet processing, etc., which frees the packet forwarding component 1190 to forward received packets quickly. That is, received control packets (e.g., routing protocol packets and/or label-based forwarding protocol packets) are not fully processed on the packet forwarding component 1190 itself, but are passed to the control component 1110, thereby reducing the amount of work that the packet forwarding component 1190 has to do and freeing it to process packets to be forwarded efficiently. Thus, the control component 1110 is primarily responsible for running routing protocols and/or label-based forwarding protocols, maintaining the routing tables and/or label forwarding information, sending forwarding table updates to the packet forwarding component 1190, and performing system management. The example control component 1110 may handle routing protocol packets, provide a management interface, provide configuration management, perform accounting, and provide alarms. The processes 1130, 1140, 1150, 1160 and 1170 may be modular, and may interact with the OS kernel 1120. That is, nearly all of the processes communicate directly with the OS kernel 1120. Using modular software that cleanly separates processes from each other isolates problems of a given process so that such problems do not impact other processes that may be running. Additionally, using modular software facilitates easier scaling.

[0101] Still referring to FIG. 11, the example OS kernel 1120 may incorporate an application programming interface (API) system for external program calls and scripting capabilities. The control component 1110 may be based on an Intel PCI platform running the OS from flash memory, with an alternate copy stored on the router's hard disk. The OS kernel 1120 is layered on the Intel PCI platform and establishes communication between the Intel PCI platform and processes of the control component 1110. The OS kernel 1120 also ensures that the forwarding tables 1196 in use by the packet forwarding component 1190 are in sync with those 1180 in the control component 1110. Thus, in addition to providing the underlying infrastructure to control component 1110 software processes, the OS kernel 1120 also provides a link between the control component 1110 and the packet forwarding component 1190.

[0102] Referring to the routing protocol process(es) 1130 of FIG. 11, this process(es) 1130 provides routing and routing control functions within the platform. In this example, the RIP 1131, ISIS 1132, OSPF 1133 and EIGRP 1134 (and BGP 1135) protocols are provided. Naturally, other routing protocols may be provided in addition, or alternatively. Similarly, the label-based forwarding protocol process(es) 1140 provides label forwarding and label control functions. In this example, the LDP 1136 and RSVP 1137 (and BGP 1135) protocols are provided. Naturally, other label-based forwarding protocols (e.g., MPLS, SR, etc.) may be provided in addition, or alternatively. In the example router 1100, the routing table(s) 1139 is produced by the routing protocol process(es) 1130, while the label forwarding information 1145 is produced by the label-based forwarding protocol process(es) 1140.

[0103] Still referring to FIG. 11, the interface process(es) 1150 performs configuration of the physical interfaces (Recall, e.g., 1016 and 926 of FIG. 10.) and encapsulation.

[0104] The example control component 1110 may provide several ways to manage the router. For example, it 1110 may provide a user interface process(es) 1160 which allows a system operator 1165 to interact with the system through configuration, modifications, and monitoring. The SNMP 1185 allows SNMP-capable systems to communicate with the router platform. This also allows the platform to provide necessary SNMP information to external agents. For example, the SNMP 1185 may permit management of the system from a network management station running software, such as Hewlett-Packard's Network Node Manager (HP-NNM), through a framework, such as Hewlett-Packard's OpenView. Accounting of packets (generally referred to as traffic statistics) may be performed by the control component 1110, thereby avoiding slowing traffic forwarding by the packet forwarding component 1190.

[0105] Although not shown, the example router 1100 may provide for out-of-band management, RS-232 DB9 ports for serial console and remote management access, and tertiary storage using a removable PC card. Further, although not shown, a craft interface positioned on the front of the chassis provides an external view into the internal workings of the router. It can be used as a troubleshooting tool, a monitoring tool, or both. The craft interface may include LED indicators, alarm indicators, control component ports, and/or a display screen. Finally, the craft interface may provide interaction with a command line interface (CLI) 1160 via a console port, an auxiliary port, and/or a management Ethernet port

[0106] The packet forwarding component 1190 is responsible for properly outputting received packets as quickly as possible. If there is no entry in the forwarding table for a given destination or a given label and the packet forwarding component 1190 cannot perform forwarding by itself, it 1190 may send the packets bound for that unknown destination off to the control component 1110 for processing. The example packet forwarding component 1190 is designed to perform Layer 2 and Layer 3 switching, route lookups, and rapid packet forwarding.

[0107] As shown in FIG. 11, the example packet forwarding component 1190 has an embedded microkernel 1192, interface process(es) 1193, distributed ASICs 1194, and chassis process(es) 1195, and stores a forwarding (e.g., route-based and/or label-based) table(s) 1196. The microkernel 1192 interacts with the interface process(es) 1193 and the chassis process(es) 1195 to monitor and control these functions. The interface process(es) 1192 has direct communication with the OS kernel 1120 of the control component 1110. This communication includes forwarding exception packets and control packets to the control component 1110, receiving packets to be forwarded, receiving forwarding table updates, providing information about the health of the packet forwarding component 1190 to the control component 1110, and permitting configuration of the interfaces from the user interface (e.g., CLI) process(es) 1160 of the control component 1110. The stored forwarding table(s) 1196 is static until a new one is received from the control component 1110. The interface process(es) 1193 uses the forwarding table(s) 1196 to look up next-hop information. The interface process(es) 1193 also has direct communication with the distributed ASICs 1194. Finally, the chassis process(es) 1195 may communicate directly with the microkernel 1192 and with the distributed ASICs 1194.

[0108] Referring back to distributed ASICs 1194 of FIG. 11, FIG. 12 is an example of how the ASICS may be distributed in the packet forwarding component 1190 to divide the responsibility of packet forwarding. As shown in FIG. 12, the ASICs of the packet forwarding component 1190 may be distributed on physical interface cards (PICs) 1210, flexible PIC concentrators (FPCs) 1220, a midplane or backplane 1230, and a system control board(s) 1240 (for switching and/or forwarding). Switching fabric is also shown as a system switch board (SSB), or a switching and forwarding module (SFM) 1250. Each of the PICs 1210 includes one or more PIC I/O managers 1215. Each of the FPCs 1220 includes one or more I/O managers 1222, each with an associated memory 1224. The midplane/backplane 1230 includes buffer managers 1235a, 1235b. Finally, the system control board 1240 includes an internet processor 1242 and an instance of the forwarding table 1244 (Recall, e.g., 1196 of FIG. 11).

[0109] Still referring to FIG. 12, the PICs 1210 contain the interface ports. Each PIC 1210 may be plugged into an FPC 1220. Each individual PIC 1210 may contain an ASIC that handles media-specific functions, such as framing or encapsulation. Some example PICs 1210 provide SDH/SONET, ATM, Gigabit Ethernet, Fast Ethernet, and/or DS3/E3 interface ports.

[0110] An FPC 1220 can contain from one or more PICs 1210, and may carry the signals from the PICs 1210 to the midplane/backplane 1230 as shown in FIG. 12.

[0111] The midplane/backplane 1230 holds the line cards. The line cards may connect into the midplane/backplane 1230 when inserted into the example router's chassis from the front. The control component (e.g., routing engine) 1110 may plug into the rear of the midplane/backplane 1230 from the rear of the chassis. The midplane/backplane 1230 may carry electrical (or optical) signals and power to each line card and to the control component 1110.

[0112] The system control board 1240 may perform forwarding lookup. It 1240 may also communicate errors to the routing engine. Further, it 1240 may also monitor the condition of the router based on information it receives from sensors. If an abnormal condition is detected, the system control board 1240 may immediately notify the control component 1110.

[0113] Referring to FIGS. 12, 13A and 13B, in some exemplary routers, each of the PICs 1210,1110 contains at least one I/O manager ASIC 1215 responsible for media-specific tasks, such as encapsulation. The packets pass through these I/O ASICs on their way into and out of the router. The I/O manager ASIC 1215 on the PIC 1210,1110 is responsible for managing the connection to the I/O manager ASIC 1222 on the FPC 1220,1120, managing link-layer framing and creating the bit stream, performing cyclical redundancy checks (CRCs), and detecting link-layer errors and generating alarms, when appropriate. The FPC 1220 includes another I/O manager ASIC 1222. This ASIC 1222 takes the packets from the PICs 1210 and breaks them into (e.g., 74-byte) memory blocks. This FPC I/O manager ASIC 1222 sends the blocks to a first distributed buffer manager (DBM) 1235a, decoding encapsulation and protocol-specific information, counting packets and bytes for each logical circuit, verifying packet integrity, and applying class of service (CoS) rules to packets. At this point, the packet is first written to memory. More specifically, the example DBM ASIC 1235a manages and writes packets to the shared memory 1224 across all FPCs 1220. In parallel, the first DBM ASIC 1235a also extracts information on the destination of the packet and passes this forwarding-related information to the Internet processor 1242/1142. The Internet processor 1242/1142 performs the route lookup using the forwarding table 1244 and sends the information over to a second DBM ASIC 1235b. The Internet processor ASIC 1242/1142 also collects exception packets (i.e., those without a forwarding table entry) and sends them to the control component 1110. The second DBM ASIC 1235b then takes this information and the 74-byte blocks and forwards them to the I/O manager ASIC 1222 of the egress FPC 1220/1120 (or multiple egress FPCs, in the case of multicast) for reassembly. (Thus, the DBM ASICs 1235a and 1235b are responsible for managing the packet memory 1224 distributed across all FPCs 1220/1120, extracting forwarding-related information from packets, and instructing the FPC where to forward packets.)

[0114] The I/O manager ASIC 1222 on the egress FPC 1220/1120 may perform some value-added services. In addition to incrementing time to live (TTL) values and re-encapsulating the packet for handling by the PIC 1210, it can also apply class-of-service (CoS) rules. To do this, it may queue a pointer to the packet in one of the available queues, each having a share of link bandwidth, before applying the rules to the packet. Queuing can be based on various rules. Thus, the I/O manager ASIC 1222 on the egress FPC 1220/1120 may be responsible for receiving the blocks from the second DBM ASIC 1235b, incrementing TTL values, queuing a pointer to the packet, if necessary, before applying CoS rules, re-encapsulating the blocks, and sending the encapsulated packets to the PIC I/O manager ASIC 1215.

[0115] FIG. 14 is a flow diagram of an example method 1400 for providing packet forwarding in the example router. The main acts of the method 1400 are triggered when a packet is received on an ingress (incoming) port or interface. (Event 1410) The types of checksum and frame checks that are required by the type of medium it serves are performed and the packet is output, as a serial bit stream. (Block 1420) The packet is then decapsulated and parsed into (e.g., 64-byte) blocks. (Block 1430) The packets are written to buffer memory and the forwarding information is passed on the Internet processor. (Block 1440) The passed forwarding information is then used to lookup a route in the forwarding table. (Block 1450) Note that the forwarding table can typically handle unicast packets that do not have options (e.g., accounting) set, and multicast packets for which it already has a cached entry. Thus, if it is determined that these conditions are met (YES branch of Decision 1460), the packet forwarding component finds the next hop and egress interface, and the packet is forwarded (or queued for forwarding) to the next hop via the egress interface (Block 1470) before the method 1400 is left (Node 1490) Otherwise, if these conditions are not met (NO branch of Decision 1460), the forwarding information is sent to the control component 1110 for advanced forwarding resolution (Block 1480) before the method 1400 is left (Node 1490).

[0116] Referring back to block 1470, the packet may be queued. Actually, as stated earlier with reference to FIG. 12, a pointer to the packet may be queued. The packet itself may remain in the shared memory. Thus, all queuing decisions and CoS rules may be applied in the absence of the actual packet. When the pointer for the packet reaches the front of the line, the I/O manager ASIC 1222 may send a request for the packet to the second DBM ASIC 1235b. The DBM ASIC 1235 reads the blocks from shared memory and sends them to the I/O manager ASIC 1222 on the FPC 1220, which then serializes the bits and sends them to the media-specific ASIC of the egress interface. The I/O manager ASIC 1215 on the egress PIC 1210 may apply the physical-layer framing, perform the CRC, and send the bit stream out over the link.

[0117] Referring back to block 1480 of FIG. 14, as well as FIG. 12, regarding the transfer of control and exception packets, the system control board 1240 handles nearly all exception packets. For example, the system control board 1240 may pass exception packets to the control component 1110.

[0118] Although example embodiments consistent with the present invention may be implemented on the example routers of FIG. 10 or 11, embodiments consistent with the present invention may be implemented on communications network nodes (e.g., routers, switches, etc.) having different architectures, or even a remote server (e.g., a path computation element (PCE)). More generally, embodiments consistent with the present invention may be implemented on an example system 1400 as illustrated on FIG. 15.

[0119] FIG. 15 is a block diagram of an exemplary machine 1500 that may perform one or more of the processes described, and/or store information used and/or generated by such processes. The exemplary machine 1500 includes one or more processors 1510, one or more input/output interface units 1530, one or more storage devices 1520, and one or more system buses and/or networks 1540 for facilitating the communication of information among the coupled elements. One or more input devices 1532 and one or more output devices 1534 may be coupled with the one or more input/output interfaces 1530. The one or more processors 1510 may execute machine-executable instructions (e.g., C or C++ running on the Linux operating system widely available from a number of vendors such as Red Hat, Inc. of Durham, N.C.) to effect one or more aspects of the present invention. At least a portion of the machine executable instructions may be stored (temporarily or more permanently) on the one or more storage devices 1520 and/or may be received from an external source via one or more input interface units 1530. The machine executable instructions may be stored as various software modules, each module performing one or more operations. Functional software modules are examples of components of the invention.

[0120] In some embodiments consistent with the present invention, the processors 1510 may be one or more microprocessors and/or ASICs. The bus 1540 may include a system bus. The storage devices 1520 may include system memory, such as read only memory (ROM) and/or random access memory (RAM). The storage devices 1520 may also include a hard disk drive for reading from and writing to a hard disk, a magnetic disk drive for reading from or writing to a (e.g., removable) magnetic disk, an optical disk drive for reading from or writing to a removable (magneto-) optical disk such as a compact disk or other (magneto-) optical media, or solid-state non-volatile storage.

[0121] Some example embodiments consistent with the present invention may also be provided as a machine-readable medium for storing the machine-executable instructions. The machine-readable medium may be non-transitory and may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards or any other type of machine-readable media suitable for storing electronic instructions. For example, example embodiments consistent with the present invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of a communication link (e.g., a modem or network connection) and stored on a non-transitory storage medium. The machine-readable medium may also be referred to as a processor-readable medium.

[0122] Example embodiments consistent with the present invention (or components or modules thereof) might be implemented in hardware, such as one or more field programmable gate arrays (FPGAs), one or more integrated circuits such as ASICs, one or more network processors, etc.

[0123] Alternatively, or in addition, embodiments consistent with the present invention (or components or modules thereof) might be implemented as stored program instructions executed by a processor. Such hardware and/or software might be provided in an addressed data (e.g., packet, cell, etc.) forwarding device (e.g., a switch, a router, etc.), a laptop computer, desktop computer, a tablet computer, a mobile phone, or any device that has computing and networking capabilities.

4.4 Refinements, Alternatives and Extensions

[0124] Referring back to block 750 of FIG. 7, the set of SR segment list(s) need to steer traffic over the i.sup.th CSG may be determined using the technique illustrated in FIGS. 16 and 17. Block reference numbers used in the flow diagram of FIG. 17 are annotated onto the pseudo code of FIG. 16.

[0125] Referring back to block 760 of FIG. 7, the loadshares may be tuned to maximize the bandwidth capacity that may be carried over the i.sup.th CSG is a non-linear programming problem that may be solved using Sequential Least SQuares Programming (SLSQP).

[0126] FIGS. 18-20 illustrate different architectures that may be used to implement an example method consistent with the present description. More specifically, FIG. 18 illustrates a centralized architecture in which a centralized controller includes a path computation element (PCE), a resource manager (RM) and a BGP route reflector (RR). The PCE can communicate with the RM and the BGP RR using, for example, Google's open source remote procedure call (gRPC) and/or the PCE protocol (PCEP). The PCE includes a segment routing (SR) bandwidth (BW) path computation engine which uses and/or generates information in a traffic engineering database (TED) and a label switched path (LSP) database. The RM includes a link CAC (Call Admission Control, for performing admission control on the link(s) that constitute the SR Path) database. More specifically, the RM includes a link database of SR link(s) in the network and where the SR path reservation(s) and admission is performed and maintained on the traversed link(s). The BGP RR may store BGP link state information. As shown, R1 in domain 1 can communicate with the PCE using, for example, PCEP. Local state information, such as link capacity, link utilization, and per SID traffic rates can be communicated from each of the domains to the RM. This may be done using, for example, BGP-LS, Telemetry, and/or SNMP. Further, information can be exchanged between each of the domains and the BGP RR using, for example, BGP-LS.

[0127] FIG. 19 illustrates an architecture using distributed computation and distributed CAC. In this example, the centralized node includes a central instance of the RM and the BGP RR. As shown, domain 1 includes the PCE and local RM with a local instance of the CAC, while domain 2 includes a local RM with a local instance of the CAC. The SR BW path computation module may communicate with the BGP RR using, for example, BGP-LS. The local instances of the RM may communicate with the centralized RM using, for example, gRPC, PCEP, and/or BGP. Finally, local state information, such as link capacity, link utilization, and per SID traffic rates can be communicated from each of the domains to the BGP-RR. This may be done using, for example, BGP-LS.

[0128] Finally, FIG. 20 illustrates an architecture using distributed computation and a centralized CAC. In this example, the centralized node includes the RM and the BGP RR. As shown, domain 1 includes the PCE. The SR BW path computation module may communicate with the BGP RR using, for example, BGP-LS. The SR BW path computation module may communicate with the RM to request certain allocations, and receive a response to its request(s). Local state information, such as link capacity, link utilization, and per SID traffic rates can be communicated from each of the domains to the BGP-RR. This may be done using, for example, BGP-LS.

4.5 CONCLUSIONS

[0129] Example embodiments consistent with the present description allows the setup of SR path(s) with bandwidth guarantees in SR network.

[0130] Example embodiments consistent with the present description are applicable to SRv6 and SR-MPLS dataplane technologies.

[0131] Example embodiments consistent with the present description enable auto-bandwidth to work for SR Path(s).

[0132] Example embodiments consistent with the present description can work on a central computation server, where per path reservations are managed centrally.

[0133] Example embodiments consistent with the present description are compatible with RSVP-TE LSP and bandwidth reservations in the same network.