Ultrawideband very low noise amplifier with noise reduction and current reuse

Abstract

A novel and useful noise reduction technique that improves the noise figure (NF) of a common-source (CS) low noise amplifier (LNA). The technique exploits dc current reuse and increases transconductance of the CS transistor while maintaining its power consumption. By using noise reduction and dc current reuse techniques, the thermal current noise of the noise cancellation stage is reduced without adding any extra branch to the circuit. As a result, the current thermal noise of second stage decreases dramatically leading to better NF without consuming any extra power. Moreover, since the circuit block is implemented using a pMOS transistor, the second order nonlinearity of pMOS and nMOS transistors cancel each other, resulting in improved nonlinearity performance of the LNA, including improvements to both IIP2 and IIP3.

Claims

1. A low noise amplifier (LNA) circuit, comprising: an input node for receiving an input signal; an input matching stage coupled to said input node and operative to provide wideband input matching; a noise cancellation stage coupled to said input matching stage and operative to substantially cancel thermal current noise generated by said input matching stage and to generate an output signal thereby; and a noise reduction stage coupled to said input matching stage and in parallel with said noise cancellation stage in ac mode, said noise reduction stage operative to reduce thermal current noise of said noise cancellation stage by boosting transconductance of said noise cancellation stage and hence reducing its thermal noise effects.

2. The circuit according to claim 1, further comprising a g.sub.m boosting stage coupled to said input matching stage.

3. The circuit according to claim 1, wherein said noise reduction stage comprises a pMOS transistor.

4. The circuit according to claim 1, wherein said noise cancellation stage comprises a common source amplifier transistor.

5. The circuit according to claim 1, wherein said noise cancellation stage and said noise reduction stage are operative to utilize dc current reuse resulting in ac paralleling of a noise reduction stage transistor with a noise canceling stage transistor thereby summing their transconductances and reducing thermal noise without required additional power consumption.

6. The circuit according to claim 1, wherein said noise cancellation stage comprises a pMOS-nMOS structure with sweet spot biasing applied to improve linearity.

7. The circuit according to claim 1, wherein said noise cancellation stage is operative to generate two in phase signal currents which are summed to generate an amplified output signal whereby two out of phase noise currents are canceled.

8. A noise reduction method for use in a low noise amplifier (LNA), the method comprising: receiving an input signal at an input node; wideband matching the input signal utilizing an input matching stage; canceling thermal current noise generated by said input matching stage utilizing a noise cancellation stage and generating an output signal therefrom; and reducing thermal current noise generated by said noise cancellation stage utilizing a noise reduction stage configured in parallel to said noise cancellation stage in ac mode whereby thermal current noise is reduced by boosting transconductance of said noise cancellation stage and hence reducing its thermal noise effects.

9. The method according to claim 8, further comprising using dc current reuse in said noise cancellation stage resulting in ac paralleling of a noise reduction stage transistor with a noise canceling stage transistor thereby summing their transconductances and reducing thermal noise.

10. The method according to claim 8, wherein said noise cancellation stage is operative to generate two in phase signal currents which are summed to generate an amplified output signal whereby two out of phase noise currents are canceled.

11. A low noise amplifier (LNA) circuit, comprising: an input node for receiving an input signal; an input matching stage coupled to said input node and operative to provide wideband input matching; a first noise cancellation stage coupled to said input matching stage and operative to substantially cancel thermal current noise generated by said input matching stage; and a second noise cancellation stage coupled to said first noise cancellation stage and operative to substantially cancel thermal current noise generated by said first noise cancellation stage and to generate an output signal thereby.

12. The circuit according to claim 11, further comprising a common mode feedback stage coupled to said input matching stage.

13. The circuit according to claim 11, wherein said input matching stage comprises a common gate transistor structure.

14. The circuit according to claim 11, wherein said first noise cancellation stage comprises first and second transistors having a common source topology.

15. The circuit according to claim 11, wherein said second noise cancellation stage comprises first and second transistors having a common source/source follower topology operative to cancel the channel thermal noise of said first noise cancellation stage.

16. The circuit according to claim 11, wherein said first and second noise cancellation stages comprise a pMOS-nMOS transistor structure.

17. The method according to claim 8, wherein said noise cancellation stage comprises a pMOS-nMOS structure with sweet spot biasing applied to improve linearity.

18. The method according to claim 8, wherein said noise cancellation stage comprises a common source amplifier transistor.

19. The method according to claim 8, wherein canceling thermal current noise comprises generating two in phase signal currents which are summed to generate an amplified output signal whereby two out of phase noise currents are canceled.

20. The method according to claim 8, wherein said noise reduction stage comprises a pMOS transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

(2) FIG. 1A is a schematic diagram illustrating an example prior art common gate wideband matching technique;

(3) FIG. 1B is a schematic diagram illustrating an example prior art shunt feedback common source wideband matching technique;

(4) FIG. 2 is a schematic diagram illustrating an example conventional noise cancellation technique;

(5) FIG. 3 is a schematic diagram illustrating an example noise reduction technique;

(6) FIG. 4 is a graph illustrating a comparison of noise figure (NF) of a shunt feedback common source amplifier with and without the noise reduction technique;

(7) FIG. 5 is a schematic diagram illustrating an example noise cancellation and reduction technique;

(8) FIG. 6 is a schematic diagram illustrating an example wideband noise cancelling low noise amplifier (LNA);

(9) FIG. 7 is a schematic diagram illustrating an example wideband noise cancelling low noise amplifier (LNA) incorporating noise cancellation and reduction techniques;

(10) FIG. 8 is a diagram illustrating the percentage of noise sources for common gate structure, LNA without noise reduction, and LNA with noise reduction;

(11) FIG. 9 is a graph illustrating second order nonlinear component of pMOS and nMOS transistors;

(12) FIG. 10 is a graph illustrating second and third order derivatives of the drain source dc current i.sub.ds with response to V.sub.gs;

(13) FIG. 11 is a graph illustrating simulated input return loss;

(14) FIG. 12 is a graph illustrating simulated power gain as a function of frequency;

(15) FIG. 14 is a graph illustrating a full wave simulation of noise figure and power gain as a function of frequency;

(16) FIG. 13 is a graph illustrating simulated noise figure as a function of frequency;

(17) FIG. 15 is a graph illustrating stability of the simulated LNA as a function of frequency;

(18) FIG. 16 is a graph illustrating simulated IIP3 as a function of frequency;

(19) FIG. 17 is a schematic diagram illustrating a two-fold noise cancelling LNA of the present invention; and

(20) FIG. 18 is a graph illustrating simulated power gain, input return loss and noise figure as a function of frequency.

DETAILED DESCRIPTION OF THE INVENTION

(21) To aid in understanding the operation of the noise reduction technique of the present invention, the basic idea of conventional noise cancellation is presented. Then, the noise reduction technique of the present invention is described.

(22) Regarding conventional noise cancellation techniques, the most important noise source in CMOS transistors at radio frequencies is the channel thermal noise. This noise is modeled as a shunt current source between the transistor drain and source terminals. The goal of the designer is to minimize the amount of noise generated within each element to obtain a low NF.

(23) An example conventional noise cancellation scheme is shown in FIG. 2. In operation, the noise current of the main transistor M.sub.1 flows through the feedback resistor R.sub.F to the gate of the matching amplifier and creates two noise voltages with the same phase but different amplitudes in nodes X and Y. On the other hand, the signal voltage at these nodes has opposite phase and different amplitude due to the inverting amplifier. The difference of signal and noise polarities at nodes X and Y results in cancellation of the noise of the matching transistor while adding the signal contributions constructively. The noise voltage in node X, V.sub.nX, is amplified and inverted by M.sub.2 while the noise voltage in node Y, V.sub.nY, passes across M.sub.3 without any change. Then in the output, the two voltages with opposite phases are summed. Therefore, the channel thermal noise of M.sub.1 is canceled at the output provided that the following condition is satisfied:

(24) $\begin{array}{cc}{V}_{n,\mathrm{out}}=V_{\mathrm{nY}}\frac{r_{\mathrm{ds}2}}{r_{\mathrm{ds}2}+1/g_{m2}}-v_{\mathrm{nX}}\frac{g_{m2}}{g_{m3}}=0\frac{R_F+R_s}{R_s}=\frac{g_{m2}}{g_{m3}}& \left(1\right)\end{array}$
where g.sub.mr.sub.ds>>1 is assumed.

(25) As mentioned supra, this kind of noise cancellation is well known and used in numerous LNA structures. The main drawback of this technique, however, is the need for an extra stage in order to amplify and invert the noise voltage in node X and add it to V.sub.nY at the output. According to Equation 1, since the size of the feedback resistor is much larger than the size of the source resistor, R.sub.F>>R.sub.s, the transconductance of M.sub.2, g.sub.m2, must be large enough to provide the noise cancellation condition. As a result, power consumption is increased. To address this, the present invention provides a noise reduction technique which improves the NF without increasing the power consumption.

(26) The main goal of the noise reduction technique of the present invention is to improve the noise performance of the common-source structure without consuming any extra power. This is achieved by using a direct current (dc) current reuse technique. An example noise reduction technique is shown in FIG. 3. In this circuit, generally referenced 40, the noise voltage at node X, V.sub.nX, is amplified, inverted, and added to the noise voltage in node Y, V.sub.nY. In this manner, the adder is not used because the amplified V.sub.nX is sent to the output where the noise voltage V.sub.nY exists. Thus, any extra branch is not used in this technique. This technique can be considered to perform different functions: (1) to reduce the NF or (2) to reduce the power consumption. In the former, the noise figure is improved by the constant power consumption and in the latter the noise figure is considered constant enabling a reduction in power consumption.

(27) These two cases are explained as follows. With reference to FIG. 3, M.sub.1 is the main transistor whose thermal noise should be reduced. M.sub.2 acts as a gain-inverter in order to amplify Via at the output. The gate of these transistors is connected together through C.sub.2. In addition, the source of M.sub.1 is connected to the ground by C.sub.3. The inductor L.sub.1 isolates the drain and source of two transistors. Thus, in dc mode, M.sub.2 is biased by the main transistor current. In ac mode, however, M.sub.2 is paralleled with the main transistor. As mentioned supra, the main noise source in the shunt-feedback amplifier shown in FIG. 1B is the channel thermal noise of M.sub.1 which is calculated as:

(28) $\begin{array}{cc}\begin{array}{c}{F}_{M1}={.Math.\frac{\stackrel{\_}{V_{n,M1}}/A_v}{\stackrel{\_}{V_{n,\mathrm{Rs}}}}.Math.}^2={.Math.\frac{\stackrel{\_}{I_{n,M1}}{Z}_{\mathrm{out}}}{\stackrel{\_}{V_{n,\mathrm{Rs}}}{A}_v}.Math.}^2\\ =\frac{4{\mathrm{kTg}}_{m1}{.Math.Z_{\mathrm{out}}.Math.}^2}{4{\mathrm{kTg}}_{m1}^2{.Math.Z_{\mathrm{out}}.Math.}^2}\frac{}{}=\frac{1}{R_s{g}_{m1}}\frac{}{}.\end{array}& \left(2\right)\end{array}$
where F.sub.M1 is the noise factor due to the channel thermal noise in M.sub.1 and Z.sub.out is the output impedance. In addition, .sub.n,M.sub.1.sup.2=4kTg.sub.m1 is the channel thermal noise of M.sub.1 and A.sub.v=g.sub.m1Z.sub.out. Hence, the noise factor of the shunt-feedback amplifier shown in FIG. 1B is approximately equal to:

(29) $\begin{array}{cc}F1+\frac{1}{g_{m1}{R}_s}\frac{}{}& \left(3\right)\end{array}$

(30) According to Equation 3, the noise factor has a reverse relation with the transconductance. It means that by increasing the transconductance of the main transistor, the circuit's noise figure is decreased. But, this results in more power dissipation. By using the noise reduction technique, the noise factor is roughly equal to: F.sub.1+F.sub.M1+F.sub.M2 where F.sub.M1 and F.sub.M2 are expressed by:

(31) $\begin{array}{cc}\begin{array}{c}{F}_{M1}=\frac{4{\mathrm{kTg}}_{m1}{.Math.Z_{\mathrm{out}}.Math.}^2}{4{{\mathrm{kTR}}_s\left(g_{m1}+g_{m2}\right)}^2{.Math.Z_{\mathrm{out}}.Math.}^2}\frac{}{}\\ =\frac{g_{m1}}{{R_s\left(g_{m1}+g_{m2}\right)}^2}\frac{}{}.\end{array}& \left(4\right)\\ \begin{array}{c}{F}_{M2}=\frac{4{\mathrm{kTg}}_{m2}{.Math.Z_{\mathrm{out}}.Math.}^2}{4{{\mathrm{kTR}}_s\left(g_{m1}+g_{m2}\right)}^2{.Math.Z_{\mathrm{out}}.Math.}^2}\frac{}{}\\ =\frac{g_{m2}}{{R_s\left(g_{m1}+g_{m2}\right)}^2}\frac{}{}.\end{array}& \left(5\right)\end{array}$

(32) Finally, the total noise factor of the circuit, without considering the thermal noise of R.sub.D1, is approximately given by:

(33) $\begin{array}{cc}F1+\frac{}{\left(g_{m1}+g_{m2}\right)R_s}& \left(6\right)\end{array}$

(34) According to Equation 6, by using the noise reduction technique, M.sub.2 is paralleled with the main transistor (i.e. in the small signal or ac model; in the dc mode the two transistors are stacked for current reuse), and hence, its transconductance is added with g.sub.m1. As a result, the transconductance of the main transistor is enhanced. This technique reduces the noise figure without increasing the bias current. If the dc current reuse technique is not used and M.sub.2 is paralleled with M.sub.1, the structure consumes two times more power in order to achieve the same NF. Nonetheless, the main drawback of this technique is the reduced voltage headroom.

(35) The LNA shown in FIG. 3 has been designed and constructed in 28 nm CMOS technology. The performance of the noise reduction technique is illustrated in FIG. 4 as trace 52 and is compared with trace 50 from the shunt feedback amplifier shown in FIG. 1B. In this comparison, it has been considered that both structures consume the same power, and also, the size of M.sub.1 in both structures is the same. As shown in FIG. 4, the structure of the present invention significantly reduces the noise figure. The noise figure variation of the shunt feedback amplifier is between 4.7 to 5.2 dB. By using the noise reduction technique of the present invention, the NF is reduced and it is between 1.6 to 2.1 dB. The power consumption of the circuit of FIG. 3 is the same as the main structure without the noise reduction of FIG. 1B. According to Equation 1, in the conventional noise cancellation, the current of the second stage should be increased in order to satisfy the noise cancellation condition resulting in more power dissipation.

(36) A schematic diagram illustrating an example noise cancellation and reduction technique is shown in FIG. 5. As shown in the circuit, generally referenced 60, when the noise reduction technique is used in the conventional noise cancellation, the transconductance of M.sub.2 is increased without any extra power. As a result, the noise cancellation condition is provided while consuming less power. This is given by:

(37) $\begin{array}{cc}{\stackrel{\_}{V}}_{n,\mathrm{out}}^2={{\stackrel{\_}{V}}_{\mathrm{nY}}^2\left(\frac{r_{\mathrm{ds}2}.Math..Math.r_{\mathrm{ds}4}}{r_{\mathrm{ds}2}.Math..Math.r_{\mathrm{ds}4}+1/g_{m3}}\right)}^2-{{\stackrel{\_}{V_{\mathrm{nX}}}}^2\left(\frac{g_{m2}+g_{m4}}{g_{m3}}\right)}^2{V}_{n,\mathrm{out}}=0.Math.\frac{R_F+R_s}{R_s}=\frac{g_{m2}+g_{m4}}{g_{m3}}& \left(7\right)\end{array}$

(38) In the above, g.sub.m2 is added with g.sub.m4 and hence this condition can be satisfied by consuming less power. Therefore, using the noise reduction approach in the noise cancellation stage of the conventional noise cancellation scheme reduces the power dissipation without affecting the NF. Note that Equation 7 is used to show the effect of M.sub.4 in the conventional noise cancellation condition without considering the parasitic capacitances. The noise cancellation condition of the circuit, considering all parasitic capacitances, is shown in Equation 10. Although in practice, the condition presented in Equation 8 is not completely satisfied due to the parasitic capacitances and the limitation of the power consumption. Therefore, the noise is reasonably attenuated even by partially meeting this condition.

(39) A schematic diagram illustrating an example wideband noise cancelling low noise amplifier (LNA) is shown in FIG. 6. In the circuit, generally referenced 65, the common gate (CG) transistors are used as an input stage to provide wideband input matching. The channel thermal noise of the matching transistor creates two out of phase voltage noises at nodes Y and X, with the latter smaller in amplitude. By amplifying the voltage noise X through M.sub.2 and adding it to the voltage noise Y amplified through M.sub.3, the noise of the input transistor M.sub.1 is canceled at the output. Although in this NC structure the channel thermal noise of the matching stage M.sub.1 is cancelled by the second stage, i.e. M.sub.2 and M.sub.3, the noise of the second stage is unaffected and can negatively impact the overall noise performance. This is reinforced by the fact that the input matching stage does not provide enough gain, so M.sub.2 can be the dominant noise source.

(40) A schematic diagram illustrating an example wideband noise cancelling low noise amplifier (LNA) incorporating noise cancellation and reduction techniques is shown in FIG. 7. The LNA, generally referenced 70, is applicable to 4G/5G applications. In this topology, M.sub.1 provides the wideband input matching. Moreover, the CS stage M.sub.2, is selected to cancel the channel thermal noise of M.sub.1. To reuse the current of M.sub.2 and improve the IIP2, M.sub.3 is chosen as a pMOS transistor. The inductor L.sub.S functions to provide a dc current path and resonates with the total parasitic capacitance at the input node. Finally, the presented noise reduction is used in the LNA. By using the current-reuse technique, the transistor M.sub.4 is paralleled with M.sub.2 ac-wise in order to boost its transconductance, and hence, decrease its thermal noise effect. In the LNA, the pMOS-nMOS structure and sweet spot biasing are applied to improve the linearity. Moreover, in one embodiment, a large value is selected for inductor L.sub.S and located off-chip in order to save on-chip area.

(41) Note that the common-gate transistor is used in the first stage to realize the wideband input matching. To consider the body effect of M.sub.1 and also to simplify the relations, G.sub.m1 stands for (1+g.sub.m0)(g.sub.m1+g.sub.mb1)(1+g.sub.m0)g.sub.m1. Hence, the input impedance is given by:

(42) $\begin{array}{cc}\begin{array}{c}{Z}_{in}=\left(R_{\mathrm{Ls}}+{\mathrm{sL}}_s\right).Math.\frac{1}{{\mathrm{sC}}_X}.Math.\frac{1}{G_{m1}}\\ =\frac{R_{\mathrm{Ls}}+{\mathrm{sL}}_s}{C_X{L}_s{s}^2+\left(R_{\mathrm{Ls}}{C}_X+G_{m1}{L}_s\right)s+\left(G_{m1}{R}_{\mathrm{Ls}}+1\right)}\end{array}& \left(8\right)\end{array}$
where C.sub.X demonstrates the total parasitic capacitance in node X which is damped by L.sub.S. The size of L.sub.S should be increased up to 150 nH to achieve the input matching at low frequencies. If the size of L.sub.S is decreased, the series resistance of L.sub.S, R.sub.Ls, will be also decreased (approximately up to 5) due to the limited quality factor of L.sub.S. This resistance is paralleled with 1/(G.sub.m1) and lowers the equivalent input impedance.

(43) The equivalent impedance, seen from the drain of M.sub.1 toward the ground, is called Z.sub.Y and it is equal to R.sub.D1[r.sub.ds1+(R.sub.s1/sC.sub.XsL.sub.s)(1+G.sub.m1r.sub.ds1]/sC.sub. where R.sub.S is the source resistance. Moreover, R.sub.D1 is the load resistance of M.sub.1 and C.sub.Y is the total parasitic capacitance in node Y. Z.sub.out determines the output impedance which is calculated as r.sub.ds2r.sub.ds3r.sub.ds41/sC.sub.out where C.sub.out is the total output parasitic capacitance. Therefore, the voltage gain of the proposed LNA is given by:

(44) $\begin{array}{cc}{A}_v=\frac{1/g_{m1}}{1/g_{m1}+R_s}\left(g_{m1}{g}_{m3}.Math.Z_Y.Math.+g_{m2}+g_{m4}\right).Math.Z_{\mathrm{out}}.Math.& \left(9\right)\end{array}$

(45) Technology scaling causes the value of r.sub.ds to be reduced due to the channel length reduction. Also, by using pMOS transistors at the output node, the parasitic capacitances are increased resulting in more variation in r.sub.ds at high frequencies. This is the main reason the bandwidth of the circuit is limited at high frequencies. To solve this problem, inductive shunt-peaking and series-peaking techniques can be used. The shunt inductive peaking causes a resonance at the output of each stage when the gain starts to roll off at higher frequencies.

(46) As mentioned supra, the purpose of noise cancellation is to dissociate the input matching relation from the NF by canceling the noise from the matching stage at the output node. In the LNA of the present invention, the current noise of the input transistor flows into node X but out of node Y causing two voltages with opposite phases at these nodes. These two voltages are converted to current by M.sub.2 and M.sub.3. But, the input signal in these two nodes have the same phase. Thus, the input signal is amplified at the output. These two noise voltages are calculated as V.sub.nX.sup.2=Z.sub.in.sup.2I.sub.n,M1.sup.2. Thus, the output current noise due to the thermal noise of M.sub.1 is as follows:

(47) $\begin{array}{cc}\begin{array}{c}{\stackrel{\_}{I_{n,\mathrm{out}}}}^2={{\stackrel{\_}{V_{\mathrm{nX}}}}^2\left(g_{m2}+g_{m4}\right)}^2-{\stackrel{\_}{V_{\mathrm{nX}}}}^2{g}_{m3}=0\\ =\frac{g_{m2}+g_{m4}}{g_{m3}}=\frac{Z_Y}{Z_X}\end{array}& \left(10\right)\end{array}$

(48) In one embodiment, to reuse the current of M.sub.2, M.sub.3 is chosen as a pMOS transistor. Also, the noise reduction technique is applied to improve the NF without any additional power consumption. In this technique, for ac signals, M.sub.4 is paralleled with M.sub.2, and hence, the transconductance of M.sub.4 is added to that of M.sub.2. Moreover, M.sub.4 is selected as a pMOS transistor in order to reuse the current of M.sub.2. By increasing the transconductance of M.sub.2, the channel thermal noise of the cancellation stage is reduced. In this way, any extra branch is not used in the LNA. Thus, the improvement in noise figure is achieved without consuming any extra power as explained supra. By using the noise cancellation technique, the most important noise sources are the thermal noise of R.sub.D1 and the channel thermal noise of transistors M.sub.2, M.sub.3, and M.sub.4. The noise factor of the LNA is equal to F=1+F.sub.RD1+F.sub.M2+F.sub.M3+F.sub.M4 where the terms are given by the following relations:

(49) 0$\begin{array}{cc}\begin{array}{c}{F}_{R,D1}=\frac{4{{\mathrm{kTR}}_{D1}\left(g_{m3}.Math.Z_{\mathrm{out}}.Math.\right)}^2{\left(Z_{o1}/\left(Z_{o1}+R_{D1}\right)\right)}^2}{4{\mathrm{kTR}}_s{A}_v^2}\\ \frac{R_s}{R_{D1}}\end{array}& \left(11\right)\end{array}$
where according to FIG. 7, Z.sub.o1=[r.sub.ds1+(R.sub.s1/sC.sub.XsL.sub.s)(1+g.sub.m1r.sub.ds1)] and Z.sub.Y=R.sub.D1Z.sub.o1 when the parasitic capacitances in node Y are not considered in order to simplify the above equation. A.sub.v denotes the voltage gain of proposed LNA which is simplified by considering the noise cancellation condition (g.sub.m2+g.sub.m4)R.sub.s=g.sub.m3R.sub.D1 and input matching as Z.sub.in=R.sub.s=1/G.sub.m1.

(50) $\begin{array}{cc}{F}_{M2}=\frac{4{\mathrm{kTg}}_{m2}{.Math.Z_{\mathrm{out}}.Math.}^2}{4k{\mathrm{TR}}_s{A}_v}\frac{}{}=\frac{4g_{m2}}{{R_s\left(Z_Y{G}_{m1}{g}_{m3}+g_{m2}+g_{m4}\right)}^2}\frac{}{}\frac{g_{m2}}{{R_s\left(g_{m2}+g_{m4}\right)}^2}\frac{}{}.& \left(12\right)\\ F_{M3}=\frac{4{\mathrm{kTg}}_{m3}{.Math.Z_{\mathrm{out}}.Math.}^2}{4{\mathrm{kTR}}_s{A}_v}\frac{}{}=\frac{4g_{m3}}{{R_s\left(Z_Y{G}_{m1}{g}_{m3}+g_{m2}+g_{m4}\right)}^2}\frac{}{}\frac{R_s}{{.Math.Z_Y.Math.}^2{g}_{m3}}\frac{}{}.& \left(13\right)\end{array}$

(51) $\begin{array}{cc}{F}_{M4}=\frac{4{\mathrm{kTg}}_{m4}{.Math.Z_{\mathrm{out}}.Math.}^2}{4{\mathrm{kTR}}_s{A}_v}\frac{}{}=\frac{4g_{m4}}{{R_s\left(Z_Y{G}_{m1}{g}_{m3}+g_{m2}+g_{m4}\right)}^2}\frac{}{}\frac{g_{m4}}{{R_s\left(g_{m2}+g_{m4}\right)}^2}\frac{}{}.& \left(14\right)\end{array}$

(52) Considering the noise cancellation condition, Equation 13 can be simplified as follows:

(53) $\begin{array}{cc}{F}_{M3}=\frac{R_s}{{.Math.Z_Y.Math.}^2{g}_{m3}}\frac{R_s}{R_{D1}\left(g_{m2}+g_{m4}\right)R_s}\frac{}{R_{D1}\left(g_{m2}+g_{m4}\right)}.& \left(15\right)\end{array}$

(54) Finally, the total noise factor of the LNA of the present invention is approximately given by:

(55) $\begin{array}{cc}F1+\frac{R_s}{R_{D1}}+\frac{}{R_{D1}\left(g_{m2}+g_{m4}\right)}+\frac{}{R_s\left(g_{m2}+g_{m4}\right)}& \left(16\right)\end{array}$
where the fourth component in Equation 16 represents the total noise factor due to M.sub.2 and M.sub.4 transistors. According to Equation 16, to reduce the thermal noise of R.sub.D1, its value should be increased, but, this is limited by the voltage drop on R.sub.D1. In addition, the channel thermal noise of M.sub.3 can be decreased by enhancing g.sub.m2. Referring to FIG. 7, by using the noise reduction technique of the present invention, g.sub.m2 is increased without utilizing any additional power.

(56) The LNA 70 shown in FIG. 7 has been designed and constructed using 28 nm CMOS technology. The percentage of noise sources in the total NF at 800 MHz is shown in FIG. 8 where the circuit of the present invention structure (pyramids 77) is compared with two others, namely (1) the CG structure shown in FIG. 1A without any noise cancellation and reduction techniques (boxes 75) and (2) an LNA without M.sub.4, i.e. without the noise reduction technique of the present invention (cylinders 76), i.e. the circuit of FIG. 6. In this comparison, the LNA with and without M.sub.4 consumes 6.5 mW power with the same size transistors. The size of transistor in the CG structure is the same as the size of CG transistor in the LNA of the present invention and its power consumption is the same as that of the first stage in the circuit of the present invention which is about 1.5 mW.

(57) As shown, the common-gate structure (boxes 75) suffer from high NF. The channel thermal noise of the main transistor M.sub.1 is 40% of the total NF. By canceling the thermal noise of the main transistor, the most effective noise source, which is controllable, is the thermal noise of M.sub.2. In the structure without M.sub.4 (cylinders 76) the thermal noise of the main transistor M.sub.1 is reduced to 3%, whereas the thermal noise of the cancellation transistor M.sub.2 is added to the circuit and its amount is almost 29%. By using both noise reduction and cancellation techniques (pyramid 77) the thermal noise of M.sub.2 is decreased to 3%, and hence, the noise performance is improved while using the same power consumption. The thermal noise of R.sub.D1 remains after using the cancellation and reduction techniques. To reduce the noise effect of R.sub.D1, its amount should be increased, but as mentioned supra, the amount of R.sub.D1 is limited by the supply voltage.

(58) In a wireless communication receiver, signals are usually treated as small signals before the baseband amplifier. The important nonlinearity effects for small signals are the second and third order intermodulation products, of which the former is preferably lowered in a direct-conversion receiver, while the latter should be suppressed enough to avoid the large interference from adjacent channels.

(59) Since the nonlinearity of a CS transistor is worse than that of a CG transistor, the pMOS-nMOS structure is applied in the output stage to enhance the values of IIP2 and IIP3. According to the circuit 70 of FIG. 7, utilizing power series, the current of either pMOS or nMOS transistor is equal to i.sub.ds=()+().sup.2+().sup.3 where g.sub.m, g.sub.m, and g.sub.m are the first three order derivatives of the drain-source dc current i.sub.ds with respect to v.sub.gs which are the linear, second-order and third-order nonlinear components, respectively. By considering this equation in the second stage of the proposed LNA, the second-order nonlinear term 2g.sub.mv.sub.inv.sub.s can be mixed with the input by the feedback path. Thus, the third-order nonlinear component is generated and added to the main third-order nonlinear term.

(60) A graph illustrating second order nonlinear component of pMOS and nMOS transistors is shown in FIG. 9. As shown, using pMOS and nMOS transistors at the output stage causes the second-order nonlinear components, g.sub.mp, and g.sub.mn, to neutralize each effect in a range of the bias voltage. As a result, the second-order nonlinear term is attenuated and both IIP2 and IIP3 are improved. By using this technique, the linearity of the CS transistor is improved. To improve the linearity of the CG transistor, this transistor is biased in the sweet spot.

(61) A graph illustrating second and third order derivatives of the drain source dc current i.sub.ds with response to V.sub.gs is shown in FIG. 10. As shown, by biasing the transistor with an appropriate voltage in which the third-order nonlinear component of the CG transistor, g.sub.m, is equal to zero, the IIP3 of the common-gate structure can be improved. A drawback of the sweet spot technique is its sensitivity to the process corners. The constant g.sub.m biasing circuit is used in the proposed LNA structure in order to deal with the problem of sweet spot technique because the constant g.sub.m biasing is less sensitive to the process corners and temperature variations. To examine the stability of an LNA with arbitrary source and load impedances, the Stern stability factor defined in Equation 17 below is often utilized:

(62) $\begin{array}{cc}K=\frac{1+{.Math..Math.}^2-{.Math.S_{11}.Math.}^2-{.Math.S_{22}.Math.}^2}{2.Math.S_{21}.Math..Math.S_{12}.Math.}& \left(17\right)\end{array}$

(63) where =S.sub.11S.sub.22S.sub.12S.sub.21 and S.sub.11, S.sub.22, S.sub.21, and S.sub.12 are the input return loss, output return loss, forward gain, and reverse gain, respectively. If K>1 and <1, then the circuit is unconditionally stable. According to Equation 17, the stability of the circuit is improved by maximizing the reverse isolation.

(64) The LNA 70 of FIG. 7 has been implemented in 28 nm CMOS technology over 0.1 to 7.3 GHz. By carefully sizing of the transistors and using the noise cancellation and reduction techniques (i.e. dc current reuse technique), it is possible to operate this amplifier with a power dissipation of 6.25 mW from a 1.05 V power supply while achieving relatively high and flat small-signal gain and a very low noise figure over the entire bandwidth. The S-parameters, noise figure, IIP2 and stability of the proposed LNA are simulated. This wideband LNA provides 15 dB maximum power gain with a NF of 2.7 dB in worse case.

(65) A graph illustrating simulated input return loss including S-parameters of the LNA is shown in FIG. 11. As shown, the minimum input return loss is around 500 MHz, which means the input impedance is matched at that frequency. Although the input return loss is higher away from this point, the wideband input matching feature is well controlled below 10 dB in the whole bandwidth. As it is anticipated, the input return loss becomes worse because the paralleled transistor M.sub.4 adds extra parasitic capacitances to the input node.

(66) A graph illustrating a simulation of power gain as a function of frequency is shown in FIG. 12. As shown, the noise figure is shown as trace 112 and S.sub.21 as trace 110. The power gain varies between 12.2-15.2 dB in 100 MHz up to 7.3 GHz. As shown, adding transistor M.sub.4 causes an increase in the second stage transconductance in the LNA resulting in 2 dB more power gain which is expected from the Equation 9. Since the drain of three transistors M.sub.2, M.sub.3, M.sub.4 are connected to the output node, the total parasitic capacitance in this node is increased. Hence, the 3 dB bandwidth of the LNA is decreased. One solution to alleviate this is to use a shunt-peaking inductor at the output node in order to damp the total parasitic capacitance and smooth the gain. This, however, also increases the on-chip area of the LNA.

(67) The NF of the LNA of the present invention is shown in FIG. 13. By applying the noise reduction technique, the NF has been decreased by 25% because the transconductance of M.sub.2 is boosted and its thermal noise effect is reduced. The noise figure of the LNA varies from 2 dB to 2.7 dB in the 7.2 GHz bandwidth.

(68) A graph illustrating a full wave simulation of noise figure and power gain as a function of frequency is shown in FIG. 14. In full wave analysis, all the interconnections and passive devices are accurately RLC extracted from 0 to 20 GHz using an electromagnetic tool such as Solidworks EMS magnet and electromagnetic software simulation product from Dassault Systems, Paris, France. Then they are used with RC extracted from active devices to do full wave simulation. As shown, the noise figure is represented as trace 112 and S.sub.21 as trace 110. The power gain S.sub.21 varies between 11.6 to 14.6 dB in 100 MHz up to 7.3 GHz. The minimum amount of the noise figure is approximately 2.3 dB.

(69) To determine stability, the simulated Stern stability factor K (trace 132) and A (trace 130) are illustrated in FIG. 15. As indicated, over the whole bandwidth, K>1 and A<1 resulting in guaranteed stability of the simulated LNA. Finally, a two-tone RF signal sweeping from 100 MHz up to 7.3 GHz is used to simulate the linearity performance of the LNA. As shown in FIG. 16, the simulated IIP3 (trace 140) is 4 dBm in the middle of the bandwidth. A summary of the LNA including a figure of merit (FoM) is summarized below in Table 1.

(70) TABLE-US-00001 TABLE 1 LNA Summary and FoA CMOS Tech. [nm] 28 BW [GHz] 0.1~7.3 S.sub.11 [dB] <10 S.sub.21 [dB] 12.2~15.2 IB-IIP3 [dBm] 4~8 NF [dB] 2-~2.4 VDD [V] 1.05 Power [mW] 6.5 Active Area [mm.sup.2] 0.024 FoM.sub.1 12.63

(71) $\begin{array}{cc}{\mathrm{FOM}}_1=\frac{{\mathrm{Gain}}_{\mathrm{av}}\left[\mathrm{abs}\right]\mathrm{BW}\left[\mathrm{GHz}\right]}{\left(F_{\mathrm{av}}-1\right)P_{dc}\left[\mathrm{mW}\right]}& \left(18\right)\\ {\mathrm{FOM}}_2=\frac{{\mathrm{Gain}}_{\mathrm{av}}\left[\mathrm{abs}\right]\mathrm{BW}\left[\mathrm{GHz}\right]\mathrm{IIP}3\left[\mathrm{mW}\right]}{\left(F_{\mathrm{av}}-1\right)P_{dc}\left[\mathrm{mW}\right]}& \left(19\right)\end{array}$

(72) Where Gain.sub.av is the average power gain, F.sub.av is the average noise factor over the frequency range and P.sub.dc is the power consumption. According to Table 1, the LNA provides a relatively low noise figure and has acceptable power consumption for 7.3 GHZ bandwidth which is achieved by using both noise reduction and cancellation techniques. Moreover, the circuit has a comparable linearity and quite high power gain. Nonetheless, the outstanding FoM makes the circuit a good candidate for low noise and low power wideband CMOS transconductance amplifiers.

(73) Note that a goal of the present invention is to provide a noise reduction technique that does not require extra power consumption. This is due to the use of the dc current reuse technique to decrease the noise of the circuit.

(74) In an alternative embodiment, three stages are used to realize inductor-less two-fold noise cancellation to further lower the noise figure while extending the bandwidth. A schematic diagram illustrating a two-fold noise cancelling LNA of the present invention is shown in FIG. 17. The circuit, generally referenced 150, comprises a common mode feed block 152, input matching block 154, first noise cancellation stage 156, and second noise cancellation stage 158.

(75) In this structure, M.sub.1 is used as the CG structure for implementing the broadband input matching. M.sub.2 is paralleled with M.sub.1 in order to reduce the current of first stage and increase the overall transconductance g.sub.m. The second stage is an NC complementary CS topology of M.sub.3 and M.sub.4. A pMOS-nMOS complementary pair is used in both first and second stages to improve linearity as well as to enhance linearity (IIP3) via a sweet spot biasing technique. The latter technique is also utilized in the additional, i.e. third, stage.

(76) Using the noise cancellation technique, the most important noise source, i.e. the channel thermal noise of CS transistors in the second stage, is addressed. In order to deal with this challenge, the third stage, M.sub.5 and M.sub.6, is utilized to cancel the channel thermal noise of M.sub.3 and M.sub.4, i.e. the first noise cancellation stage. Inductance L.sub.s is used in the source of M.sub.1 and M.sub.2 to provide a dc current path and cancel the degrading effect of the parasitic capacitances of transistors M.sub.1, M.sub.2 and M.sub.3. Since the P and Q nodes are the high impedance node, their voltage varies. The transistors M.sub.F1 to M.sub.F5 are employed to provide the variation of voltage in P node. Moreover, the negative feedback R.sub.F is used to prevent the variation of dc voltage in node Q. Since the Miller effect of R.sub.F is much larger than the input and output impedances, its effect is ignored in all analysis.

(77) Regarding, dc biasing, a constant g.sub.m biasing circuit is used to bias the transistors. Two external source inductors L.sub.s provide a dc path for the bias current of the first stage. Two nMOS and pMOS branches are used in first and second stages which can cause the dc voltages of P and Q nodes to vary. In other words, the P and Q nodes are of high impedance which may cause the transistors to inadvertently enter the linear region. For the first stage, common-mode feedback circuitry is utilized to define the drain dc voltage of transistors M.sub.1 and M.sub.2. This circuit realized by transistors M.sub.F1 to M.sub.F5 in block 152. The voltage variation of P node is compensated by variation of gate-source voltage of M.sub.1. In addition, C.sub.7 sets the ac ground for the gate of M.sub.1 so the feedback path regulates the bias output voltage. In addition, the resistive feedback R.sub.F is used to handle the variations of dc voltage at node Q. As mentioned supra, the size of R.sub.F is assumed high, therefore, the dc voltage at node Q is approximately equal to M.sub.3's gate-source voltage V.sub.gs3.

(78) Regarding input matching, the LNA input must be matched to the specific reference impedance Z.sub.0=50 to not affect the preceding stage (e.g., the antenna). The quality of input matching is judged by the S-parameter S.sub.11 defined as:

(79) $\begin{array}{cc}{S}_{11}=.Math.\frac{Z_{in}-Z_0}{Z_{in}+Z_0}.Math.& \left(20\right)\end{array}$
where Z.sub.in is the input impedance of the LNA. The value of S.sub.11 is preferably <10 dB.

(80) The complementary common gate (CG) transistors, M.sub.1 and M.sub.2, are used in the first stage to realize the wideband input matching. Since they are in parallel at ac (i.e. mid frequencies), their transconductances add and their combined input impedance becomes 1/(g.sub.m1+g.sub.mb1+g.sub.m2+g.sub.mb2). This value is, to the first order, independent of frequency. Due to the current being reused, the structure provides the required input matching at a much lower current.

(81) To simplify the following notation, we lump the body effect into the main transconductance g.sub.m. Hence, g.sub.m1 and g.sub.m2 stand for g.sub.m1+g.sub.mb1 and g.sub.m2+g.sub.mb2, respectively. The input impedance is calculated as:

(82) $\begin{array}{cc}{Z}_{in}=\frac{1}{2}\left(R_{\mathrm{Ls}}+{\mathrm{sL}}_s\right).Math.\frac{1}{{\mathrm{sC}}_N}.Math.\frac{1}{g_{m1}+g_{m2}}=\frac{R_{\mathrm{Ls}}+{\mathrm{sL}}_s}{\begin{array}{c}{C}_N{L}_s{s}^2+\left(R_{\mathrm{Ls}}{C}_N+\left(g_{m1}+g_{m2}\right)L_s\right)s+\\ \left(\left(g_{m1}+g_{m2}\right)R_{\mathrm{Ls}}+1/2\right)\end{array}}& \left(21\right)\end{array}$
where R.sub.Ls is a series resistance of L.sub.s. Since M.sub.1 and M.sub.2 are in parallel at ac, the parasitic capacitance at node N is added to that of node M. C.sub.N denotes the total parasitic capacitance seen by the input node which is damped by L.sub.s. According to Equation 20, the input matching condition, S.sub.11<10 dB, will be achieved if |Z.sub.in| is around 50. As stated by Equation 21, at mid frequencies, the input impedance is 1/(g.sub.m1+g.sub.m2). At low frequencies, the input matching can be effectively influenced by R.sub.Ls. The value of L.sub.s should be increased up to 150 nH to ensure the input matching. If the size of L.sub.s decreases, R.sub.Ls will also decrease due to the limited quality factor of L.sub.s (approximately up to 5). Therefore, this resistance is paralleled with 1/(g.sub.m1+g.sub.b1) and lowers the equivalent input impedance. Note that in one embodiment, inductance L.sub.s is an off-chip component.

(83) Regarding gain analysis, three stages are used in the LNA structure which provides significant gain. The second stage is the most effective stage to provide gain and thus consumes more current than other branches. Since the first stage preferably provides input matching condition, it draws less current. Therefore, its voltage gain could not be high enough. In addition, the third stage functions as a buffer and cannot increase gain effectively.

(84) The equivalent impedance, seen from the drain of M.sub.1 toward the ground, is called Z.sub.P and it is equal to r.sub.ds1[r.sub.ds2+(R.sub.s1/sC.sub.NsL.sub.s/2)((g.sub.m2+g.sub.m1)r.sub.ds1r.sub.ds2)]/sC.sub.P where R.sub.s is the source resistance and C.sub.P is the total parasitic capacitance in node P. Z.sub.Q is equal to r.sub.ds2r.sub.ds31/sC.sub.Q where C.sub.Q is the entire parasitic capacitor in node Q. Z.sub.out is defined as the output impedance which is calculated as r.sub.ds5r.sub.ds61/g.sub.m61/sC.sub.out where C.sub.out is the output parasitic capacitance. The voltage gain of LNA is calculated as:

(85) $\begin{array}{cc}{A}_v=\left(\frac{1/\left(g_{m1}+g_{m2}\right)}{1/\left(g_{m1}+g_{m2}\right)+R_s}\right)\left[\left(\left(g_{m1}+g_{m2}\right)g_{m4}.Math.Z_P.Math.+g_{m3}\right)g_{m6}\right)].Math.Z_{\mathrm{out}}.Math.& \left(22\right)\end{array}$

(86) The voltage gain of the proposed LNA without considering the third stage, A.sub.v, is equal to: A.sub.v=Z.sub.Q which is equal to ()[g.sub.m3+(g.sub.m1+g.sub.m2)g.sub.m4(r.sub.ds1r.sub.ds2)]. As stated by the transfer function of Z.sub.Q, the dominate pole causes the Z.sub.Q to have a large variation (the Z.sub.Q roll off happens at low frequencies) so 3 dB bandwidth decreases. By applying the third stage, the voltage gain is equal to: A.sub.v=(g.sub.m6Z.sub.Q+g.sub.m3)Z.sub.out. The transconductance of M.sub.5 is added to A.sub.v which creates a zero after dominate pole and naturalizes its effect. This zero makes the Z.sub.Q's variation become smooth so the high edge of bandwidth is extended.

(87) Regarding noise analysis, in the LNA 150, double noise cancellation techniques are utilized to enhance the noise figure. One noise cancellation technique is applied for the CG structure which is conventional noise cancellation and another one is used for CS transistors in the second stage. The two noise cancellation techniques will now be explained.

(88) In a first noise cancellation block 156 for CG transistors, as described supra, since the CG structure has high NF, a noise cancellation technique is applied to cancel the noise effect of the input transistors. The current noise of the input transistors flow into the input node N or M node but out of the node P that creates two voltages with opposite phases. These two voltages are converted to current by M.sub.3 and M.sub.4. The input signal in these two nodes, however, has the same phases. Thus, the input signal is boosted at the output. These two voltages are calculated as V.sub.nN.sup.2 .Math.=Z.sub.P.sup.2.Math., thus, the current noise after passing through the cancellation stage I.sub.n2 is equal to:

(89) 0$\begin{array}{cc}\begin{array}{c}{\stackrel{\_}{I}}_{n2}^2={\stackrel{\_}{V}}_{\mathrm{nN}}^2{g}_{m3}^2-{\stackrel{\_}{V}}_{\mathrm{nP}}^2{g}_{m4}^2=0\\ =\frac{g_{m3}}{g_{m4}}=.Math.\frac{Z_P}{Z_N}.Math.\end{array}& \left(23\right)\end{array}$

(90) To reuse the current of M.sub.3, M.sub.4 is selected as a pMOS transistor. In this manner, the noise factor of the LNA without considering third the stage F.sub.1 is equal to F.sub.1=1+F.sub.M3+F.sub.M4. The terms of noise factor are given by following relations:

(91) $\begin{array}{cc}{F}_{M3}=\frac{4{\mathrm{kTg}}_{m3}{.Math.Z_Q.Math.}^2}{4{\mathrm{kTR}}_s{A}_v^{}}\frac{}{}=\frac{4g_{m3}}{{R_s\left(.Math.Z_P.Math.\left(g_{m1}+g_{m2}\right)g_{m4}+g_{m3}\right)}^2}\frac{}{}\frac{g_{m3}}{{R_s\left(g_{m3}\right)}^2}\frac{}{}.& \left(24\right)\\ F_{M4}=\frac{4{\mathrm{kTg}}_{m4}{.Math.Z_Q.Math.}^2}{4{\mathrm{kTR}}_s{A}_v^{}}\frac{}{}=\frac{4g_{m4}}{{R_s\left(.Math.Z_P.Math.\left(g_{m1}+g_{m2}\right)g_{m4}+g_{m3}\right)}^2}\frac{}{}\frac{R_s}{{.Math.Z_P.Math.}^2\left(g_{m1}+g_{m2}\right)g_{m4}}\frac{}{}.& \left(25\right)\end{array}$
where A.sub.v is the voltage gain of the LNA without considering the third stage, is the excess noise factor in short channel devices, and is the ratio of the transconductance g.sub.m to the zero-bias drain conductance g.sub.d0. Since the parasitic capacitances in input node C.sub.N are almost damped by L.sub.s, the relations Z.sub.in=R.sub.s=1/(g.sub.m1+g.sub.m2) is assumed. Thus, F.sub.1 is approximately given by:

(92) $\begin{array}{cc}F1+\frac{}{R_s{g}_{m3}}+\frac{R_s}{{.Math.Z_P.Math.}^2\left(g_{m1}+g_{m2}\right)g_{m4}}& \left(26\right)\end{array}$

(93) As indicated by Equation 26, the noise performance of the LNA is improved by cancelling the noise effect of M.sub.1 and M.sub.2, i.e. matching transistors, whereas the thermal noise of M.sub.3, 4, i.e. common source transistors, influence the factor noise effectively. Therefore, the second noise cancellation technique functions to cancel out the noise of M.sub.3, 4 and achieve improved noise performance.

(94) In a second noise cancellation block 158 for CS transistors, the noise current of the transistor M.sub.3 flows through the feedback resistor R.sub.F to the node N and instantaneously creates two noise voltages with the same phase but different amplitudes in nodes N and Q. On the other hand, the signal voltage at these nodes has opposite phase and different amplitude due to the inverting amplifier. The difference between the signal and noise polarities at nodes N and Q makes it possible to cancel the M.sub.3 noise while adding the signal contributions constructively. The noise voltage in node N Vn.sub.N.sup.2 is amplified and inverted by M.sub.5 and also the noise voltage in node Q V.sub.nQ.sup.2 is passed across M.sub.6 without any change. Then in the output V.sub.out two voltages with opposite phases are added. Therefore, the channel thermal noise of M.sub.3 will be canceled at the output provided the following condition is satisfied:

(95) $\begin{array}{cc}{\stackrel{\_}{V}}_{\mathrm{nout}}^2={\stackrel{\_}{V}}_{\mathrm{nQ}}^2{g}_{m6}^2{.Math.Z_{\mathrm{out}}.Math.}^2-{\stackrel{\_}{V}}_{\mathrm{nN}}^2{g}_{m5}^2{.Math.Z_{\mathrm{out}}.Math.}^2=0\frac{g_{m5}}{g_{m6}}=\frac{\left(R_F+R_s/2\right).Math..Math..Math.Z_Q.Math.}{R_s/2}& \left(27\right)\end{array}$
where g.sub.mr.sub.ds>>1 is assumed. The terms of noise factor in the LNA are given by the following relations in which the two noise cancellation conditions in Equations 23 and 27 are applied to simplify the relations:

(96) $\begin{array}{cc}\begin{array}{c}{F}_{M5}=\frac{4{\mathrm{kTg}}_{m5}{.Math.Z_{\mathrm{out}}.Math.}^2}{4{\mathrm{kTR}}_s{A}_v}\frac{}{}\\ =\frac{4g_{m5}}{{R_s\left[\left(.Math.Z_P.Math.\left(g_{m1}+g_{m2}\right)g_{m4}+g_{m3}\right)g_{m6}.Math.Z_Q.Math.+g_{m5}\right]}^2}\\ \frac{4}{R_s{g_{M5}\left(.Math.Z_P.Math.g_{m4}+1\right)}^2}\frac{}{}.\end{array}& \left(28\right)\\ \begin{array}{c}{F}_{M6}=\frac{4{\mathrm{kTg}}_{m6}{.Math.Z_{\mathrm{out}}.Math.}^2}{4{\mathrm{kTR}}_s{A}_v}\frac{}{}\\ =\frac{4g_{m6}}{{R_s\left[\left(.Math.Z_P.Math.\left(g_{m1}+g_{m2}\right)g_{m4}+g_{m3}\right)g_{m6}.Math.Z_Q.Math.+g_{m5}\right]}^2}\\ \frac{R_s}{{\left(.Math.Z_P.Math.g_{m4}+1\right)}^2.Math.Z_Q^2.Math.}\frac{}{}.\end{array}& \left(29\right)\end{array}$
where Z.sub.out is output impedance and was mentioned supra and (R.sub.F+R.sub.s/2)>>Z.sub.Q is assumed. Finally, the total noise factor of the LNA 150 is given approximately by:

(97) $\begin{array}{cc}F1+\frac{4}{R_s{g_{m5}\left(Z_P{g}_{m4}+1\right)}^2}+\frac{R_s}{{\left(Z_P{g}_{m4}+1\right)}^2{.Math.Z_Q.Math.}^2}& \left(30\right)\end{array}$

(98) As stated by Equation 30, the channel thermal noise of third stage is added to the circuit. But the effect of the third and fourth terms of Equation 30, i.e. the noise effect of the third stage compared to the input, is very small because it is divided over the total voltage gain of the LNA and therefore has the least influence on total noise factor. Therefore, it is expected that the LNA 150 has a very low noise figure by use of the noise cancellation. One drawback of the circuit 150, however, is extra circuit branch which slightly increases power consumption.

(99) Regarding linearity of the LNA, by applying the two noise cancellation techniques, both linearity and noise performance of circuit improve. Nonlinearity of CG transistors can be modeled as a current source between their drain and source controlled by both V.sub.gs and V.sub.as. As described supra, this nonlinear current produces two voltages in opposite phase in node N and P which neutralize each effect by using noise cancellation stage, i.e. M.sub.3 and M.sub.4. Although this technique can cancel all intrinsic distortion generated by M.sub.1 and M.sub.2, including both g.sub.m and g.sub.as non-linearity, M.sub.3,4's distortion dominates the residual nonlinearity. Nonlinearity of CS transistors M.sub.3 and M.sub.4 can be modeled as a current between their drain and source too. By passing this current through R.sub.F and R.sub.s two nonlinear voltages are created. These two voltages are cancelled each effect by using third stage as second noise cancellation.

(100) Moreover, a pMOS-nMOS pair is used in both first and second stages in order to improve the IIP3. The input pMOS and nMOS transistors are biased in a way that the second nonlinear component of M.sub.1 and M.sub.2 cancel each other's effects within range of the bias voltage. In addition, the linearity of CS transistor M.sub.3 is improved by attenuating its second nonlinear term via the pMOS-nMOS structure. By using both the noise cancellation technique and pMOS-nMOS structures, the distortion of CS transistor in third stage M.sub.5 is the dominant component of the proposed structure's nonlinearity. To address this challenge, M.sub.5 is biased in the sweet spot. In the sweet spot, the third nonlinear component of M.sub.5 is equal to zero and hence its linearity is improved. As a result, the IIP3 of the LNA is improved.

(101) The LNA 150 of FIG. 17 has been implemented in 28 nm CMOS technology. By using double noise cancellation techniques, it is possible to achieve reasonably high and flat small signal gain and low noise figure in the whole of requisite bandwidth.

(102) The simulation results of the proposed LNA are shown in FIG. 18. In accordance with FIG. 18, the power gain S.sub.21 is shown as dashed trace 160, the noise figure (NF) as solid trace 162, and the input return loss S.sub.11 as dotted trace 164. Using CG transistors in the input stage provides an acceptable S.sub.11 comparable to state of the art designs. The results show a value of S.sub.11 below 10 dB over 0.1 to 4.5 GHz bandwidth. By using the third stage, the parasitic capacitances of M.sub.5 are added to the total capacitance in input node thereby deteriorating S.sub.11. But, as indicated by FIG. 18, the wideband input matching characteristic is well controlled below 10 dB across the entire bandwidth.

(103) The 3 dB bandwidth power gain is illustrated in FIG. 18 as well. The maximum power gain is 21 and 3 dB bandwidth is achieved in 0.1 to 3 GHz bandwidth. By adding the third stage, the power gain is increased which is expected as stated by Equation 10. As described supra, the third stage creates a zero which accomplishes the bandwidth extension. The bandwidth of the LNA without the third stage ranges from 200 MHz up to 1.2 GHz. By utilizing the third stage, the 3 dB bandwidth is extended to 3 GHz.

(104) The proposed LNA has relatively high power gain while achieving a low noise performance by drawing only 6.5 mA current from 1.05 V supply voltage. In addition, the LNA occupies a relatively very small area since it is inductor-less.

(105) Those skilled in the art will recognize that the boundaries between logic and circuit blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.

(106) Any arrangement of components to achieve the same functionality is effectively associated such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as associated with each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being operably connected, or operably coupled, to each other to achieve the desired functionality.

(107) Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

(108) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises and/or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(109) In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The use of introductory phrases such as at least one and one or more in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles a or an limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases one or more or at least one and indefinite articles such as a or an. The same holds true for the use of definite articles. Unless stated otherwise, terms such as first, second, etc. are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

(110) The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.