AUTO-CALIBRATION CIRCUIT FOR PULSE GENERATING CIRCUIT USED IN RESONATING CIRCUITS

Abstract

Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level.

Claims

1. An auto-calibration circuit (206) for calibrating a circuit fabricated on Metal-Oxide Semiconductors (MOS) technology providing required calibration to improve the performance of the circuit, wherein said auto-calibration circuit (206) comprises: an inverter block (302) that comprises a P-type Metal Oxide Semiconductor (PMOS) (312) and a N-type Metal Oxide Semiconductor (NMOS) (314); one or more gated inverters (304A-304N) that obtain first inputs B.sub.n and B.sub.p from Digital Memory Counters of the circuit, wherein the one or more gated inverters (304A-304N) comprises a plurality of PMOS and a plurality of NMOS; a first comparator (306) that is connected with the one or more gated inverters (304A-304N) that obtains a second input from at least one of the inverter block (302) or the one or more gated inverters (304A-304N); a NMOS gate (320) that is connected with a capacitor (316) and an XOR gate (318) to charge the capacitor (316) using a XOR signal (n1x) from the XOR gate (318), wherein the XOR gate (318) generates the XOR signal when the XOR gate (318) is connected with the first comparator (306); a second comparator (308) that obtains input from at least one of a voltage divider (310) or a capacitor (316); a PMOS counter that increases the count values when output values of the second comparator (308) and the XOR gate (318) are high, wherein the count values of the PMOS counter enables the plurality of PMOS of the one or more gated inverters (304A-304N); and a NMOS counter that increases the count values when the output value of the second comparator (308) is low and the output value of the XOR gate (318) is high, wherein the count values of the NMOS counter enables the plurality of NMOS of the one or more gated inverters (304A-304N) to provide required calibration to the circuit.

2. The circuit as claimed in claim 1, wherein the plurality of PMOS is connected with the inverter block (302) when the input B.sub.p is high.

3. The circuit as claimed in claim 1, wherein the plurality of NMOS is connected with the inverter block (302) when the input B.sub.n is high.

4. The circuit as claimed in claim 1, wherein a voltage divider (310) comprises a first resistor (322) and a second resistor (324), wherein the ratio between the first resistor (322) and the second resistor (324) is selected based on a threshold voltage which is used to provide the required calibration.

5. The circuit as claimed in claim 1, wherein the one or more gated inverters (304A-304N) comprises a NOT (402), a NOR gate (404), a NAND gate (406), a gated PMOS (408) and a gated NMOS (410), wherein the one or more inverter (304) obtains the first input B.sub.p using the NOT gate (402) and the first input B.sub.n using the NAND gate (406).

6. The circuit as claimed in claim 1, wherein the one or more gated inverters (304A-304N) connected with the inverter block (302).

7. The circuit as claimed in claim 1, wherein the capacitor (316) samples the input voltage when the XOR signal is high.

8. The circuit as claimed in claim 1, wherein the second comparator (308) generates a second comparator output (nvx) and the XOR gate (318) generates the XOR signal, wherein the PMOS counter and the NMOS counter increases the count-up value when the XOR signal and the second comparator output is high, wherein the PMOS counter and the NMOS counter increases the count-down value when the XOR signal is high and the second comparator output is low.

9. A method for calibrating the pulse widths of a pulse generator (102) circuit using auto-calibration circuit (206), the method comprising generating a pulse to turn on a NMOS switch (320) using a first comparator (318); allowing a capacitor (316) to charge based on an input signal using the NMOS switch (320); generating a second comparator output (nvx) based on the input received from the capacitor (316) and a resistance divider (310) using a second comparator (308); and generating control bits using one or more gated inverters (304A-304N) for calibrating the pulse widths of a pulse generator (102).

10. The method as claimed in claim 9, wherein the method comprises generating a XOR signal using the XOR gate (318); increasing a count-up value when the XOR signal and the second comparator output is high using a PMOS counter and a NMOS counter; and increasing a count-down value when the XOR signal is high and the second comparator output is low using a PMOS counter and a NMOS counter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The embodiment herein will be better understood from the following detailed description with the drawings, in which

[0018] FIG. 1 illustrates a pulse generator circuit that is auto-calibrated to generate the precise pulses that are required for energy savings in the digital circuits according to an embodiment herein;

[0019] FIG. 2 illustrates an auto-calibration circuit of the pulse generator circuit of FIG. 1 according to an embodiment herein;

[0020] FIG. 3 illustrates an auto-calibration circuit of the pulse generator circuit shown in FIG. 1, according to an embodiment herein;

[0021] FIG. 4 illustrates an exploded view of a gated inverter of FIG. 3 according to an embodiment herein;

[0022] FIG. 5 represents the waveforms related to the calibration circuit shown in FIG. 3, according to an embodiment herein; and

[0023] FIG. 6 is a flow diagram illustrates a method of calibrating using the auto-calibration circuit shown in FIG. 3 according to the embodiment herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

[0025] FIG. 1 illustrates a pulse generator circuit 102 that is auto-calibrated to generate the precise pulses that are required for energy savings in the digital circuits according to an embodiment herein. The pulse generator circuit 102 is connected to a voltage doubler 104. The pulse generator circuit 102 comprises inverter 106, a delay inductance, a transmission gate, a matched capacitance and an exclusive OR (XOR) gate. The transmission gate comprises PMOS transistor and NMOS transistor in parallel.

[0026] In this disclosure, inverter 106 in FIG. 1 is being replaced by a circuit which is capable of calibrating the optimal pulse width across the PVT (process, voltage, temperature). FIG. 2 shows this circuit in block format, where block 206 corresponds to the circuit shown in FIG. 3.

[0027] FIG. 3 illustrates a calibration circuit that is auto-calibrated to generate the precise pulses that are required for energy saving in the digital circuits according to an embodiment herein. The calibration circuit comprises one or more P-Channel Metal Oxide Semiconductor (PMOS), one or more N-Channel Metal Oxide Semiconductor (NMOS), a resistance divider 310, comparators 306 and 308, capacitor 316, and corresponding hardware to the logic 317 shown in illustrative box 327. The resistance divider 310 includes one or more resistors (e. g. a resistor R1 and a resistor R2). Comparator 308 obtains a first input from a mid-point or a reference point voltage of the resistor divider 310 and a second input from the capacitor 316. The capacitor 316 samples the input voltage (node 302) when the output of the XOR 318 is high.

[0028] The values of the resistors are arbitrary so that the ratio of R1 and R2 could be set to choose a particular trip voltage (also called threshold voltage). In an embodiment, the calibration circuit is Process, Voltage and Temperature (PVT) independent. In an embodiment, the auto-calibration circuit replaces the inverter 106 which is connected with one of the input terminals of the XOR gate present in the pulse generator circuit.

[0029] FIG. 3 further illustrates an auto-calibration circuit of the pulse generator circuit shown in FIG. 1 according to an embodiment herein. The circuit includes an inverter comprised of transistor 312 and transistor 314, one or more gated inverters 304A-304N, a first comparator 306, a second comparator 308 and a voltage divider circuit 310. The inverter comprised of transistor 312 and transistor 314 includes a PMOS 312 and a NMOS 314 that are connected together. The one or more gated inverters are connected together parallel with the inverter comprised of transistor 312 and transistor 314. The one or more gated inverters obtain the input bits B.sub.p and B.sub.n. In an embodiment, the PMOS of the one or more gated inverters 304A-304N are connected in parallel to the inverter comprised of transistor 312 and transistor 314 when the input bit (B.sub.p) of the one or more gated inverters 304A-304N is high. A NMOS of the one or more gated inverters 304A-304N are connected in parallel to the inverter comprised of transistor 312 and transistor 314 when the input bit (B.sub.n) of the one or more gated inverters 304A-304N is high. The first comparator 306 obtains one of its inputs from at least one of the inverter comprised of transistor 312 and transistor 314 and the one or more gated inverters 304A-304N. In an embodiment, an XOR gate 318 is connected with the first comparator 306 to generate the output n1x. The second comparator 308 obtains one of its inputs from the voltage divider circuit 310. In an embodiment, a capacitor 316 is connected with the second comparator 308 to provide the input. The capacitor 316 gets charged when n1x is high using a NMOS 320. In an embodiment, the number of one or more gated inverters 304A-304N is determined based on the requirement to cover a dynamic range of the auto-calibration circuit. In an embodiment, the dynamic range is nearly Vdd or equal to Vdd. In another embodiment, a (variable) dynamic range can range from Vdd to less than Vdd. In yet another embodiment, the dynamic range is set to be between zero and Vdd. Now, the count value of the pmos-counter enables the number of PMOS transistors of gated inverters 304A-304N. The count value of the nmos-counter enables the number of NMOS transistors in gated inverters 304A-304N. A pulse generator's pmos-counter increases its count when the output of the XOR 318 (following comparator 306) and comparator 308 are both high (i.e., 1 or logic one). The pulse generator's nmos-counter increases its value when the output of the XOR 318 (following comparator 306) is high and the output of comparator 308 is low (i.e. 0, or logic zero).

[0030] FIG. 4 illustrates an exploded view of a gated inverter of FIG. 3 according to an embodiment herein. The gated inverters 304A-304N includes an inverter 402, an OR gate 404, an AND gate 406, a PMOS 408 and a NMOS 410.

[0031] FIG. 5 represents the waveforms related to the calibration circuit shown in FIG. 3, according to an embodiment herein. The input voltage 502 (voltage at node 302 in FIG. 3) crosses the reference trip point at 508A, and the input waveform 502 and output waveform 504 cross at point 508B. The comparator and the XOR gate detects this timing difference between 508A and 508B, and this difference is shown as an output pulse of the XOR gate. The set of waveforms 508 and 510 shows the scenario where the pmos-counter is being increased and therefore increasing the number of PMOS transistors in parallel to the inverter (composed of transistor 312 and transistor 314) shifting the trip point to the target value. In another scenario, the set of waveforms 518 and 520, will cause the nmos-counter to increase, and therefore increase the number of NMOS transistors in parallel to the inverter (composed of transistor 312 and transistor 314) shifting the trip point to the target value. The description written in the logic box 316 describes the conditions fulfilled by the set of 508, 510, and the set of 518, 520 responsible for the pmos-counter and nmos-counter, respectively.

[0032] FIG. 6 is a flow diagram which illustrates a method of calibrating the pulse widths of a pulse generator circuit across the PVT using the calibration circuit shown in FIG. 3, according to an embodiment herein. At step 602, a pulse is generated to turn on a NMOS switch 320 using a first comparator 318. At step 604, a capacitor 316 is allowed to charge based on an input signal using the NMOS switch 320. At step 606, a second comparator output (nvx) is generated based on the input received from the capacitor 316 and a resistance divider 310 using a second comparator 308. At step 608, control bits are generated using one or more gated inverters 304A-304N for calibrating the pulse widths of a pulse generator 102 increasing a count-down value when the XOR signal is high and the second comparator output is low using a PMOS counter and a NMOS counter.

[0033] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments.