Abstract
A wideband, linear, direct-digital RF modulator (DDRM) for a digitally-intensive transmitter (DTX) includes an interpolation filter and an in-phase/quadrature (I/Q)-interleaving RF digital-to-analog converter (RF-DAC). The interpolation filter suppresses sampling replicas in the DDRM's output RF spectrum. I/Q interleaving performed by the interleaving RF-DAC avoids problems associated with using two separate I- and Q-path RF-DACs. Each unit cell of the interleaving RF-DAC is capable of producing four unique non-overlapping waveforms covering all four quadrants of the I/Q signal plane. In one embodiment of the invention, the interleaving RF-DAC includes three parallel-connected RF-DACs operating in accordance with a multi-phase set of LO clocks to both cancel 3.sup.rd-order and 5.sup.th-order LO harmonics generated by the RF-DAC unit cells' interleaving logic and prevent 3.sup.rd-order intermodulation from occurring in the DTX's final stage RF power amplifier.
Claims
1. A digital radio frequency (RF) modulator, comprising: an interpolation filter configured to upsample input I and Q digital baseband signals I.sub.BB and Q.sub.BB of sample rate F.sub.S to upsampled I and Q digital baseband signals I.sub.BB,UP and Q.sub.BB,UP of upsampled rate MF.sub.S, where M is an upsampling factor greater than one; a local oscillator (LO) clock signal generator configured to generate in-phase (I) and quadrature LO clock signals; and an interleaving RF digital-to-analog converter (RF-DAC) including a plurality of interleaving RF-DAC unit cells, each interleaving RF-DAC unit cell including first and second interleavers configured to upconvert and interleave I and Q bits in the upsampled I and Q digital baseband signals I.sub.BB,UP and Q.sub.BB,UP, in accordance with the I and Q LO clock signals, wherein the first and second interleavers of each interleaving RF-DAC unit cell comprises combinatorial logic that provides each interleaving RF-DAC unit cell the ability to generate four unique, non-overlapping I/Q waveforms covering all four quadrants of the I/Q signal plane.
2. The digital RF modulator of claim 1, wherein the I and Q LO clock signals generated by the LO clock signal generator have a duty cycle of 50%.
3. The digital RF modulator of claim 1, wherein: the combinatorial logic used in the first interleaver of each interleaving RF-DAC unit cell comprises a first exclusive NOR (XNOR) logic gate configured to receive the I LO clock signal and I bits in the upsampled I and Q digital baseband signals I.sub.BB,UP and Q.sub.BB,UP, a second XNOR logic gate configured to receive the Q LO clock signal and Q bits in the upsampled I and Q digital baseband signals I.sub.BB,UP and Q.sub.BB,UP, and a first OR logic gate with inputs connected to the outputs of the first and second XNOR logic gates, or the De Morgan equivalent of the combination of first and second XNOR logic gates and first OR logic gate, and the combinatorial logic used in the second interleaver of each interleaving RF-DAC unit cell comprises a first exclusive OR (XOR) logic gate configured to receive the I LO clock signal and I bits in the upsampled I and Q digital baseband signals I.sub.BB,UP and Q.sub.BB,UP, a second XOR logic gate configured to receive the Q LO clock signal and Q bits in the upsampled I and Q digital baseband signals I.sub.BB,UP and Q.sub.BB,UP, and a second OR logic gate with inputs connected to the outputs of the first and second XOR logic gates, or the De Morgan equivalent of the combination of first and second XOR logic gates and second OR logic gate.
4. The digital RF modulator of claim 1, wherein each interleaving RF-DAC unit cell further includes first and second current sources controlled by complementary interleaved digital RF signals IQ.sup.+ and IQ.sup. produced by the first and second interleavers.
5. The digital RF modulator of claim 4, wherein the first and second current sources are fully-differential current sources.
6. The digital RF modulator of claim 4, wherein the combinatorial logic of the first and second interleavers comprises current-mode logic.
7. The digital RF modulator of claim 1, wherein each RF-DAC unit cell further includes first and second transistors that serve as switched resistors and which are controlled by complementary interleaved digital RF signals IQ.sup.+ and IQ.sup. produced by the first and second interleavers.
8. The digital RF modulator of claim 1, wherein the interpolation filter comprises a 2.sup.nd-order hold (SOH) or higher-order hold polyphase interpolation filter with upsampling factor M.
9. The digital RF modulator of claim 8, wherein the SOH or higher-order hold polyphase interpolation filter comprises a plurality parallel sub-filters that operate at sample rate F.sub.S and I and Q output multiplexers that operate at upsampled rate MF.sub.S.
10. The digital RF modulator of claim 1, wherein the RF-DAC comprises a plurality of RF-DACs connected in parallel, the LO clock signal generator comprises a multi-phase LO clock signal generator, and the plurality of parallel-connected RF-DACs is controlled by the multi-phase LO clock signal generator to cancel or substantially suppress LO harmonic emissions.
11. A digital radio frequency (RF) modulator, comprising: a multi-phase local oscillator (LO) clock signal generator; and a plurality of RF digital-to-analog converters (RF-DACs) connected in parallel configured to upconvert digital input I and Q baseband signals to RF and produce an analog RF waveform from the upconverted RF digital I and Q signals, wherein the plurality of parallel-connected RF-DACs is controlled by the multi-phase LO clock signal generator to cancel or substantially suppress LO harmonic emissions, wherein: the multi-phase LO clock signal generator is configured to generate a first pair of in-phase (I) and quadrature (Q) LO clock signals, a second pair of I and Q LO clock signals that is forty-five degrees out of phase with respect to the first pair of I and Q LO clock signals, and a third pair of I and Q LO clock signals that is forty-five degrees out of phase with respect to the second pair of I and Q LO clock signals, the plurality of parallel-connected RF-DACs includes first, second, and third parallel-connected RF-DACs, and the first RF-DAC is controlled by the first pair of I and Q LO clock signals, the second RF-DAC is controlled by the second pair of I and Q LO clock signals, and the third RF-DAC is controlled by the third pair of I and Q LO clock signals to cancel or substantially suppress 3.sup.rd-order and 5.sup.th-order LO emissions.
12. The digital RF modulator of claim 11, wherein each of the RF-DACs in the plurality of parallel-connected RF-DACs comprises an interleaving RF-DAC having a plurality of interleaving RF-DAC unit cells.
13. The digital RF modulator of claim 11, wherein the multi-phase LO clock signal generator is configured to generate a multi-phase set of LO clock signals, each having a duty cycle of 50%.
14. The digital RF modulator of claim 11, wherein the I and Q LO clock signals have a duty cycle of 50% and each RF-DAC unit cell comprises combinatorial logic that provides each RF-DAC unit cell the ability to generate four unique, non-overlapping I/Q waveforms covering all four quadrants of the I/Q signal plane.
15. The digital RF modulator of claim 12, wherein each interleaving RF-DAC unit cell comprises: a first interleaver including a first exclusive NOR (XNOR) logic gate, a second XNOR logic gate, and a first OR logic gate with inputs connected to the outputs of the first and second XNOR logic gates, or the De Morgan equivalent of the combination of first and second XNOR logic gates, and first OR logic gate; and a second interleaver including a first exclusive OR (XOR) logic gate, a second XOR logic gate, and a second OR logic gate with inputs connected to the outputs of the first and second XOR logic gates, or the De Morgan equivalent of the combination of first and second XOR logic gates, and second OR logic gate.
16. The digital RF modulator of claim 15, wherein each interleaving RF-DAC unit cell further includes first and second current sources controlled by complementary interleaved digital RF signals IQ.sup.+ and IQ.sup. produced by the first and second interleavers.
17. The digital RF modulator of claim 11, further comprising an interpolation filter configured to upsample the digital input I and Q baseband signals to an upsampled rate of upsampling factor Msample rate F.sub.S before being directed to the first, second, and third parallel-connected RF-DACs.
18. The digital RF modulator of claim 17, wherein the interpolation filter comprises a 2.sup.nd-order hold (SOH) or higher-order hold polyphase interpolation filter.
19. The digital RF modulator of claim 18, wherein the SOH or higher-order hold polyphase interpolation filter comprises a plurality of sub-filters connected in parallel that operate at sample rate F.sub.S and I and Q output multiplexers that operate at upsampled rate MF.sub.S.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1 is a drawing that shows the primary components of a radio frequency (RF) transmitter;
(2) FIG. 2 is drawing that shows the basic components of a prior art digitally-intensive RF transmitter (DTX);
(3) FIG. 3 is a drawing that conceptually illustrates how the in-phase (I) and quadrature (Q) RF-DACs in the direct-digital RF modulator (DDRM) of the DTX depicted in FIG. 2 operate;
(4) FIG. 4A is a simplified drawing of the DDRM output RF spectrum that can result when a DDRM is operated without baseband and RF filters in a wideband or multi-band, carrier aggregation environment, such as Long Term Evolution Advanced (LTE-Advanced);
(5) FIG. 4B is a simplified drawing of an output RF spectrum that can appear at the output of the RF power amplifier (RF PA) of a DTX like that depicted in FIG. 2 when the DTX and its DDRM are operated without baseband and RF filters in a wideband or multi-band, carrier aggregation environment, highlighting how local oscillator (LO) 3.sup.rd harmonics produced by the DDRM can intermodulate with the LO fundamental component when passing through the RF PA and produce undesirable counter-intermodulation distortion (C-IMD3);
(6) FIG. 5 is a simplified drawing of a digitally-intensive transmitter (DTX), according to an embodiment of the present invention;
(7) FIG. 6 is a block diagram of the in-phase portion of an exemplary 2.sup.nd-order hold (SOH) polyphase interpolation filter that may be used in the DDRM of the DTX depicted in FIG. 5;
(8) FIG. 7 is a simplified block diagram of the SOH polyphase interpolation filter depicted in FIG. 6, highlighting the fact that the filter core operates at a low sample rate of F.sub.s and only the I and Q output multiplexers of the filter operate at the upsampled rate of MF.sub.s;
(9) FIG. 8 is a more detailed depiction of the interleaving RF-DAC in the DDRM of the DTX depicted in FIG. 5;
(10) FIG. 9 is a drawing that conceptually illustrates the interleaving, frequency upconversion, and digital-to-analog conversion operations performed by the interleaving RF-DAC in the DDRM of the DTX depicted in FIG. 5;
(11) FIG. 10 is a schematic drawing of the circuitry used to implement each of the interleaving RF-DAC unit cells of the interleaving RF-DAC depicted in FIG. 8, in accordance with one embodiment of the invention;
(12) FIG. 11 is a drawing that illustrates how the XOR/OR combinatorial logic of the interleavers in the interleaving RF-DAC unit cell depicted in FIG. 10 is capable of producing four unique, 25% duty cycle, non-overlapping output waveforms covering all four quadrants of the I/Q signal plane;
(13) FIG. 12 is a schematic drawing of an interleaving RF-DAC unit cell, in accordance with one embodiment of the invention, that uses current-mode logic to form the XOR/OR combinatorial logic of the interleavers in the interleaving RF-DAC unit cell depicted in FIG. 10;
(14) FIG. 13 is a schematic drawing of an interleaving RF-DAC, in accordance with another embodiment of the invention, that utilizes a global cascoding approach, instead of the local cascoding approach used by the RF-DAC unit cell depicted in FIG. 12;
(15) FIG. 14 is a schematic drawing of an interleaving RF-DAC, in accordance with another embodiment of the invention, that relies on the ON and OFF resistances of switching transistors 1402 to perform digital-to-analog conversion and does not require the use of current sources;
(16) FIG. 15 is a schematic drawing of an interleaving RF-DAC unit cell, in accordance with another embodiment of the invention, that uses fully-differential switched current sources, rather than the pseudo-differential switched current source approaches used by the exemplary RF-DAC unit cells depicted in FIGS. 12-14;
(17) FIG. 16 is a drawing depicting a DDRM that utilizes an LO harmonic cancellation technique to suppress third- and fifth-order LO harmonics, in accordance with another embodiment of the invention;
(18) FIG. 17 is a signal diagram showing the phase relationships among the multi-phase set of LO clock signals CK.sub.0/90, CK.sub.45/135 and CK.sub.90/180 produced by the multi-phase LO clock signal generator of the DDRM depicted in FIG. 16;
(19) FIG. 18 is a signal diagram illustrating how controlling the three interleaving RF-DACs in the DDRM depicted in FIG. 16 by the multi-phase set of LO clock signals CK.sub.0/90, CK.sub.45/135 and CK.sub.90/180 is, in effect, equivalent to controlling a single interleaving RF-DAC by a single quantized pair of in-phase and quadrature sinusoids;
(20) FIG. 19 is a drawing that vectorially illustrates the LO cancellation technique performed by the parallel-connected RF-DACs of the DDRM depicted in FIG. 16;
(21) FIG. 20 is an idealized output RF spectrum of the DDRM depicted in FIG. 16, highlighting how the LO cancellation technique performed by the parallel-connected RF-DACs of the DDRM serves to cancel copies of the baseband signal that would otherwise appear in the output frequency spectrum; and
(22) FIG. 21 depicts an output RF spectrum of a DTX that lacks any RF filtering or LO cancellation capability, highlighting how the presence of the third-order LO harmonic at the input of the DTX's RF PA results in undesirable C-IMD3 near the intended/desired transmission band.
DETAILED DESCRIPTION
(23) Referring to FIG. 5, there is shown a digitally-intensive transmitter (DTX) 500, according to an embodiment of the present invention. The DTX 500 comprises a digital radio frequency (RF) modulator (DDRM) 502 that includes an interpolation filter 504 and interleaving RF-DAC 506; a clock signal generator 508; an RF power amplifier (RF PA) 510; and an antenna 512. The DTX 500 in this exemplary embodiment of the invention is a direct-conversion transmitter, meaning that the interleaving RF-DAC 506 interleaves and translates the digital input in-phase (I) and quadrature (Q) baseband signals directly to RF, without an intermediate frequency conversion step. While a direct-conversion DTX architecture is preferred, the methods and apparatus of the present invention could be modified or adapted for use in an indirect-conversion DTX architecture. In such an approach the interleaving RF-DAC 506 would interleave and translate the I and Q baseband signals to some intermediate frequency, and a subsequent analog RF mixer would then upconvert the IF waveform to the final desired RF carrier frequency.
(24) The interpolation filter 504 of the DDRM 502 in the DTX 500 serves to upsample the N-bit digital input I and Q digital baseband signals of sample rate F.sub.s to an upsampled rate f.sub.c=f.sub.LO=MF.sub.s, where N is the number of bits in (i.e., resolution op the digital input I and Q input baseband signals, M is the upsampling factor, and f.sub.c=f.sub.LO is the frequency of the DDRM local oscillator (LO) clocks provided by the clock signal generator 508. The interpolation filter 504 also serves as a digital low-pass filter (LPF) with a cut-off frequency designed to suppress sampling replicas in the DDRM's RF output spectrum. The sampling frequency F.sub.s and the upsampling factor M are selected during design to realize a desired combination of replica separation, data path power consumption, and filter complexity.
(25) In one embodiment of the invention, the interpolation filter 504 comprises a 2.sup.nd-order hold (SOH) polyphase interpolation filter with an upsampling factor of M=4. As illustrated in FIG. 6, the SOH polyphase interpolation filter 504 comprises four parallel finite impulse response (FIR) sub-filters and contains no multipliers. (Note that only the in-phase portion of the filter is shown in FIG. 6. The quadrature portion has a substantially similar construction.) As better indicated in FIG. 7, the four parallel FIR sub-filters are configured to operate at the lower sample rate of F.sub.s and only output multiplexers 704 and 706 operate at 4F.sub.s. The lower sampling rate F.sub.s used by the filter core 702 minimizes the filter's overall power consumption yet still allows the input I and Q the N-bit digital input I and Q digital baseband signals I.sub.BB[(N1):0] and Q.sub.BB[(N1):0] to be upsampled to the desired upsample rate 4F.sub.s. It should be mentioned that whereas a SOH interpolation filter is employed in this particular exemplary embodiment of the invention, interpolation filters of even higher order can be alternatively used, such as a 3rd-order hold, for example.
(26) FIG. 8 is a more detailed depiction of the interleaving RF-DAC 506 of the DDRM 502. The interleaving RF-DAC 506 comprises a plurality (or array) of interleaving RF-DAC unit cells 802 that share a common output and collectively operate according to the current-steering principle. In this exemplary embodiment of the invention the interleaving RF-DAC 506 is segmented, with a first plurality 802A of the plurality of interleaving RF-DAC unit cells 802 being thermometer-coded interleaving RF-DAC unit cells 804 and a second plurality 802B of the plurality of interleaving RF-DAC unit cells 802 being binary-coded interleaving RF-DAC unit cells 806. The N.sub.T most significant bits (MSBs) of the upsampled N-bit digital I and Q digital baseband signals I.sub.BB-UP and Q.sub.BB-UP (shown as I/Q bit pairs I[0],Q[0], I[1],Q[1], . . . , I[N1],Q[N1] in FIG. 8) are converted to thermometer code by a binary-to-thermometer decoder 808, and the resulting thermometer-coded I and Q signals are used to steer the 2.sup.N.sup.T1 thermometer-coded interleaving RF-DAC unit cells 804. The remaining N.sub.B least significant bits (LSBs) of the upsampled N-bit digital I and Q digital baseband signals I.sub.BB-UP and Q.sub.BB-UP require no decoding and consequently directly steer the N.sub.B binary-coded RF-DAC unit cells 806. Here, N=N.sub.T+N.sub.B represents the resolution of the interleaving RF-DAC 506. For example, for a resolution of N=9, N.sub.T=6, and N.sub.B=3, the interleaving RF-DAC 506 would include 63 interleaving thermometer-coded RF-DAC unit cells 804 (each having a current source of the same size I.sub.0) and 3 interleaving binary-coded RF-DAC unit cells 806 (with weighted current sources of I.sub.0/2, I.sub.0/4, and I.sub.0/8). It should be mentioned that, although a segmented RF-DAC approach is preferred, since it provides the ability to realize an optimal balance of decoding logic design complexity, layout efficacy, size, linearity, and glitch energy tolerance, a non-segmented approach comprising an all-thermometer-coded RF-DAC array or an all-binary-coded RF-DAC array could be alternatively used.
(27) FIG. 9 is a drawing that illustrates the interleaving, frequency upconversion, and digital-to-analog conversion operations performed by the interleaving RF-DAC 506. Conceptually, the interleaving RF-DAC 506 comprises an N-bit digital I/Q modulator 902 followed by an N-bit current-steering DAC 904. The N-bit digital IQ modulator 902 mixes the upsampled N-bit digital I and Q digital baseband signals I.sub.BB-UP and Q.sub.BB-UP produced by the interpolation filter 504 with RF in-phase and quadrature LO clocks CK and CK.sub.Q provided by the clock signal generator 508. The I and Q LO clocks CK and CK.sub.Q are 90 out of phase, so the resulting RF-translated signal is an interleaved RF digital IQ signal IQ.sub.RF. The interleaved RF digital IQ signal IQ.sub.RF is then introduced to the current-steering DAC 904, which converts the upconverted digital samples to the final desired modulated analog RF waveform RF.sub.OUT. (Note that the interleaving RF-DAC 506 may or may not be designed to amplify the analog RF waveform. This design option is indicated in FIG. 9 by the RF PA 906 shown in dashed lines. If desired or necessary, a PA external to the RF-DAC 506 can then be used to amplify (or further amplify) the analog RF waveform RF.sub.OUT produced at the output of the RF-DAC 506.)
(28) One significant advantage the interleaving RF-DAC 506 has over conventional RF-DAC architectures like that depicted in FIGS. 2 and 3 above, is that the I and Q data bits produced by the digital I/Q modulator in each interleaving RF-DAC unit cell are interleaved, i.e., are time-multiplexed. This allows the I and Q bits in the interleaved RF digital IQ signal IQ.sub.RF in each RF-DAC unit cell to share the same DAC circuitry (and PA if the RF-DAC 506 is also designed to amplify). Combining the upconverted I and Q signals in the digital domain also effectively reduces the DAC and RF PA resources to half that which is required in conventional, non-interleaved RF-DAC architectures like that depicted in FIGS. 2 and 3. The reduced number of required resources not only provides a more energy efficient solution, it results in a much smaller IC footprint for the overall RF-DAC 506, less parasitics, and better image rejection capability since I-path/Q-path mismatch in each unit cell is practically eliminated.
(29) FIG. 10 is a schematic drawing of the actual circuitry used to implement each of the interleaving RF-DAC unit cells in the interleaving RF-DAC 506, in one embodiment of the invention. Each interleaving RF-DAC unit cell 1002 is representative of one of the thermometer-coded interleaving RF-DAC unit cells 804 in the first plurality of interleaving RF-DACs 802A in FIG. 8 or one of the interleaving binary-coded RF-DAC unit cells 806 in the second plurality of interleaving RF-DACs 802B. The interleaving RF-DAC unit cell 1002 includes a first interleaver 1004, a second (complementary) interleaver 1006, first and second switches 1008 and 1010, and first and second current sources 1012 and 1014 connected in series with the first and second switches 1008 and 1010. The first interleaver 1004 comprises first and second exclusive OR (XOR) logic gates 1016 and 1018 and a NAND logic gate 1020 (or their collective De Morgan equivalent), and the second interleaver 1006 comprises first and second exclusive NOR (XNOR) logic gates 1022 and 1024 and a NAND logic gate 1026 (or their collective De Morgan equivalent). The first and second interleavers 1004 and 1006 translate the I and Q data bits D.sub.I and D.sub.Q to RF to produce interleaved RF drive signals IQ.sup.+ and IQ.sup., which control the ON/OFF status of the first and second switches 1008 and 1010. All of the other interleaving RF-DAC unit cells 1002 in the interleaving RF-DAC array 802 operate on their respective I and Q bit streams in a similar manner. The output currents I.sub.OUT+ and I.sub.OUT of all interleaving RF-DAC unit cells are summed at a common output, similar to as in a conventional current-steering DAC, and the total output current varies depending on the bit patterns in the I and Q bit streams directed to each unit cell, thus allowing the interleaving RF-DAC 506 to produce 2.sup.N distinct output levels.
(30) The I and Q bits applied to each interleaving RF-DAC unit cell 1002 do not have the same value at the same time. It is this exclusivity that allows the I and Q bits to be interleaved (i.e., time-multiplexed) and for the I and Q bits in the interleaved I and Q bit streams to then share the same DAC resources. As shown in FIG. 11, due to the unique XOR/OR combinatorial logic used for the interleavers 1004 and 1006, each interleaving RF-DAC unit cell 1002 is capable of producing four unique, 25% duty cycle, non-overlapping output waveforms covering all four quadrants of the I/Q signal plane, even while using LO clocks CK.sub.I and CK.sub.Q having a duty cycle D=50%. This capability avoids having to introduce complicated clipping circuitry to address I/Q waveform overlap. It also avoids having to generate LO clocks of less than 50%, which is difficult to realize, particularly at GHz frequencies, and which results in a significant increase in power consumption.
(31) In one embodiment of the invention the XOR/OR logic of the interleavers 1004 and 1006 is implemented using current-mode logic, by stacking it on top of current sources 1202, as illustrated in the exemplary interleaving RF-DAC unit cell 1200 depicted in FIG. 12. Stacking the XOR/OR current-mode logic on top of the current sources 1202 allows faster switching operation. It also allows the I and Q bits in each complementary IQ-interleaved bit stream to share the same current source (i.e., to reuse the current I.sub.0), resulting in a smaller unit-cell size and lower power consumption than if sharing was not possible. Transistors 1204 in the unit cell 1200 serve to shield the switching transistors in the XOR/OR current-mode logic from parasitic capacitances present on the drains of the current sources 1202 and consequently help to achieve and maintain linearity at high frequencies. Thick-oxide cascode transistors 1206 above the current-mode logic interleavers 1004 and 1006 are employed to withstand large voltage swings at the output nodes and to reduce interaction between DAC branches. Alternatively, a global cascoding approach using global cascode transistors 1302 may be used, as illustrated in FIG. 13.
(32) The interleaving RF-DAC unit cells depicted in FIGS. 12 and 13 employ what may be referred to as pseudo-differential switched current sources. An advantage of this pseudo-differential switched-current approach is that it reduces the number of logic gates required for each complementary half of each interleaving RF-DAC unit cell. Unit cell size could be further reduced by eliminating the current sources and relying instead on the difference between the ON and OFF resistance of switching transistors 1402, as illustrated in FIG. 14. According to that approach, the drains of all switching transistors 1402 in the RF-DAC array share the same output and those switching transistors 1402 that are switched ON at any given time are connected in parallel. Hence, depending on whether the transistors 1402 in each cell are ON or OFF, as determined by whether the values of the I and Q bits in their respective interleaved IQ data streams is high or low, the RF-DAC array 802 would then produce an analog RF waveform having a bit-to-bit amplitude that depends on the summed output conductances of all RF-DAC unit cells in the array 802. While the pseudo-differential/switched resistor approach in FIG. 14 has a size advantage because of not requiring current sources, the pseudo-differential/shared current source approach in FIG. 12 or FIG. 13 is preferred since by using current sources the output resistance of the RF-DAC array remains essentially constant, i.e., does not vary significantly depending on the bit patterns of the I and Q bits in the RF-DACs' interleaved IQ data streams. Finally, it should be mentioned that, although the pseudo-differential approach in FIG. 12 or FIG. 13 is preferred, a fully-differential approach with fully-differential switched current sources, such as depicted in FIG. 15, could be alternatively used. (Note that the XOR/OR logic used for the interleavers in FIG. 15 could be constructed using XOR/OR current-mode-logic, similar to as explained above, without any current sources at the bottoms of the associated logic gate.)
(33) The DDRM 502 described above provides an acceptable solution for some applications. However, it does not address the problem of LO harmonic emissions caused by the switching logic (e.g., by the interleavers 1004 and 1006 in the interleaving RF-DAC unit cells). As was explained above in reference to FIG. 4A, LO-harmonic-related emissions are undesirable since they contribute to out-of-band noise and make it difficult to comply with out-of-band emission requirements. In conventional DDRM approaches, pre-PA and/or post-PA band-pass filter (BPFs) is/are typically employed in an effort to suppress the LO harmonics. Unfortunately, the RF BPFs are not entirely effective at suppressing the LO harmonic emissions. Moreover, because the RF BPFs are not entirely effective, 3.sup.rd-order LO harmonic counter-intermodulation distortion (C-IMD3) results, as was illustrated in FIG. 4B. FIG. 16 is a drawing depicting a DDRM 1600 according to another embodiment of the invention that addresses these problems, without having to rely on the unsatisfactory performance of pre-PA and post-PA RF BPFs. The DDRM 1600 comprises an interpolation filter 1602 (in this exemplary embodiment a SOH polyphase interpolation filter similar to that described above in reference to FIGS. 6 and 7); a multi-phase LO clock signal generator 1604; and an RF-DAC 1606 comprised of three parallel-connected interleaving RF-DACs 1608, 1610 and 1612. (Note that non-interleaving RF-DACs may be used in this embodiment of the invention, i.e., instead of interleaving RF-DACs 1608, 1610 and 1612; however the interleaving RF-DACs 1608, 1610 and 1612 are preferred due to the various advantages that they offer.) Comparing FIG. 16 to FIG. 5, it is seen that the DDRM 1600 is similar in construction to the DDRM 502, except that the interleaving RF-DAC 1606 is constructed from a plurality of parallel-connected interleaving RF-DACs 1608, 1610 and 1612 that operate in accordance with a multi-phase set of LO clock signals: CK.sub.0/90, CK.sub.45/135 and CK.sub.90/180, rather than a single interleaving RF-DAC 506 operating in accordance with I and Q LO clocks CK.sub.I and CK.sub.Q. Each of the three interleaving RF-DACs 1608, 1610 and 1612 may be constructed using any one of the various unit cell architectures described above. Note that if a global cascoding architecture is adopted (for example similar to as the unit cell depicted in FIG. 13), the three global cascode transistor pairs of the parallel-connected RF-DACs 1608, 1610 and 1612 can be merged into a single cascode transistor pair.
(34) FIG. 17 is a signal diagram showing the phase relationships among the multi-phase set of LO clock signals: CK.sub.0/90, CK.sub.45/135 and CK.sub.90/80. The LO clock signals CK.sub.0, CK.sub.45 and CK.sub.90 are the in-phase clocks applied to the I inputs of the interleaving RF-DACs 1608, 1610 and 1612 and the LO clock signals CK.sub.90, CK.sub.135, CK.sub.180 are the quadrature clocks applied to the Q inputs of the interleaving RF-DACs 1608, 1610 and 1612. Each of the in-phase LO clock signals CK.sub.0, CK.sub.45 and CK.sub.90 has a 45 phase difference with respect to the other two in-phase LO clock signals. Similarly, each of the quadrature LO clock signals CK.sub.90, CK.sub.135, CK.sub.180 has a 45 phase difference with respect to the other two quadrature LO clock signals. Because the three interleaving RF-DACs 1608, 1610 and 1612 are connected in parallel, controlling the three interleaving RF-DACs 1608, 1610 and 1612 according to the multi-phase set of LO clock signals: CK.sub.0/90, CK.sub.45/135 and CK.sub.90/180 is, in effect, equivalent to controlling a single interleaving RF-DAC by a single quantized pair of in-phase and quadrature sinusoids, such as illustrated in FIG. 18.
(35) It can be shown that when each of the in-phase LO clock signals CK.sub.0, CK.sub.45 and CK.sub.90 and each of the quadrature LO clock signals CK.sub.90, CK.sub.135, CK.sub.180 is expressed in a Fourier series and summed the 3.sup.rd-order and 5.sup.th-order harmonics cancel. This LO cancellation is illustrated vectorially in the vector diagrams in FIG. 19, where the 3.sup.rd-order and 5.sup.th-order harmonics are referred to by their angular frequencies 3.sub. and 5.sub.. Canceling the 3.sup.rd-order and 5.sup.th-order harmonics 3.sub. and 5.sub. leaves only the desired copy of the upconverted baseband signal centered at the fundamental frequency =f.sub.LO2 . (Note that to resemble a sinusoid as best possible, the magnitude of the current source used in the middle interleaving RF-DAC 1610 is scaled by a factor of 2. Alternatively, this 2 multiplying operation can be performed in the corresponding I/Q baseband signals, in which case the magnitude of the middle current source would be the same as the others.)
(36) It should be mentioned that the LO cancellation technique described above is not limited to cancelling 3.sup.rd-order and 5.sup.th-order harmonics, in other words, can be extended to cancel higher-order harmonics. For example, 7.sup.th-order to 15.sup.th-order harmonics could be canceled by using a set of eight multi-phase LO clock signals.
(37) FIG. 20 shows an idealized output frequency spectrum produced at the output of the parallel-connected RF-DAC 1606, highlighting how controlling the parallel-connected RF-DAC 1608, 1610 and 1612 by the multi-phase set of LO clock signals: CK.sub.0/90, CK.sub.45/135 and CK.sub.90/180 serves to cancel the copies of the baseband signal that would otherwise appear in the output DDRM's output RF spectrum. By using the LO harmonic cancellation technique the need for pre-PA and post-PA RF BPFs is obviated (or at least simplifies the design complexity of any RF BPFs that may be used). Moreover, since the 3.sup.rd LO harmonic is canceled, C-IMD3, which would otherwise be generated due to intermodulation of the fundamental and 3.sup.rd LO harmonic components in the DDRM's external RF PA, is almost completely avoided. In the absence of any RF filtering and LO cancellation, a DTX output RF spectrum similar to that depicted in FIG. 21 would be produced.
(38) While various embodiments of the present invention have been presented, they have been presented by way of example and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail may be made to the exemplary embodiments without departing from the true spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the specifics of the exemplary embodiments of the invention but, instead, should be determined by the appended claims, including the full scope of equivalents to which such claims are entitled.
