Back-side illuminated image sensor

Abstract

A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

Claims

1. A back-side illuminated image sensor, comprising memory regions formed in a semiconductor wafer, each memory region being located between two opaque walls which extend into the semiconductor wafer from a rear surface of the semiconductor wafer and are in contact with an opaque screen arranged at the rear surface of the semiconductor wafer to cover the memory region, wherein each opaque wall is separated from the memory region by a polysilicon layer.

2. The sensor of claim 1, wherein, for each memory region, the opaque walls and the opaque screen are conductive and are configured for connection to a node of application of a bias potential.

3. The sensor of claim 1, wherein the opaque walls and the opaque screen are made of tungsten and the opaque walls have a thickness in the range from 50 to 200 nm.

4. The sensor of claim 1, wherein the opaque walls are separated from the memory region by a layer of hafnium oxide.

5. The sensor of claim 1, wherein the polysilicon layer is separated from the memory region by a silicon oxide layer.

6. The sensor of claim 5, wherein the opaque walls are separated from the polysilicon layer by a layer of hafnium oxide.

7. A back-side illuminated image sensor, comprising: a semiconductor wafer having a front surface and a rear surface; a pair of trenches extending completely through the semiconductor wafer between the front and rear surfaces, said pair of trenches delimiting a memory region within the semiconductor wafer for a pixel that receives light through the rear surface; a layer of polysilicon material on side walls of each trench and at a front of the trench adjacent the front surface; an opaque wall in each trench, the opaque wall surrounded inside the trench by the layer of polysilicon material; and an opaque screen arranged at the rear surface of the semiconductor wafer to cover the memory region and in contact with each opaque wall.

8. The sensor of claim 7, wherein the opaque walls and the opaque screen are made of an electrically conductive material.

9. The sensor of claim 8, wherein the electrically conductive material is tungsten.

10. The sensor of claim 7, further comprising a layer of hafnium oxide positioned between the opaque wall and the memory region.

11. The sensor of claim 7, further comprising layer of silicon oxide positioned between the layer of polysilicon material and the memory region.

12. The sensor of claim 11, further comprising a layer of hafnium oxide positioned between the opaque wall and the layer of polysilicon.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, wherein:

(2) FIGS. 1 to 9 are partial simplified cross-section views illustrating steps of an embodiment of a method of manufacturing a back-side illuminated image sensor, FIG. 9 illustrating the obtained sensor; and

(3) FIGS. 10 to 13 are partial simplified cross-section views illustrating steps of another embodiment of a method of manufacturing a back-side illuminated image sensor, FIG. 13 illustrating the obtained sensor.

DETAILED DESCRIPTION

(4) The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, conductive interconnection lines and elements such as transistors and photodiodes are not shown.

(5) In the following description, when reference is made to terms qualifying the absolute position, such as terms left, right, etc. or the relative position, such as terms upper, lower, etc., reference is made to the orientation of the concerned element in the corresponding drawings. Unless otherwise specified, expression in the order of means to within 10%, preferably to within 5%.

(6) FIGS. 1 to 9 are simplified cross-section views illustrating an embodiment of a back-side illuminated image sensor at successive steps of its manufacturing. The sensor comprises a pixel array, and the manufacturing of a single one of these pixels and of portions of neighboring pixels has been shown.

(7) At the step of FIG. 1, the front surface has been covered with a semiconductor wafer 1, for example, made of silicon, with an etch stop layer 3, for example, made of silicon oxide, and then with a silicon nitride masking layer 5. Trenches 7 have been etched in semiconductor wafer 1. Trenches 7 are arranged in pairs on either side of regions 9 of wafer 1 which correspond to future memory regions. A pair of trenches 7 and the associated region 9 are visible in the left-hand portion of FIG. 1. Memory region 9 preferably has an elongated shape in the direction orthogonal to the plane of the drawings. Each pixel comprises a photodiode which will be formed in a region 11 located outside of the pairs of trenches 7.

(8) An electrically-insulating layer 13 of small thickness, for example, made of silicon oxide, has then been conformally deposited. Layer 13 covers the lateral walls and the bottom of trenches 7.

(9) A polysilicon layer 15 is then conformally deposited on the front surface. Layer 15 covers, in particular, the portions of layer 13 located in the trenches. Layers 13 and 15 have a total thickness smaller than half that of trenches 7, so that there remain recesses 17 at the heart of trenches 7. As a variation, layer 15 may be omitted.

(10) As an example, trenches 7 have a width in the order of 200 nm. Trenches 7 may extend into the wafer down to a depth in the range from 3 to 10 m, for example, 6 m. Insulating layer 13 may have a thickness in the range from 5 to 20 nm, for example, 12 nm. Recesses 17 may have a width in the range from 50 to 200 nm, for example, 70 nm.

(11) At the step of FIG. 2, a silicon nitride layer 20 is deposited on the front surface to fill recesses 17.

(12) At the step of FIG. 3, silicon nitride layer 20 is removed, for example, by a wet etching, with an etching time provided so that there remain silicon nitride sacrificial walls 30 in recesses 17. As an example, sacrificial walls 30 fill recesses 17 up to a level located at a depth in the range from 50 to 150 nm under the front surface of wafer 1.

(13) At the step of FIG. 4, the portions 40 of recesses 17 which have remained empty have been filled with polysilicon. All the elements located on the front surface above the level of etch stop layer 3 have been removed by chemical-mechanical polishing.

(14) Doping steps are then carried out, in particular for the forming of memory regions 9 and of photodiode regions 11, as well as for the forming of various transistors such as transfer, read, or reset transistors. These steps may be implemented due to the fact that the deep trenches, which imply a high thermal budget for their manufacturing, have already been formed and filled. During these steps, sacrificial walls 30 may be submitted to high temperatures during anneal steps. Sacrificial walls 30 advantageously resist these steps due to their being made of silicon nitride. Further, layers 13 and 15 which cover the sides of sacrificial walls 30 enable to avoid any risk for nitrogen atoms originating from the sacrificial walls to reach memory regions 9 or photodiode regions 11.

(15) A protection layer 42, for example, made of silicon nitride, and an insulation layer 44, for example, made of silicon oxide, are then deposited. Layers 46 comprising interconnection lines are formed on layer 44.

(16) At the step of FIG. 5, the wafer has been flipped. The rear surface or back side is now located in the upper portion of FIGS. 5 to 9. Memory region 9 and the associated trenches 7 are located in the right-hand portion. The elements located above the level of sacrificial walls 30 are then removed, for example, by chemical-mechanical polishing of the rear surface, so that the sacrificial walls are flush with the polished rear surface.

(17) At the step of FIG. 6, sacrificial walls 30 are removed. Due to the fact that sacrificial walls 30 are made of silicon nitride, sacrificial walls 30 may advantageously be easily removed by selective wet etching in the example where the only other materials present on the back side are silicon and silicon oxide. Such a selective wet etching may be performed by a phosphoric acid solution H.sub.3PO.sub.4. Recesses 60 are obtained at the locations of sacrificial walls 30.

(18) At the step of FIG. 7, a layer 70 made of a positively-charged passivation material, such as hafnium oxide HfO.sub.2, is deposited. Layer 70 covers the rear surfaces of memory regions 9 and of photodiode 11, and covers the walls and the bottom of recesses 60. Silicon oxide is then deposited on layer 70. The deposition is non-conformal, that is, it mainly covers the surfaces oriented towards the back side. One thus forms, in addition to portions 72 on the bottoms of recesses 60, a silicon oxide layer 74 which exhibits an opening 76 at the level of each recess.

(19) As an example, layer 70 has a thickness in the range from 4 to 10 nm. Layer 74 may have a thickness in the range from 30 to 40 nm. As a variation, layer 70 may be omitted.

(20) At the step of FIG. 8, recesses 60 are filled with an opaque material, that is, a material having an optical extinction coefficient greater than 1, for example, tungsten. The filling is performed via openings 76, for example, by a tungsten deposition on the rear surface, followed by a chemical-mechanical polishing down all the way to layer 74. Layer 74 is then used as a polishing stop layer. Opaque walls 80 flush with the surface of layer 74 are obtained. Opaque walls 80 have their sides covered with layer 70.

(21) According to an advantage of the method described herein, due to the fact that the tungsten deposition is performed after the step of forming the transistors discussed in relation with FIG. 4, and particularly after the anneal steps, various problems are avoided, such as problems of tungsten diffusion into memory and photodiode regions 9 and 11.

(22) At the step of FIG. 9, antireflection layers 90 and 92 are deposited on layer 74. As an example, layer 90 is made of tantalum oxide and layer 92 is made of silicon oxide. The thickness of layer 90 is selected so that this layer, sandwiched between layers 74 and 92, forms an antireflection coating. The portions of layers 92 and 90 located opposite memory regions 9 and opaque walls 80 are etched from the back side, and the etching is continued down to a level located in layer 74. Due to the provision of layer 74, a portion of the opaque walls is exposed at the bottom of the etched portions. The etched portions, for example, tungsten, are filled with an opaque material. Due to the fact that the opaque walls are partly exposed, the tungsten is in contact with opaque walls 80. Opaque screens 96 have thus been obtained on the back side of memory regions 9, in contact with opaque walls 80.

(23) Each memory region 9 is thus located between two opaque walls 80 in contact with opaque screen 96. In operation, when the back side of the image sensor is illuminated by an optical radiation, memory region 9 is particularly efficiently protected from the radiation, particularly due to the contact between opaque screen 96 and opaque walls 80. The obtained image sensor thus has a particularly high image quality.

(24) As an example, each opaque screen 96 is connected to a node of application of a bias potential (not shown). Due to the fact for opaque walls 80 and the associated opaque screen 96 to be surrounded with the insulating materials of layers 70, 74, 90, and 92, the assembly of the opaque walls and of the screen can then be biased, which enables to control the operation of the memory cell.

(25) FIGS. 10 to 13 are simplified cross-section views illustrating another embodiment of a back-side illuminated image sensor at successive steps of its manufacturing. The manufacturing of a single pixel and of portions of neighboring pixels have been shown in the same way as in FIGS. 1 to 9.

(26) At the step of FIG. 10, from a semiconductor wafer 1, steps similar to those of FIGS. 1 to 5 have been successively implemented. The back side is thus located in the upper portion of FIGS. 10 to 13.

(27) The rear surface or back side is covered with a passivation layer 70, for example, made of hafnium oxide Hf0.sub.2, and then with a silicon oxide layer 74. An opening 100 is then etched from the back side above each of sacrificial walls 30, opening 100 extending through layer 70 and 74 all the way to sacrificial wall 30.

(28) At the step of FIG. 11, sacrificial walls 30 are removed in a way similar to that previously described in relation with FIG. 6, that is, by selective wet etching. A recess 60 is obtained at the location of each sacrificial wall 30, each recess 60 emerging towards the back side through the associated opening 100.

(29) The step of FIG. 12 is carried out in a way similar to that previously described in relation with FIG. 8, that is, by filling with an opaque material recesses 60 and openings 100, and then by polishing the rear surface all the way to polishing stop layer 74.

(30) The step of FIG. 13 is carried out similarly to that described in relation with FIG. 9. One obtains, on the one hand, an antireflection coating 74, 90, and 92 covering passivation layer 70 on the rear surface of each of photodiode regions 11 and, on the other hand, an opaque screen 96 located on the rear surface of each memory region 9. Each opaque screen 96 is in contact with opaque walls 80 delimiting each memory region 9.

(31) Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, at the step of FIG. 4, one via may be formed for each trench between, on the one hand, portion 40 and polysilicon layer 15 and, on the other hand, a node of application of a bias potential. The memory cell operation can thus be controlled.

(32) Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.