LC oscillator powering arrangement and method of powering an LC oscillator

Abstract

An LC oscillator powering arrangement comprises an LC oscillator configured to provide an oscillating signal output; a current source configured to supply the LC oscillator with a supply current, the current source during operation being controlled by a control voltage and supplied with a supply voltage subject to supply voltage ripple; and a replication block configured to generate an amplified replica of the supply voltage ripple directly from the supply voltage and to overlay the replica on the control voltage.

Claims

1. An LC oscillator powering arrangement, comprising: an LC oscillator comprising a resonant tank, wherein the LC oscillator is configured to provide an oscillating signal output; a current source configured to supply the LC oscillator with a supply current that flows entirely into the resonant tank, wherein, the current source is controllable via a control voltage and supplied with a supply voltage subject to a supply voltage ripple; and a replication block configured to generate a replica of the supply voltage ripple directly from the supply voltage and to overlay the replica on the control voltage.

2. The arrangement of claim 1, wherein the current source is a MOS transistor.

3. The arrangement of claim 2, wherein the current source is a PMOS transistor, wherein the supply voltage is applied at a source terminal of the PMOS transistor, wherein the control voltage is applied at a gate terminal of the PMOS transistor, and wherein the supply current is drawn from a drain terminal of the PMOS transistor.

4. The arrangement of claim 1, provided on a single chip.

5. An LC oscillator powering arrangement, comprising: an LC oscillator configured to provide an oscillating signal output; a current source configured to supply the LC oscillator with a supply current, wherein the current source is controllable via a control voltage and supplied with a supply voltage subject to a supply voltage ripple; a replication block configured to generate a replica of the supply voltage ripple directly from the supply voltage and to overlay the replica on the control voltage; and a calibration block, wherein the replication block is configured to amplify the replica with a tunable fractional gain settable by the calibration block, and wherein the calibration block is connected to the oscillating signal output of the LC oscillator and is configured to minimize an amplitude variation of the oscillating signal output of the LC oscillator by determining an optimum value of the tunable fractional gain of the replication block.

6. The arrangement of claim 5, wherein the calibration block comprises: a detector configured to detect the amplitude variation; a comparator configured to compare the amplitude variation with a reference voltage; and a controller connected to the comparator and configured to set the tunable fractional gain of the replication block during calibration.

7. The arrangement of claim 6, wherein the detector comprises a peak detector, an amplifier, and a low-pass filter.

8. The arrangement of claim 6, wherein during the minimizing of the amplitude variation, the reference voltage is set to a value larger than a minimum of the amplitude variation, and wherein the controller is configured to determine the optimum value of the tunable fractional gain as an average of a lower gain corresponding to a first output transition of the comparator and a higher gain corresponding to a second output transition of the comparator.

9. The arrangement of claim 5, wherein the tunable fractional gain is settable by a n-bit digital code, wherein n is a predetermined integer.

10. The arrangement of claim 9, wherein the replication block comprises a replicating part that provides unitary gain and a fractional part that provides the tunable fractional gain, wherein the fractional part comprises n injection blocks each individually switchable by an individual bit in the n-bit digital code.

11. The arrangement of claim 10, wherein the replicating part comprises a diode-connected PMOS transistor in series with two NMOS transistors forming a cascode, wherein each of the injection blocks comprises a current-source PMOS transistor in series with a switching PMOS transistor, a gate terminal of the switching PMOS transistor being connected to a corresponding the individual bit of the digital code, and a drain terminal of the switching PMOS transistor being connected to a node of the cascode.

12. A method of powering an LC oscillator, the method comprising: applying a supply voltage to drive a current source, the supply voltage being subject to a supply voltage ripple; generating, by way of a replication block, a replica of the supply voltage ripple directly from the supply voltage; applying a control voltage at the current source, the control voltage being overlaid with the replica; and supplying the LC oscillator with a supply current from the current source such that the supply current flows entirely into a resonant tank of the LC oscillator.

13. The method of claim 12, wherein the current source is a MOS transistor.

14. The method of claim 13, wherein the current source is a PMOS transistor, wherein the supply voltage is applied at a source terminal of the PMOS transistor, wherein the control voltage is applied at a gate terminal of the PMOS transistor, and wherein the supply current is drawn from a drain terminal of the PMOS transistor.

15. A method of powering an LC oscillator, the method comprising: applying a supply voltage to drive a current source, the supply voltage being subject to a supply voltage ripple; generating, by way of a replication block, a replica of the supply voltage ripple directly from the supply voltage; applying a control voltage at the current source, the control voltage being overlaid with the replica; supplying the LC oscillator with a supply current from the current source; amplifying the replica by way of the replication block with a tunable fractional gain settable by a calibration block that is connected to an oscillating signal output of the LC oscillator; and minimizing, via the calibration block, an amplitude variation of the oscillating signal output of the LC oscillator by determining an optimum value of the tunable fractional gain of the replication block.

16. The method of claim 15, wherein the calibration block comprises: a detector configured to detect the amplitude variation; a comparator configured to compare the amplitude variation with a reference voltage; and a controller connected to the comparator and configured to set said tunable fractional gain of the replication block during calibration.

17. The method of claim 16, wherein during the minimizing of the amplitude variation, the reference voltage is set to a value larger than a minimum of the amplitude variation, and wherein the controller is configured to determine the optimum value of the tunable fractional gain as an average of a lower gain corresponding to a first output transition of the comparator and a higher gain corresponding to a second output transition of the comparator.

18. The method of claim 15, wherein the tunable fractional gain is settable by a n-bit digital code, wherein n is a predetermined integer.

19. The method of claim 18, wherein the replication block comprises a replicating part that provides unitary gain and a fractional part that provides the tunable fractional gain, wherein the fractional part comprises n injection blocks each individually switchable by an individual bit in the n-bit digital code.

20. The method of claim 19, wherein the replicating part comprises a diode-connected PMOS transistor in series with two NMOS transistors forming a cascode, wherein each of the injection blocks comprises a current-source PMOS transistor in series with a switching PMOS transistor, a gate terminal of the switching PMOS transistor being connected to a corresponding the individual bit of the digital code and a drain terminal of the switching PMOS transistor being connected to a node of the cascode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1a is a conceptual block diagram of an LC oscillator powering arrangement with the equivalent model, according to an example embodiment.

(2) FIG. 1b is a conceptual block diagram of the proposed supply pushing reduction technique using a calibration loop, according to an example embodiment.

(3) FIG. 2 shows simulation results of an LC oscillator with the proposed technique, according to an example embodiment.

(4) FIG. 3 shows the operating principle of the calibration loop based on oscillation amplitude variation (V.sub.osc), according to an example embodiment.

(5) FIG. 4 is a block diagram of a calibration loop, according to an example embodiment.

(6) FIG. 5a shows the operating principle of the calibration loop using a proposed algorithm, according to an example embodiment.

(7) FIG. 5b is a flow chart of the calibration loop with the proposed algorithm, according to an example embodiment.

(8) FIG. 6a shows a simulated transfer function from peak detector output to comparator input in the calibration loop, according to an example embodiment.

(9) FIG. 6b shows a simulated power spectrum density of noise at comparator input with contributions from different noise sources, according to an example embodiment.

(10) FIG. 7 is a schematic of an implemented LC oscillator with a ripple replication block, according to an example embodiment.

(11) FIG. 8a shows the output noise of the ripple replication block, according to an example embodiment.

(12) FIG. 8b shows a schematic of a symmetrical transformer of the LC oscillator, according to an example embodiment.

(13) FIG. 8c shows the phase degradation of the LC oscillator with and without the common mode resonance, according to an example embodiment.

(14) FIG. 9 shows a chip micrograph of the LC oscillator with reduced supply pushing, according to an example embodiment.

(15) FIG. 10a shows measured phase noise of the oscillator across a gain tuning range of the calibration loop, according to an example embodiment.

(16) FIG. 10b shows measured spur level over a control code S.sub.t provided by the calibration loop, according to an example embodiment.

(17) FIG. 11a shows measured spur levels over sinusoidal ripple frequency, according to an example embodiment.

(18) FIG. 11b shows the corresponding supply pushing for both manual and automatic calibrations, according to an example embodiment.

(19) FIG. 11c shows measured spur levels over the oscillation frequency under the sinusoidal ripple, according to an example embodiment.

(20) FIG. 11d shows the corresponding supply pushing for both manual and automatic calibrations, according to an example embodiment.

(21) FIG. 11e shows measured spur levels over the frequency of sawtooth ripple, according to an example embodiment.

(22) FIG. 11f shows measured spur levels over the oscillation frequency under the sawtooth ripple, according to an example embodiment.

(23) FIG. 12a shows measured oscillator spectra before and after calibration under 50 mV peak-to-peak 5 MHz sinusoidal ripple, according to an example embodiment.

(24) FIG. 12b shows measured oscillator spectra before and after calibration under 50 mV peak-to-peak 5 MHz saw-tooth ripple, according to an example embodiment.

(25) FIG. 12c shows measured oscillator spectra under 50 mV peak-to-peak 2.5 MHz sinusoidal ripple, according to an example embodiment.

(26) FIG. 12d shows measured oscillator spectra under 20 mV peak-to-peak 2.5 MHz sinusoidal ripple, according to an example embodiment.

(27) FIG. 13 shows measured spur levels over 0-80 C., according to an example embodiment.

DETAILED DESCRIPTION

(28) An LC oscillator powering arrangement is provided which is insensitive to supply voltage ripple so that an LC oscillator may provide an oscillation output frequency.

(29) In the following, the operating principle of a technique for avoiding that a variation in supply voltage pushes or affects an oscillation output frequency, wherein the technique is based on replication of supply voltage ripple and in order to cancel an effect of the supply voltage ripple, will be elaborated. Particular reference will be made to a detailed circuit realization of a 5 GHz LC oscillator with the proposed feed-forward supply pushing reduction technique and an on-chip calibration loop.

(30) FIG. 1a illustrates the operating principle of providing supply pushing reduction. In an LC oscillator powering arrangement 100, an LC oscillator 110 comprising a resonant tank 120, comprising an inductor and a capacitor, and cross-coupled transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4 is supplied with current I.sub.0 from a current source.

(31) In this embodiment, the current source is illustrated as being implemented by way of a MOS transistor, in this example a PMOS transistor M.sub.0, supplying the LC oscillator 110 with a supply current I.sub.0. The transistor M.sub.0 is supplied with voltage V.sub.DD, which is applied at its source terminal, and controlled by a control voltage V.sub.b0, which is applied at its gate terminal. To stabilize I.sub.0, and thus the oscillating signal output V.sub.osc being output by the LC oscillator 110, in face of V.sub.DD variations, a replica G A.sub.ripple of the supply ripple A.sub.ripple is generated at a ripple replication block 130, directly from the supply voltage V.sub.DD, and overlaid on the gate of PMOS current source transistor M.sub.0. In one case, if the replica is an exact copy of the supply voltage, i.e., G=1, the gate-to-source voltage V.sub.gs of the PMOS current source transistor M.sub.0 will be stabilized. As a result, the variation of I.sub.0, and thereby of V.sub.osc, may be suppressed.

(32) The variation of oscillating frequency f.sub.osc of the LC oscillator 110 with the supply voltage, V.sub.DD, may be caused by the variation of parasitic capacitances seen by the resonant tank 120. The cross-coupled transistors M.sub.1-M.sub.4 provide a negative transconductance to sustain the oscillation and will experience cut-off, saturation and triode operating regions during each oscillation cycle. When V.sub.DD varies, the supply current, I.sub.0, and the corresponding oscillation amplitude, V.sub.osc, will also vary. Thus it will change the time interval during which the transistors stay in each operating region. Since the gate capacitance of MOS transistors shows nonlinear dependence on the voltages at their terminals (i.e. gate-to-source voltage V.sub.gs and drain-to-source voltage V.sub.ds), the change in the operating states of MOS transistors would vary the equivalent parasitic capacitance, C.sub.par,equ. Thus, the oscillating frequency will be pushed. If a periodical ripple is on V.sub.DD, I.sub.0 and V.sub.osc will also show periodical variations. Therefore, the change of C.sub.par,equ will also be periodical and could manifest itself as large spurs in the output spectrum of the LC oscillator 110. Stabilizing I.sub.0 and V.sub.osc under V.sub.DD variations allows a clean output spectrum to be obtained when V.sub.DD contains ripples.

(33) If M.sub.0 is a device, whose drain current is controlled by its V.sub.gs according to the square law, then an exact copy of the supply ripple waveform is may be used at its gate terminal V.sub.b0 to keep I.sub.0 and V.sub.osc constant. However, for nanoscale CMOS technologies, a channel-length modulation effect is not negligible. This means that the drain current of M.sub.0 may depend on its Vs. Thus in order to compensate for residue current variation due to the variation of V.sub.ds of M.sub.0, some embodiments may use an amplified replica of the supply ripple in the waveform at V.sub.b0.

(34) FIG. 1a also shows the equivalent model to estimate the optimum gain (G.sub.opt). Based on this model, the supply voltage variation, V.sub.DD, induced supply current variation, I.sub.0,VDD, could be calculated as

(35) $\begin{array}{cc}{I}_{0,V_{\mathrm{DD}}}=\frac{1+g_{m0}.Math.r_{o0}}{r_{o0}+Z_{\mathrm{eq}}}{V}_{\mathrm{DD}},& \left(1\right)\end{array}$
while the supply current variation induced by control voltage variation V.sub.b0=G.Math.V.sub.DD is

(36) $\begin{array}{cc}{I}_{0,V_{b0}}=-\frac{g_{m0}.Math.r_{o0}}{r_{o0}+Z_{\mathrm{eq}}}{V}_{b0},& \left(2\right)\end{array}$
where Z.sub.eq is the large-signal equivalent impedance of the cross-coupled transistors M.sub.1-4 and the resonant tank 120 that is seen by M.sub.0, while g.sub.m0 and r.sub.o0 are the effective transconductance and output resistance of M.sub.0, respectively. To compensate for the supply current variation due to V.sub.ds, the magnitudes of (1) and (2) should be equal. Hence, G.sub.opt may be calculated as

(37) $\begin{array}{cc}{G}_{\mathrm{opt}}1+\frac{1}{g_{m0}.Math.r_{o0}}.& \left(3\right)\end{array}$
Since g.sub.m0.Math.r.sub.o0 is relatively large (e.g. >10), G.sub.opt is slightly larger than 1.

(38) As shown in simulation results in FIG. 2, the variations of I.sub.0 and V.sub.osc may be largely suppressed when the waveform applied at V.sub.b0 is the same as that of the supply ripple (gain, G=1). Hence, the frequency variations due to the supply voltage are largely reduced, resulting in a much lower supply pushing of the oscillator. FIG. 2 also shows that I.sub.0 and V.sub.osc are further stabilized (i.e. 10 times smaller variations compared to the G=1 case) under supply variations when GG.sub.opt, thus the supply pushing of the oscillator becomes much lower.

(39) Portable devices such as Internet-of-Things (IOT) devices powered by batteries or energy harvesters may include buck and/or switching DC-DC converters to transform the output levels of energy sources to the nominal supply voltage of IOT electronic circuitry. Due to the switching operation of DC-DC converters, the resulting output ripples can degrade performance of the supply-sensitive circuitry, such as LC-tank oscillators, when connected directly. This supply pushing of LC-tank oscillators may be reduced to allow them to operate from DC-DC converters, which naturally contain high level of ripples. To avoid this, a low dropout (LDO) linear regulator is usually inserted after the switching converter to stabilize the supply voltage. However, the extra voltage overhead (200 mV) may worsen the system's power efficiency (80% under 1V supply). This will make it even more critical with the supply scaling down with technology.

(40) In the present disclosure, there is proposed a feed-forward supply ripple replication and cancellation technique which may be wholly contained within an LC oscillator in order to make it practically insensitive to supply ripples of switching DC-DC converters. Since, in the present disclosure, the LC oscillator may be driven directly from the output of the DC-DC converter, no extra voltage headroom may be used. Therefore, power can be saved.

(41) Optionally, a calibration block, here in the form of a calibration loop 140, may also be implemented, optionally integrated on-die, as shown in FIG. 1b. The replication block 130 is configured to amplify the replica with a tunable fractional gain settable by the calibration block 140, with the calibration block 140 being connected to the oscillating signal output V.sub.osc of the LC oscillator.

(42) As can be gathered from equation 3, the optimum gain is prone to PVT variations. The calibration loop 140 may compensate for such variations, improving performance as compared to using a pre-determined gain.

(43) The calibration scheme is based on measuring the variation of the oscillation amplitude, V.sub.amp, in response to the V.sub.DD perturbations. FIG. 3 shows the operating principle of the calibration loop 140. When G<G.sub.opt (case A), I.sub.0,Vb0 is smaller than I.sub.0,VDD, so V.sub.amp is in phase with V.sub.DD and decreases in magnitude as G gets closer to G.sub.opt. However, when G>G.sub.opt (case B), I.sub.0,Vb0 becomes larger than I.sub.0,VDD. Then, V.sub.amp is out of phase with V.sub.DD, and its magnitude increases again with the increase of G. At the optimum point, G=G.sub.opt, and a constant oscillation, amplitude is maintained under supply variations.

(44) Thus, the calibration loop 140 may be configured to measure V.sub.amp under different gain settings to calculate the optimum operating point for the oscillator circuit. Thus, the calibration block 140 is configured to minimize the amplitude variation V.sub.amp of the oscillating signal output V.sub.osc of the LC oscillator 110 by determining an optimum value of a tunable fractional gain G of the replication block 130. The calibration loop 140 may be configured to only be active during calibration.

(45) FIG. 4 shows an example block diagram of an integrated calibration loop 140. As discussed above, the perturbation of the oscillation amplitude, V.sub.amp, is used in the loop 140 as a stimulus to calibrate G.sub.opt. The outputs of the oscillator may be first connected to a peak detector 410. The output V.sub.pd of the peak detector 410, contains two frequency components: the one at f.sub.ripple, and the additional one at the second harmonic of the oscillation frequency, f.sub.osc. V.sub.pd may then be amplified through self-biased inverters.

(46) Two inverter stages 422, 424 with bandwidth of 20 MHz may be implemented. The inverter stages 422, 424 amplify the small input level at V.sub.pd (e.g. 1 mV) to a larger amplitude (e.g., 250 mV) at the output V.sub.inv, with a relatively large gain (e.g. 48 dB).

(47) The output of the inverter chain, V.sub.inv, may be filtered by an RC low-pass filter (LPF) 430. The cut-off frequency of the LPF 430 may be set to pass through the frequency component at f.sub.ripple, while the second harmonic at 2f.sub.osc is filtered out. If there is any mismatch in the input differential pair of the peak detector, V.sub.pd would contain a third frequency component at f.sub.osc. Since f.sub.osc (several GHz) is much higher than f.sub.ripple (tens of MHz), this component is filtered out by the inverter chain and the LPF. Hence, the mismatch in the peak detector will not affect the calibration results.

(48) The resulting transfer function from amplifier 420 input V.sub.pd to LPF 430 output V.sub.lpf is shown as a function of frequency in FIG. 6a.

(49) Thus, the calibration block 140 comprises a detectorcomprising the peak detector 410, the amplifier 420, and the LFP 430configured to detect the amplitude variation V.sub.amp of the oscillating signal output V.sub.osc of the LC oscillator 110.

(50) The output of the LPF 430, V.sub.lpf, may then be compared with a reference value, V.sub.ref, through a comparator 440. V.sub.ref is roughly set to a voltage higher than the product of the V.sub.amp and the DC gain of the peak detector 410 cascade with the inverter stages 422, 424.

(51) The output V.sub.out of the comparator 440 may be connected to the clock terminal of a D flip-flop (DFF) 450. When V.sub.ref is crossed, the comparator's 440 output becomes high, triggering the output of the DFF to flip to 1. A digital algorithm in the loop monitors the latch output, Latch_out, and may calculate the optimum control code S.sub.t (see below) for the ripple replication block 130. Other ways of controlling the replication block 130 are equally possible.

(52) The digital block 460 attempts to find the minimum point of V.sub.amp vs. the control code (V.sub.amp,min in FIG. 5a). FIG. 5a shows the operating principle of the proposed technique. The reference voltage, V.sub.ref, at the comparator input is roughly set to a value corresponding to an oscillation amplitude variation of V.sub.amp,th, which is higher than V.sub.amp,min. The calibration process starts from a small value of S.sub.t, where G<G.sub.opt and V.sub.amp>V.sub.amp,th. Thus, the initial value of Latch_out is 1. The algorithm keeps increasing S.sub.t, which decreases V.sub.amp as G approaches G.sub.opt. When V.sub.amp becomes lower than V.sub.amp,th, Latch_out changes from 1 to 0. The algorithm records this code as S.sub.t,min, and then increases S.sub.t again. When S.sub.t is large enough, V.sub.amp would be higher than V.sub.amp,th again, and Latch_out switches back to 1. The algorithm records this code as S.sub.t,max, and the optimum code, S.sub.t,avg, is calculated as the average of these two recorded codes. FIG. 5b reveals the operational flow chart of this calibration process. The high-pass response of the loop due to AC-coupling limits the settling time when S.sub.t changes. In this example, the corner frequency is designed to be 2.5 MHz, resulting in a settling time of 0.4 is per step. Lower corner frequency could be used to detect lower ripple frequency at the expense of longer settling time.

(53) Thus, the LC powering arrangement 100 is configured so that, during the minimizing of the amplitude variation V.sub.amp, the reference voltage V.sub.ref is set to a value larger than a minimum V.sub.amp,min of the amplitude variation, a controller, here in the form of digital block 460, being configured to determine the optimum value G.sub.opt of the tunable fractional gain G as an average of a lower gain corresponding to a first output transition of the comparator 440 and a higher gain corresponding to a second output transition of the comparator 440.

(54) Thus, in the present disclosure, a calibration algorithm is proposed whereby one comparator 440 without any offset calibration can be used in the loop. Otherwise, to precisely detect V.sub.amp,min, a set of comparators and DFFs may be used. The simulated amplitude variation at the output of the LPF is 300 mV. Thus, 20 comparators, followed by a DFF each, are able to achieve a voltage resolution of 15 mV Some offset calibration techniques could be used to reduce the input referred offset of comparators to a level much lower than the voltage resolution. The digital algorithm would then count the number of is in the output of the DFFs to determine V.sub.amp. Such a method would increase the design complexity greatly. Thus, the method of the present disclosure achieves an accurate determination of V.sub.amp,min while retaining low design complexity.

(55) FIG. 6b shows the simulated power spectrum density (PSD) of noise at the comparator's input. A major part of the noise is contributed by the oscillator itself. The differential output of the oscillator is less affected by the variation of the common mode voltage, but the output level of the peak detector would be modulated. Thus, the calibration loop 140 is more sensitive to the common mode noise from the LC oscillator 110, e.g. noise of the supply current source. After being shaped by the transfer function of the inverter chain 420 and LPF 430, the common-mode noise is finally passed to the comparator's 440 input. From FIG. 6b, the integrated noise is around 14 mV, corresponding to 0.095 mV equivalent input noise at the input of the peak detector at 5 MHz f.sub.ripple. To achieve less than 50 dBc spur level, V.sub.amp is simulated to be 1.8 mV (0.64 mV.sub.rms), leading to a SNR of 16.5 dB, which is sufficient for an effective calibration.

(56) FIG. 7 shows a schematic of an example ripple replication block 130 together with an example LC oscillator 110. The ripple replication block 130 is proposed to bias the gate terminal of current source M.sub.0 of the LC oscillator 110. To generate the replica with the gain G larger than 1, the ripple replication block 130 is logically divided into two parts. The first part 132 (left dashed box in FIG. 7) contains a diode-connected PMOS transistor, M.sub.b0, in series with two cascode NMOS transistors, M.sub.b1,2. Due to the high output impedance of the cascode, M.sub.b0 can replicate the supply ripple to V.sub.b0 with a fixed and unitary gain of 1. Thus, the first term on the right hand side of equation 3 is covered by this part.

(57) To boost the gain above 1, the fractional part 134 (right dashed box in FIG. 7) is introduced to inject some extra current proportional to V.sub.DD into the cascode node, V.sub.inj. To digitally control the fractional gain, current source PMOS transistors M.sub.pk (k=0, 1, . . . n) are individually turned on/off by switch PMOS transistors M.sub.sk (k=0, 1, . . . n) according to the digital code S.sub.t generated by the calibration loop 140. Switching PMOS transistor M.sub.pk drain terminal is connected to the node V.sub.inj of the cascode.

(58) Thus, the tunable fractional gain is settable by a n-bit digital code, where n is a predetermined integer and the fractional part of the replication block comprises n injection blocks each individually switchable by an individual bit in the n-bit digital code.

(59) The fractional part thus provides an adjustable transconductance between V.sub.DD and V.sub.inj. The final gain G provided by the ripple replication block 130 can be approximated as

(60) $\begin{array}{cc}G1+\frac{g_{m,f}}{g_{m,b0}}& \left(4\right)\end{array}$
where g.sub.m,f and g.sub.m,b0 are the total equivalent transconductance of the fractional part 134 and the transconductance of M.sub.b0, respectively. Since G.sub.opt is only slightly larger than 1, the g.sub.m,f should be much smaller than g.sub.m,b0. Therefore, the total current injected into V.sub.inj may be smaller than the current consumed by M.sub.b0, and would not lead to a large variation of the operating point of the LC oscillator. Moreover, the cascode transistor M.sub.b1 could be removed for designs with lower V.sub.DD. The slightly reduced gain provided by the first part could be compensated by slightly increasing g.sub.m,f.

(61) In this design, a channel length of 120 nm is used for M.sub.0 leading to a load of 800 fF. When g.sub.m/I.sub.ds12, the total current consumption (including the fractional part) is 200 A with a maximum G of 1.1. A 5-bit thermometer code is implemented to cover the aforementioned maximum G. The PMOS transistors in the fractional part are sized to achieve tuning resolution of 0.003 as a trade-off between the resolution and calibration time. The unit-gain bandwidth, co, of the ripple replication block is established by both the frequency of the supply ripple, f.sub.ripple, and the tolerable phase shift between the ripple and the replica. To guarantee <50 dBc spur level at f.sub.ripple=20 MHz, a .sub.u of 450 MHz may be used based on simulations. Together with the capacitive load at the output of the ripple replication block, this bandwidth determines the current consumption of this block. A smaller capacitance could be achieved when M.sub.0 is designed with a minimum channel length. However, the G.sub.opt would increase, which could adversely affect the tuning resolution and/or calibration time. The present design provides a compromise.

(62) For the LC oscillator 110, as in this example, a complementary cross-coupled oscillator structure may be chosen. This leads to lower power consumption compared to its NMOS- and PMOS-only counterparts at same V.sub.DD and equivalent parallel resistance of the tank. The designed oscillator uses a transformer-based resonant tank. Since the ripple replication block is connected to the gate of supply current source M.sub.0, the replicator's output noise (see FIG. 8a), especially flicker noise of transistors M.sub.b0,2, will modulate the oscillator's current, thus up-converting into output phase noise (PN) through a mechanism such as Groszkowski's effect. An implicit common-mode resonance technique is applied, which limits PN degradation. Single-ended capacitor banks are connected to a symmetrical transformer, as shown in FIG. 8b, are used to tune the common-mode resonance frequency to around 2f.sub.osc. Simulation results in FIG. 8c show that the PN degradation can be reduced to <1 dB when the implicit common-mode technique is used. Both the NMOS and PMOS cross-coupled transistors M.sub.1-4 provide the negative transconductance in the complementary structure. The body terminals of the PMOS cross-coupled pair, M.sub.1,2, are deliberately connected to their source terminals to avoid the body effect. Otherwise, their threshold voltage, V.sub.th, would be modulated under supply variations thus varying the oscillation amplitude V.sub.osc, consequently pushing f.sub.osc. Simulation results show that the supply pushing due to this body effect could be as high as 9.5 MHz/V Note that the above mentioned NMOS alternative to the supply current transistor M.sub.0 would not be effective unless a costly triple-well technology is used.

(63) The example LC oscillator 110 with the proposed powering arrangement 100 with feed-forward ripple replication and cancellation was implemented in TSMC 40-nm 1P8M CMOS process without ultra-thick metal layers. The proposed calibration loop 140 was also integrated on-die. FIG. 9 shows the chip micrograph. The total active area is 0.23 mm.sup.2, in which the oscillator core occupies about 0.215 mm.sup.2. The additional area occupied by the ripple replication block with its biasing circuit and the calibration loop 140 is just 0.012 mm.sup.2. The symmetrical transformer was designed by stacking the top two metal layers with the aluminum capping layer, which enhances the tank's Q-factor. The spacing between each turn of the transformer was optimized for a magnetic coupling factor of 0.31. The simulated differential inductance of the transformer is 1.7 nH. The Q-factor of the whole tank is estimated to be 7. The capacitor banks are split into a 5-bit differential bank and a 5-bit common-mode bank to tune the common-mode resonance frequency.

(64) The measured tuning range (TR) is 4.9-5.7 GHz (15%). FIG. 10a shows the measured PN performance across the TR. PN varies from 108 to 111 dBc/Hz @1 MHz offset, with a flicker noise corner of around 100 kHz. To verify the concept of the proposed technique, the control code S.sub.t of the ripple replication block is manually swept while a 50 m V.sub.pp (peak-to-peak) 5 MHz sinusoidal ripple is applied on the oscillator supply. As shown in FIG. 10b, there exists an optimum code at which the spur level is lower than 60 dBc, corresponding to a >27 dB improvement over the S.sub.f=0 case. Note that G1 when S.sub.t=0, and the oscillator already benefits from the significantly reduced supply pushing.

(65) The effectiveness of the automatic calibration loop 140 is verified in FIG. 12a, which compares the spectra before and after the calibration. With the supply contamination by a 50 m V.sub.pp 5 MHz sinusoidal ripple, the spur level is reduced by 30 dBc and reaches 68.7 dBc after the calibration. FIG. 11a shows the measured spur level over the frequency of the supply ripple. The proposed technique achieves 49 dBc optimum spur levels under 50 m V.sub.pp, 0.5-20 MHz sinusoidal ripples, while the calibrated spur levels closely follow the optimum ones in most cases. The increase of the spur level at high ripple frequencies is due to the bandwidth limitation of the ripple replication block, and could be extended by expending more power. In FIG. 11c, the spur level is measured across the tuning range of the oscillator. The worst-case spur under a 50 m V.sub.pp 5 MHz sinusoidal ripple is 59 dBc. FIG. 11b and FIG. 11d show the oscillator's supply pushing based on the measured spur levels. When the ripple frequency is lower than 12 MHz, the calculated supply pushing is lower than 1 MHz/V for both the optimum and calibrated cases.

(66) Similar measurements were also performed for saw-tooth ripples. FIG. 12b compares the spectra before and after the calibration. Under a 50 m V.sub.pp 5 MHz saw-tooth ripple, the spur at the fundamental offset is reduced by 22.9 dB and reaches 61.7 dBc after the calibration. For spurs at higher harmonics, the suppression is also observed, but with lower magnitudes (5.8 dBc suppression for the second harmonic reaching 59.1 dBc after the calibration). FIG. 11e shows the spur levels over the ripple frequency. The worst-case spur of 47 dBc is found under 50 m V.sub.pp, 0.5-20 MHz saw-tooth ripples, while the calibration results follow the optima. In FIG. 11f, the spurs are lower than 58 dBc within the entire tuning range under a 50 m V.sub.pp 5 MHz saw-tooth ripple.

(67) FIG. 12c shows the measured oscillator spectrum under a 50 m V.sub.pp 2.5 MHz supply ripple. A spur can also be observed at an offset frequency of 5 MHz (i.e. 22.5 MHz). This second ripple harmonic spur mainly comes from the nonlinearity of the fractional part of the ripple replication block. To achieve fine tuning resolution, the transistors in this part are biased with small overdrive voltage, resulting in V.sub.IP2140 mV and g.sub.m/I.sub.ds19. To improve the performance at the second ripple these transistors can be re-sized and biased with a different linearity and smaller g.sub.m/I.sub.ds. The resulting increase in current consumption would be quite small (i.e. 12 A) since the current consumed by the fractional part is much smaller than that consumed by the integer part. Also, the spur at the second ripple harmonic reduces faster with the ripple amplitude. As shown in FIG. 12c, the measured spur level at the second harmonic is reduced to 65.9 dBc under a 20 m V.sub.pp ripple, which should bear little practical consequences.

(68) The IC chip was also measured over the temperature range of 0-80 C, and the results are shown in FIG. 13. The spur levels are lower than 60 dBc, except for the calibrated one at 80 C.

(69) Table I summarizes the features and performance of the proposed technique.

(70) TABLE-US-00001 TABLE 1 Description Feed-forward compensation Osc. Type LC Tech. (nm) 40 (w/o UTM) V.sub.pp (V) 1.0 Frequency Range (GHz) 4.9-5.7 (15%) PN (dBc/Hz) @1 MHz 107.9 to 110.9 Ripple amplitude 50 mV.sub.pp Sinewave Spur (dBc) @1 MHz <54 @5 MHz <58 K.sub.sup (MHz/V) @1 MHz <0.16* @5 MHz <0.5* Improv. (dBc) @1 MHz 18-24** @5 MHz 24-30** Saw-tooth Spur (dBc) @1 MHz <50 @5 MHz <58 Improv. (dBc) @1 MHz 11.3** @5 MHz 22-27** Osc. Power Cons. (mW) 0.8-1.3 Power Cons. K.sub.sup Reduction Tech. (mW) 0.2 Area of K.sub.sup Reduction Tech (mm.sup.2) 0.012 Total area (mm.sup.2) 0.23 *Calculated value from the spur level. **Compared with the case S.sub.t = 0 (G = 1) where the supply pushing of the oscillator is already suppressed.

(71) With the present disclosure, it is possible to significantly reduce supply pushing in current-mode LC oscillators while consuming no extra voltage headroom. The proposed ripple replication block 130 generates an amplified supply ripple replica GA.sub.ripple at the gate terminal of the oscillator's 110 supply current source, in order to stabilize the supply current and oscillation amplitude under supply variations. The oscillation frequency is stabilized in turn, leading to <1 MHz/V supply pushing for supply ripples up to 12 MHz. To suppress the phase noise degradation due to the extra circuitry, implicit common mode resonance is used in the resonant tank. A calibration loop 140 with an algorithm is also integrated on-chip, which finds the optimum gain G for the ripple replication block 130.

(72) The above disclosure has mainly been described with reference to a limited number of examples. However, other examples than the ones disclosed above are equally possible within the scope of the disclosure, as defined by the appended claims.