RED LED AND METHOD OF MANUFACTURE

Abstract

A red-light emitting diode (LED) comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion. The light emitting region comprises: a light-emitting indium gallium nitride layer which emits light at a peak wavelength between 600 and 750 nm under electrical bias thereacross; a III-nitride layer located on the light-emitting indium gallium nitride layer; and a III-nitride barrier layer located on the III-nitride layer, and the light emitting diode comprises a porous region of III-nitride material. A red mini LED, a red micro-LED, an array of micro-LEDs, and a method of manufacturing a red LED are also provided.

Claims

1. A red-light emitting diode (LED), comprising: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion, the light emitting region comprising: a light-emitting indium gallium nitride layer which emits light at a peak wavelength between 600 and 750 nm under electrical bias thereacross; a Ill-nitride layer located on the light-emitting indium gallium nitride layer; and a III-nitride barrier layer located on the Ill-nitride layer, wherein the light emitting diode comprises a porous region of III-nitride material.

2. A red LED according to claim 1, wherein the light emitting diode comprises at least one feature selected from: (a) the light emitting region comprises one or two or three or four or five or six or seven or eight quantum wells (or at least one quantum well); or (b) the Ill-nitride layer comprises an aluminum gallium nitride layer which has a composition Al.sub.yGa(.sub.I-y)N, where y is in a range from 0.1 to 1.0; or (c) a UV or blue emitting InGaN/GaN or InGaN/inGaN superlattice or InGaN layer is located between the n-doped portion and the light emitting region.

3. A red LED according to claim 1, in which the light emitting region emits light at a peak wavelength between 600 and 700 nm, or between 615 and 675 nm under electrical bias.

4. A red LED according to claim 1, in which the LED light emitting region is an LED light emitting region for emitting at a peak wavelength of 500-580 nm, and in which the porous region of III-nitride material shifts the emission wavelength of the light-emitting region to between 600 and 750 nm.

5. A red LED according to claim 1 , in which the porous region has a thickness of at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm.

6. A red LED according to claim 5, in which the red LED comprises a connecting layer of III-nitride material positioned between the n-doped portion and the porous region, preferably in which the thickness of the connecting layer is at least 100 nm.

7. A red LED according to claim 6, comprising a non-porous intermediate layer of III-nitride material positioned between the porous region and the connecting layer.

8. A red LED according to claim 5, in which the n-doped portion comprises an n-doped III-nitride layer, preferably in which the n-doped portion comprises n-GaN, or n-InGaN, or a stack of alternating layers of n-GaN/n-InGaN, or a stack of alternating layers of n-InGaN/n-InGaN containing different concentrations of indium.

9. A red LED according to claim 8, in which the n-doped portion comprises a single-crystalline n-doped III-nitride portion, preferably in which the n-doped portion comprises a single-crystalline n-doped III-nitride layer having a planar top surface.

10. A red LED according to claim 9, in which the porous region and each layer between the porous region and the single-crystalline n-doped III-nitride layer are planar layers having a respective top surface and a respective bottom surface that are parallel to the planar top surface of the single-crystalline n-doped III-nitride layer.

11. A red LED according to claim 1, in which the light-emitting indium gallium nitride layer comprises one or more InGaN quantum wells, preferably between 1 and 7 quantum wells.

12. A red LED according to claim 11, in which the light emitting indium gallium nitride layer is a nanostructured layer of InGaN comprising quantum structures such as quantum dots, fragmented or discontinuous quantum wells..

13. A red LED according to claim 11 in which a light-emitting indium gallium nitride layer and/or the quantum wells have the composition In.sub.xGa.sub.1-xN, in which 0.15 ≤ × ≤ 0.40, preferably 0.20 ≤ × ≤ 0.40 or 0.26 ≤ × ≤ 0.40, particularly preferably 0.30 ≤ × ≤ 0.40.

14. A red LED according to claim 11, in which the LED comprises a cap layer of III-nitride material between the quantum wells and the p-doped portion.

15. A red LED according to claim 1, in which the p-doped portion comprises a p-doped III-nitride layer and a p-doped aluminium gallium nitride layer positioned between the p-doped III-nitride layer and the light emitting region.

16. A red LED according to claim 15, in which the p-doped aluminium nitride layer is an electron-blocking-layer (EBL) between the cap layer and the p-type layer, in which the electron-blocking-layer contains 5-25 at% aluminium, preferably in which the electron-blocking-layer has a thickness of between 10-50 nm.

17. A red LED according to claim 1, in which the porous region is not part of a distributed Bragg reflector (DBR).

18. A red mini-LED, comprising the red LED according to claim 1, in which the light-emitting region has lateral dimensions of greater than 100 .Math.m and less than 200 .Math.m.

19. A red micro-LED, comprising the red LED according to claim 1, in which the light-emitting region has lateral dimensions of less than 100 .Math.m.

20. A microLED array, comprising a plurality of red micro-LEDs according to claim 19.

21. A method of manufacturing a red LED, comprising the step of overgrowing, over a porous region of III-nitride material: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion, the light emitting region comprising a light-emitting indium gallium nitride layer which emits light at a peak wavelength between 600 and 750 nm under electrical bias thereacross.

22. A method of manufacturing a red LED, comprising the step of overgrowing, over a porous region of III-nitride material: an n-doped portion; a p-doped portion; and an LED light emitting region between the n-doped portion and a p-doped portion, the light emitting region comprising a light-emitting indium gallium nitride layer for emitting at a peak wavelength of 500-550 nm or 550 nm - 600 nm, wherein overgrowth on the porous region of III-nitride material shifts the emission wavelength of the light-emitting region to a peak wavelength between 600 and 750 nm under electrical bias.

23. A method according to claim 21 comprising the first step of electrochemically porosifying a layer of III-nitride material, to form the porous region of III-nitride material.

24. A method according to claim 23, comprising the step of forming the porous region of III-nitride material by electrochemical porosification through a non-porous region of III-nitride material, such that the non-porous region of III-nitride material forms a non-porous intermediate layer.

25. A method according to claim 24, comprising the step of depositing one or more connecting layers of III-nitride material on the surface of the intermediate layer of III-nitride material prior to overgrowing the n-doped region, the LED light emitting region and the p-doped region with In% on the connecting layer.

26. A method according to claim 23, comprising the step of depositing a connecting layer of III-nitride material onto the surface of the porous region of III-nitride material.

27. A method according to claim 25, comprising the step of overgrowing the n-doped region, the LED light emitting region and the p-doped region on the connecting layer.

28. A method according to claim 22, in which the red LED comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion, the light emitting region comprising: a light-emitting indium gallium nitride layer which emits light at a peak wavelength between 600 and 750 nm under electrical bias thereacross; a Ill-nitride layer located on the light-emitting indium gallium nitride layer; and a III-nitride barrier layer located on the Ill-nitride layer, wherein the light emitting diode comprises a porous region of III-nitride material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0108] Embodiments of the invention will now be described with reference to the figures, in which:

[0109] FIG. 1 illustrates a porous template suitable for a red LED according to the present invention;

[0110] FIGS. 2-13 illustrate the steps of manufacturing a red LED according to a preferred embodiment of the present invention;

[0111] FIG. 14 is a graph of normalised electroluminescence (EL) intensity vs wavelength, for an InGaN LED over a porous region according to a preferred embodiment of the present invention;

[0112] FIG. 15 is a graph of normalised electroluminescence (EL) intensity vs wavelength at different current injections, for an InGaN LED on a non-porous substrate;

[0113] FIG. 16 is a graph of normalised electroluminescence (EL) intensity vs wavelength at different current injections, for the same InGaN LED as FIG. 15 grown over a porous region according to a preferred embodiment of the present invention;

[0114] FIG. 17 is an I-V curve measured for InGaN micro-LEDs of different pixel sizes on a non-porous substrate, with the inset image showing yellow emission;

[0115] FIG. 18 is an I-V curve measured for InGaN micro-LEDs of different pixel sizes on a porous substrate, with the inset image showing red emission.

[0116] FIG. 1 illustrates a porous template suitable for a red LED according to the present invention.

[0117] The porous template comprises a porous region of III-nitride material on a substrate, with a non-porous layer of III-nitride material arranged over the top surface of the porous region. Optionally there may be further layers of III-nitride material between the substrate and the porous region.

[0118] As described in more detail below, the porous region may be provided by epitaxially growing an n-doped region of III-nitride material and then an undoped layer of III-nitride material, and porosifying the n-doped region using the porosification process as set out in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728).

[0119] As described above, this porosification leads to strain relaxation in the crystal lattice, which means that subsequent overgrowth of further semiconductor layers benefit from reduced compressive strain in their lattices.

[0120] The porous region may comprise one or more layers one or more III-nitride materials, and may have a range of thicknesses, all while still providing the strain relaxation benefit that shifts the wavelength of InGaN light emitting layers overgrown above the porous region. In preferred embodiments, the porous region may for example comprise GaN and/or InGaN.

[0121] A variety of LED structures may be overgrown over the template illustrated in FIG. 1.

[0122] In particular, LED structures containing InGaN light emitting layers, which are known in the art to be yellow or green LEDs, may be overgrown on the porous template using standard LED manufacturing steps. When grown on the porous template, however, a LED structure which normally emits at yellow or green wavelengths, will emit at red wavelengths of 600-750 nm.

[0123] In this way, the use of a porous region of III-nitride material as a template or pseudo-substrate for overgrowth of yellow or green InGaN LEDs allows red LEDs to be manufactured in a straightforward manner.

[0124] In a preferred embodiment, a red LED according to the present invention comprises the following layers, and may be manufactured using the step by step process described below.

[0125] The following description of the LED structure relates to a Top emission architecture being described from the bottom up, but the invention is equally applicable to a bottom emission architecture.

Figure 2 - Substrate & III-Nitride Layer for Porosification

[0126] A compatible substrate is used as a starting surface for epitaxy growth. The substrate may be Silicon, Sapphire, SiC, β-Ga2O3, GaN, glass or metal. The crystal orientation of the substrates can be polar, semi-polar or non-polar orientation. The substrate size may vary from 1 cm.sup.2, 2 inch, 4 inch, 6 inch, 8 inch, 12 inch, 16 inch diameters and beyond, and the substrate may have a thickness of greater than 1 .Math.m, for example between 1 .Math.m and 15000 .Math.m.

[0127] A layer or stack of layers of III-nitride material is epitaxially grown on the substrate. The III-nitride layer may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layer).

[0128] The thickness T of the III-nitride stack is preferably at least 10 nm, or at least 50 nm, or at least 100 nm, for example between 10-10000 nm.

[0129] The III-nitride layer comprises a doped region having an n-type doping concentration between 1 × 10.sup.17 cm.sup.-3 - 5 × 10.sup.20 cm.sup.-3. The III-nitride layer may also comprise an undoped “cap” layer of III-nitride material over the doped region.

[0130] The doped region may terminate at the exposed upper surface of the III-nitride layer, in which case the surface of the layer will be porosified during electrochemical etching.

[0131] Alternatively, the doped region of the III-nitride material may be covered by an undoped “cap” layer of III-nitride material, so that the doped region is sub-surface in the semiconductor structure. The sub-surface starting depth (d) of the doped region may be between 1-2000 nm for example.

Figure 3 - Porosification to Porous Region

[0132] After it is deposited on the substrate, the III-nitride layer (or stack of layers) is porosified with a wafer scale porosification process as set out in international pat. applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728). During this process, the doped region of the III-nitride material becomes porous, while any undoped region of III-nitride material does not become porous.

[0133] Following the porosification step, the structure therefore contains a porous region which remains where there was previously n-doped III-nitride material, and optionally a non-porous intermediate layer overlying the porous region.

[0134] The degree of porosity of the porous region is controlled by the electrochemical etching process and may be between 1%-99% porosity, preferably between 20% to 90% porosity or between 30% - 80%, though lesser or greater porosities could also be employed.

[0135] The thickness of the porous region following porosification is preferably greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm. However, the thickness of material required to obtain the strain relaxation benefit provided by the porous region may vary depending on the type of III-nitride material from which the porous region is made.

[0136] The porous region created by the porosification process may be a bulk layer of a III-nitride material having a uniform composition and a uniform porosity throughout the layer. Alternatively the porous region may comprise multiple layers of porous material of different compositions and/or porosities, forming a porous stack of III-nitride material. For example the porous region may be a continuous layer of porous GaN, or a continuous layer of porous InGaN, or a stack comprising one or more layers of porous GaN and/or one or more layers of porous InGaN. The inventors have found that the strain relaxation benefit of the porous region for overgrowth is obtainable across a wide range of porous regions having different thicknesses, compositions, and layered stacks.

[0137] In the embodiment illustrated in the Figures, the porous region is a single porous layer.

[0138] Where there is an undoped cap layer of III-nitride material over the doped region, the undoped region remains non-porous following through-surface porosification of the doped region below. The thickness D of this non-porous cap layer may preferably be at least 2 nm, or at least 5 nm, or at least 10 nm, preferably 5-3000 nm. Providing an undoped cap layer over the doped region advantageously leads to a non-porous layer of III-nitride material covering the porous region following porosification. This non-porous cap layer may advantageously allow better overgrowth of further material above the porous region.

[0139] As the porosification method of PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728) can be carried out on entire semiconductor wafers, no processing/patterning/treatment is needed to prepare the template for porosification.

Figure 4 - Connecting Laver

[0140] After formation of the porous layer, a III-nitride LED epitaxy structure can be grown onto the porous template/pseudo-substrate provided by the porous layer and the non-porous cap layer.

[0141] The first layer for growth of the LED structure onto the template may be termed a connecting layer 1.

[0142] Although it is possible for an LED epitaxial structure to be grown directly onto the non-porous cap layer, it is preferable that a connecting layer 1 is provided over the cap layer before overgrowth of the LED structure. The inventors have found that the use of a III-nitride connecting layer 1 between the porous region and the LED epitaxy structure may advantageously ensure a good epitaxial relationship between the LED and the porous template/substrate. The growth of this layer makes sure that subsequent overgrowth on top of the connecting layer is smooth and epitaxial and suitably high quality.

[0143] The connecting layer 1 is formed of III-nitride material and may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layer).

[0144] The connecting layer can be a doped or un-doped layer. The connecting layer can optionally be doped with suitable n-type dopant materials , e.g Si, Ge, C, O. The III-nitride layer may have a doping concentration between 1×10.sup.17 cm.sup.-3 - 5×10.sup.20 cm.sup.-3.

[0145] The thickness of this connecting layer is preferably at least 100 nm, and can be for example between 100-10000 nm.

Figure 5 - N-Doped Region

[0146] After the growth of the connecting layer, a bulk n-doped III-nitride region 2 is grown.

[0147] The n-doped region 2 may comprise or consist of a III-nitride layer containing Indium, or a stack of thin III-nitride layers with or without indium, or a bulk layer or stack of III-nitride layers with a variation in atomic percentage of indium across the layer or stack is grown. For example, the n-doped region may be a layer of n-GaN, or a layer of n-InGaN, or alternatively the n-doped region may be a stack of n-GaN/n-InGaN alternating layers, or a stack of n-InGaN/n-InGaN alternating layers having different quantities of indium in alternating layers.

[0148] Preferably the n-doped region 2 comprises indium, so that the crystalline lattice of the n-doped region has similar lattice parameters to the lattice of the InGaN light emitting layer in the LED. The Indium atomic percentage in the n-doped region may vary between 0.1 - 25 % for example.

[0149] In preferred embodiments, the indium content of the n-doped region is within 20 at%, or within 15 at%, or within 10 at%, or within 5 at% of the indium content of the InGaN light emitting layer. This may advantageously ensure that the lattice parameters of the n-doped region are sufficiently similar to those of the InGaN light emitting layer to avoid excessive strain between these layers.

[0150] The total thickness of the n-doped region may be at least 2 nm, or at least 5 nm, or at least 10 nm, or at least 20 nm. The thickness of the n-doped region may vary between 2 nm -5000 nm, or even thicker, for example. If the n-doped region comprises a stack of layers, the thickness of each individual layer in the stack is preferably between 1-40 nm.

[0151] The n-doped region preferably has an n-type doping concentration between 1×10.sup.17 cm.sup.-3 -5×10.sup.20 cm.sup.-3, preferably between 1×10.sup.18 cm.sup.-3 - 5×10.sup.20 cm.sup.-3, particularly preferably greater than 1×10.sup.18 cm.sup.-3.

Figure 6 - Light Emitting Region

[0152] After growth of the n-doped region 2, an underlay or pre-layer or pre-well (not labelled in FIG. 6) may be grown, in order to release the strain in the light emitting layer(s). The underlay can be a single layer or stack/multi-layers of GaN, InGaN, or GaN/InGaN, or InGaN/InGaN. Alternatively, the underlay may have a structure similar to InGaN QW/GaN quantum barrier but with a lower proportion of indium. For example, before depositing the light emitting layer having a relatively high proportion of indium, an underlay consisting of a layer of bulk InGaN having a lower proportion of indium than the light emitting layer may be grown. Alternatively, the underlay may take the form of an InGaN “dummy” QW with a lower proportion of indium than the light emitting layer, and one or more GaN quantum barriers.

[0153] After growth of the n-doped region 2 and optionally the underlay, a light emitting region 3 containing an InGaN light emitting layer is grown.

[0154] The light emitting region 3 may contain at least one InGaN light emitting layer. Each InGaN light emitting layer may be an InGaN quantum well (QW). Preferably the light emitting region may comprise between 1-7 quantum wells. Adjacent quantum wells are separated by barrier layers of III-nitride material having a different composition to the quantum wells.

[0155] The light emitting layer(s) may be referred to as “quantum wells” throughout the present document, but may take a variety of forms. For example, the light emitting layers may be continuous layers of InGaN, or the layers may be continuous, fragmented, broken layers, contain gaps, or nanostructured so that the quantum well effectively contains a plurality of 3D nanostructures behaving as quantum dots.

[0156] The quantum wells and barriers are grown in a temperature range of 600 - 800° C.

[0157] Each quantum wells consists of an InGaN layer with atomic indium percentage between 15-40%. Preferably the light-emitting indium gallium nitride layer(s) and/or the quantum wells have the composition In.sub.xGa.sub.1-xN, in which 0.15 ≤ x ≤ 0.40, preferably 0.20≤ x ≤ 0.40 or 0.26 ≤ x ≤ 0.40, particularly preferably 0.30 ≤ x ≤ 0.40.

[0158] The thickness of each quantum well layer may be between 1.5-8 nm, preferably between 1.5 nm and 6 nm, or between 1.5 nm and 4 nm.

[0159] The quantum wells may be capped with a thin (0.5-3 nm) III-nitride QW capping layer, which may contain one or a combination of these elements: Al, Ga, In (ternary of quaternary layer)

[0160] The QW capping layer, which is the layer added immediately after QW growth, can be AlN, AlGaN of any Al% 0.01-99.9%, GaN, InGaN of any In% 0.01-30%.

[0161] The III-nitride QW barriers separating the light emitting layers (quantum wells) may contain one or a combination of these elements: Al, Ga, In (ternary of quaternary layer). The QW barrier can be AlN, AlGaN of any Al% 0.01-99.9%, GaN and InGaN of any In% 0.01-15%. Preferably the QW barrier layers contain AlN and/or AlGaN.

[0162] The QW capping layer(s) and QW barriers are not indicated with individual reference numerals in the Figures, as these layers form part of the light emitting region 3.

[0163] The QW capping layers may be grown after each QW but before the barrier growth. For example, if an LED contains 3 QWs then each of these QWs may be overgrown with a QW capping layer and then a QW barrier layer, so that the light emitting region contains 3 such QW capping layers and three such QW barrier layers. [0164] 1. One can grow the cap at the same conditions as the QW. [0165] 2. One can ramp without growth to higher temperature, and grow this cap (effectively this is an annealing step) and here the ramp can be carried out in a different gas mixture. [0166] 3. One can ramp and grow during the temperature ramp.

[0167] For the manufacture of red LEDs the large amount of Indium in the light emitting layer(s) makes the capping layer even more important, as previous attempts to manufacture red LEDs have failed due to not enough Indium being incorporated. So capping is very important to make sure that there is sufficient Indium trapped within the light emitting region.

Figure 7 - Cap Layer

[0168] After growth of the light emitting layer(s) a non-doped cap layer 4 is grown. Non-doped cap layer 4 may be termed a light-emitting-region cap layer, as this layer is formed after growth of the complete light emitting region, for example after the growth of the stack of QWs, QW capping layers and QW barrier layers.

[0169] The cap layer (light-emitting-region cap layer) 4 is a standard layer which is very well known in the growth schemes for III-nitride LEDs.

[0170] The thickness of the cap layer can be between 5-30 nm, preferably between 5-25 nm or 5-20 nm.

[0171] The purpose of the light-emitting-region cap layer 4, is to protect the indium in the light emitting region (QW stack) and prevent it from desorbing/evaporating during subsequent processing. Because the InGaN QW is normally grown at lower temperature, that is not favourable for GaN/AlGaN, there is typically a temperature ramp step needed before further layers can be overgrown above the light emitting region. The cap layer is used to ensure that the InGaN light emitting layer(s) are properly capped and protected, so that there is a chance and time window to change the p-doped layer growth conditions for better material quality. The light-emitting-region cap layer 4 also ensures that no Mg dopant is entering the QW region during the growth of p-type layers.

Electron Blocking Laver (EBL)

[0172] After the growth of quantum wells, capping and barrier layers, an electron blocking III-nitride layer (EBL) 5 containing Aluminium is grown. The Al% can be between 5-25% for example, though higher Al content is possible.

[0173] The EBL is doped with a suitable p-type doping material. The p-type doping concentration of the EBL is preferably between 5×10.sup.18 cm.sup.-3 - 8×10.sup.20 cm.sup.-3

[0174] The thickness of the EBL can be between 10-50 nm, preferably 20 nm.

Figure 8 - P-Doped Layer

[0175] A p-doped layer 6 is grown above the electron blocking layer (EBL) 5.

[0176] The p-type region is preferably doped with Mg, and the p-type doping concentration of the p-type layer is preferably between 5×10.sup.18 cm.sup.-3 - 8×10.sup.20 cm.sup.-3.

[0177] The p-doped III-nitride layer may contain In and Ga.

[0178] The doping layer is preferably between 20-200 nm thick, particularly preferably between 50-100 nm thick. The doping concentration may vary across the p-type layer and can have a spike in doping levels in the last 10-30 nm of the layer towards the LED surface, in order to allow better p-contact.

[0179] For activation of Mg acceptors in the p-doped layer, the structure may be annealed inside of MOCVD reactor or in an annealing oven. The annealing temperature may be in the range of 700-850° C. in N.sub.2 or in N.sub.2/O.sub.2 ambient.

[0180] As both the EBL and the p-doped layer are p-type doped, these layers may be referred to as the p-doped region.

Figure 9 - Transparent Conducting Laver

[0181] The stack of active semiconductor layers is covered with a transparent conducting layer 7. The transparent conducting layer can be made of Ni/Au , indium tin oxide, indium zinc oxide, graphene, Pd, Rh, silver, ZnO etc., or a combination of these materials.

[0182] The thickness of the transparent conducting layer can be between 10-250 nm.

[0183] Transparent conducting layers are well known in the art, and any suitable material and thickness may be used.

[0184] An annealing step may be required for making the p-contact ohmic.

Figure 10

[0185] Depending on the LED structure being manufactured, the semiconductor structure may be processed into LED, mini-LED or micro-LED devices.

[0186] Normal LEDs are typically larger than 200 .Math.m (referring to the lateral dimensions of width and length of the LED structure. Mini-LEDs are typically 100-200 .Math.m in lateral size, while Micro-LEDs are typically less than 100 .Math.m in size.

[0187] FIG. 10 onwards illustrates the semiconductor structure following etching of layers 2-7 of the semiconductor structure into multiple discrete LED stacks, or mesas, each having the same structure.

[0188] In the next step, the transparent conducting layer 7 is structured in such a way that it covers only the top surface of the active emission element. The structuring can be done using standard semiconductor processing methods that included resist coating and photolithography. The transparent conducting layer is etched by using wet chemistry or a sputter etch process using Argon. This step is followed by wet or dry etching of the III-nitride structure. An inductively couple plasma reactive ion etching, only reactive ion etching or neutral beam etching is used to create mesas in the III-nitride layer. The dry etch process may include either one or more of Cl, Ar, BCl.sub.3, SiCl.sub.4 gases.

[0189] The purpose of this step is to isolate the individual emitting elements and access the buried n-doped layer of the p-n junction.

[0190] After the dry etch process a wet etch process is done to remove the dry etching damage from the sidewalls of the mesa. The wet chemistry may involve KOH (1-20%), TMAH or other base chemistries.

Figure 11 - Passivation

[0191] The next step is to deposit a passivation layer 8 or a combination of passivation layers. The starting passivation layer can be Al2O3 (10-100 nm) (deposited by atomic layer depositions) followed by sputtered or plasma enhanced chemical vapor deposited SiO2, SiN or SiON (50-300 nm).

[0192] The Al2O3 can be deposited between 50-150° C.

[0193] The SiO2, SiN and SiON can be deposited between 250-350° C.

[0194] The sputter process can be done at room temperature.

Figure 12

[0195] The next step is to create openings in the oxide passivation layer 8 to expose the p- and n-GaN. This can be done via wet or dry etching or a combination of both.

[0196] For wet etching buffered oxide etch, diluted hydrofluoric acid phosphoric acid or a mixture of these can be used.

Figure 13

[0197] The final step in the device fabrication is to cover the openings in the oxide with metal layers 9. The covering can be done with a single step or multiple steps. In this example a single step is used to simplify the details.

[0198] The metal may contain Ti, Pt, Pd, Rh, Ni, Au. The thickness of the complete metal stack can be between 200-2000 nm.

[0199] And after all processing, the substrate can be thinned, and/or the porous region can be removed so that the connecting layer 1 is exposed.

[0200] Surface structuring or texturing can be done on the substrate, at the porous region, or layer 1 to enhance the light output and control the emission angle, as well as other optical engineering and design.

[0201] Finally, the wafer/devices can be flipped, and bonded to another carrier substrate either can be silicon/sapphire or any type as passive devices, alternatively, the devices can be bonded to a CMOS silicon backplane for active matrix micro-LED display panel.

Figures 14-18

[0202] FIG. 14 shows that an InGaN LED over a porous layer according to a preferred embodiment of the present invention emits at a peak wavelength of around 625 nm.

[0203] FIGS. 15 and 16 compare the emission characteristics of an InGaN LED on a non-porous substrate (FIG. 15) and the same InGaN LED grown on a template comprising a porous layer of III-nitride material. Comparison of these two graphs demonstrates the shift towards longer emission wavelengths caused by the porous underlayer, as the emission of the LED on the porous template is consistently between 21 nm and 45 nm longer than that of the same LED on the non-porous template.

[0204] FIGS. 17 and 18 compare the I-V characteristics of InGaN micro-LEDs on a non-porous substrate (FIG. 17) with InGaN micro-LEDs on a template containing a porous layer.