DIGITAL-TO-ANALOG CONVERTER AND METHOD FOR DIGITAL-TO-ANALOG CONVERSION

Abstract

A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.

Claims

1. A digital-to-analog converter, DAC, for use in an incremental analog-to-digital converter, iADC, the DAC being configured for converting a multi-bit word to an analog feedback signal, the multi-bit word representing an integer within a range of integers, the DAC comprising a mismatch shaping logic block configured to generate a selection vector with a predefined number of bits based on the multi-bit word, a plurality of output elements configured to generate respective analog portions based on the selection vector, and a signal combiner for combining the analog portions to the analog feedback signal, wherein in the mismatch shaping logic block a predetermined number of switching blocks are arranged cascaded, each switching block is configured to receive at least a portion of the multi-bit word, to split the portion into two sub-portions and to forward each sub-portion to one further subsequent switching block or to one of the output elements, respectively, in each switching block a weight factor is adjusted by multiplying the weight factor with the difference of the two sub-portions, and each switching block comprises a weight accumulator provided for accumulating successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word coming to the respective switching block at a subsequent clock period within the conversion cycle of the iADC is determined based on the sign of the weight accumulator.

2. The DAC according to claim 1, wherein in each clock period within the conversion cycle of the iADC, a new weight factor is provided, wherein successive weight factors decrease according to a monotonically decreasing function.

3. The DAC according to claim 1, wherein each switching block further comprises a divider configured to split the portion of the multi-bit word into two preliminary sub-portions with equal value, a selector configured to select one of the preliminary sub-portions, the selection being based on the sign of the weight accumulator, and an adder configured to add a remainder of the splitting conducted by the divider to the preliminary sub-portion selected by the selector.

4. The DAC according to claim 1, wherein each switching block further comprises a first input for receiving the portion of the multi-bit word, a second input for providing the weight factors, a third input for providing a clock signal, the clock signal being provided for the weight accumulator to accumulate subsequent adjusted weight factors, a detector configured to detect, if an integer represented by the portion of the multi-bit word is even or odd, a divider configured to split the portion of the multi-bit word into two preliminary sub-portions, the preliminary sub-portions having a smaller absolute value than the portion of the multi-bit word, a selector configured to select one of the preliminary sub-portions, the selection being based on the sign of the weight accumulator, and an adder configured to add a remainder of the splitting conducted by the divider to the preliminary sub-portion selected by the selector, a first output for forwarding the first sub-portion, a second output for forwarding the second sub-portion.

5. The DAC according to claim 4, wherein in each switching block the divider is configured to split the portion of the multi-bit word into two preliminary sub-portions with equal value, and the adder is configured to add the remainder of the splitting conducted by the divider to the preliminary sub-portion selected by the selector.

6. The DAC according to claim 3, wherein in the first switching block receiving the multi-bit word, a further detector is configured to detect a sequence of multi-bit words representing even integers, which are larger than the minimum and smaller than the maximum integer within the range of integers, and for each r-th multi-bit word of the detected sequence, where r is a natural number, the adder is configured to add a unit to one of the two preliminary sub-portions and a subtractor is configured to subtract the unit from the other preliminary sub-portion, wherein the selector determines the respective preliminary sub-portions based on the sign of the weight accumulator.

7. The DAC according to claim 3, wherein in the first switching block receiving the multi-bit word, a further detector is configured to detect multi-bit words representing even integers, which are larger than the minimum and smaller than the maximum integer within the range of integers, a ditherer determines by random to split a multi-bit word detected by the further detector into two portions of equal or unequal value, respectively, and in case that the ditherer determined unequal splitting, the adder is configured to add a unit to one of the two preliminary sub-portions and a subtractor is configured to subtract the unit from the other preliminary sub-portion, wherein the selector determines the respective preliminary sub-portions based on the sign of the weight accumulator.

8. The DAC according to claim 1, the DAC further comprising a weight generator configured to provide successive weight factors for each clock period within the conversion cycle of the iADC, wherein the weight generator generates monotonically decreasing weight factors.

9. The DAC according to claim 8, wherein the weight generator comprises a generator input receiving a digital starting factor, a generator output providing the weight factor, at least one integration stage coupling the generator input to the generator output, the integration stage further comprising a stage input to receive a digital input signal from the generator input or from a preceding integration stage, respectively, a stage output to provide a digital output signal for a subsequent integration stage or the generator output, respectively, a stage combiner configured to combine the digital input signal and a feedback from the digital output signal, and a register configured to process the combination of the digital input signal and the feedback from the digital output signal, the register providing the digital output signal.

10. The DAC according to claim 8, wherein the weight generator forwards the respective weight factor for a given clock period of the conversion cycle to each switching block.

11. An incremental analog-to-digital converter, iADC, comprising a DAC according to claim 1, the iADC further comprising an input for providing an analog input signal, a combiner being configured to combine the analog input signal with the analog feedback signal from the DAC, a loop filter being configured for filtering a combination of the analog input signal and the analog feedback signal, an N-level quantizer for generating the multi-bit word based on an output of the loop filter, a feedback path comprising the DAC, the DAC being configured for converting the multi-bit word from the N-level quantizer to an analog feedback signal for the combiner of the iADC, and a decimation filter provided for filtering the multi-bit word to generate a digital system output signal.

12. An electronic device comprising the iADC according to claim 11, the electronic device further being connected to at least one sensor, wherein the iADC is configured to perform an analog-to-digital conversion of a signal provided by the at least one sensor.

13. A digital-to-analog conversion method for converting a multi-bit word representing an integer within a range of integers to an analog feedback signal of an incremental analog-to-digital converter, iADC, the digital-to-analog conversion method comprising generating a selection vector with a predefined number of bits based on the multi-bit word, generating, with a plurality of output elements, respective analog portions based on the selection vector, combining the analog portions to the analog feedback signal, wherein the generation of the selection vector comprises successive splitting of the multi-bit word x[n] into portions and sub-portions, respectively, adjusting of weight factors by multiplying the weight factors with the difference of two respective sub-portions, and accumulating successive adjusted weight factor, wherein the way of splitting portions of further multi-bit words at subsequent clock periods within the conversion cycle of the iADC is determined based on the sign of the accumulation of adjusted weight factors.

14. The method according to claim 13, further comprising: in each clock period within the conversion cycle of the iADC providing a new weight factor, wherein successive weight factors decrease according to a monotonically decreasing function.

15. The method according to claim 13, further comprising generating successive weight factors for each clock period within the conversion cycle of the iADC by use of a weight generator, the generation of weight factors further comprising receiving a digital starting factor at a generator input, providing at least one integration stage coupling the generator input to a generator output, at a stage input of the integration stage, receiving a digital input signal from the generator input or from a preceding integration stage, combining the digital input signal and a feedback from a digital output signal, at a stage output of the integration stage, providing the digital output signal by processing the combination of the digital input signal and the feedback from the digital output signal for a subsequent integration stage or the generator output, and providing the weight factors at the generator output.

16. The method according to claim 13, further comprising detecting, if the integer represented by the portion of the multi-bit word coming to a respective switching block is even or odd, splitting the portion of the multi-bit word into two preliminary sub-portions of equal value, selecting one preliminary sub-portion based on the sign of the accumulation of adjusted weight factors, and adding a remainder of the splitting to the selected preliminary sub-portion.

17. The method according to claim 13, in a first switching block receiving the multi-bit word further comprising detecting sequences of multi-bit words representing even integers, which are larger than the minimum and smaller than the maximum integer within the range of integers, and for each r-th multi-bit word of the detected sequence, where r is a natural number, adding a unit to one of the two preliminary sub-portions and subtracting the unit from the other preliminary sub-portion, wherein the respective preliminary sub-portions are selected based on the sign of the accumulation of adjusted weight factors.

18. The method according to claim 13, in the first switching block receiving the multi-bit word further comprising detecting multi-bit words representing even integers, which are larger than the minimum and smaller than the maximum integer within the range of integers, determining by random to split a detected multi-bit word representing an even integer into two portions of equal or unequal value, respectively, and in case of determination of unequal splitting, adding a unit to one of the two preliminary sub-portions and subtracting the unit from the other preliminary sub-portion, wherein the respective preliminary sub-portions are selected based on the sign of the accumulation of adjusted weight factors.

19. A digital-to-analog converter, DAC, for use in an incremental analog-to-digital converter, iADC, the DAC being configured for converting a multi-bit word to an analog feedback signal, the multi-bit word representing an integer within a range of integers, the DAC comprising a mismatch shaping logic block configured to generate a selection vector with a predefined number of bits based on the multi-bit word, a plurality of output elements configured to generate respective analog portions based on the selection vector, and a signal combiner for combining the analog portions to the analog feedback signal, wherein in the mismatch shaping logic block a predetermined number of switching blocks are arranged cascaded forming layers of switching blocks, each switching block is configured to receive at least a portion of the multi-bit word, to split the portion into two sub-portions and to forward each sub-portion, wherein switching blocks of preceding layers are configured to forward the sub-portions to one further switching block of a subsequent layer and switching blocks of a last layer are configured to forward the sub-portions to one of the output elements, in each switching block a weight factor is adjusted by multiplying the weight factor with the difference of the two sub-portions, wherein in each clock period within the conversion cycle of the iADC a new weight factor is provided by a weight generator, wherein successive weight factors decrease according to a monotonically decreasing function, and each switching block comprises a weight accumulator provided for accumulating successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word coming to the respective switching block at a subsequent clock period within the conversion cycle of the iADC is determined based on the sign of the weight accumulator.

20. The DAC according to claim 19, the DAC further comprising a weight generator, wherein the weight generator is re-initialized at predetermined time intervals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0101] The improved conversion concept will be described in more detail below for several embodiments with reference to the drawings. Identical reference numerals designate signals, elements or components with identical functions. If signals, elements or components correspond to one another in function, a description of them will not necessarily be repeated in each of the following figures.

[0102] FIG. 1 shows a schematic of an incremental analog-to-digital converter, iADC.

[0103] FIG. 2 shows a schematic of an embodiment of a digital-to-analog converter, DAC.

[0104] FIG. 3 shows a selection vector according to an embodiment of a digital-to-analog converter, DAC.

[0105] FIG. 4 shows a schematic of a switching block according to an embodiment of a digital-to-analog converter, DAC.

[0106] FIG. 5 shows a schematic of a switching block according to another embodiment of a digital-to-analog converter.

[0107] FIG. 6 shows two flow charts of even value detection according to the embodiment of FIG. 5.

[0108] FIG. 7 shows a schematic of a weight generator according to an embodiment of a digital-to-analog converter, DAC.

[0109] FIG. 8 shows schematic of an electronic device according to an embodiment.

DETAILED DESCRIPTION

[0110] In FIG. 1 a schematic of an incremental analog-to-digital converter, iADC, is shown. Since the functional principal of an iADC is known for one skilled in the art, the schematic is described only roughly.

[0111] The iADC 1 comprises an input 2 for providing an analog input signal A. The iADC further comprises a feedback path 3 with a digital-to-analog converter, DAC 4. The DAC 4 provides an analog feedback signal y[n] for each clock period n within the conversion cycle of the iADC. Both analog input signal A and analog feedback signal y[n] are forwarded to a combiner 5 of the iADC 1. The combiner 5 sums up the analog input signal A and the negated analog feedback signal y[n] and forwards the combined signal C to a loop filter 6. This means, the combiner subtracts the analog feedback signal y[n] from the analog input signal A. The loop filter 6 is configured to filter the combined signal C according to known filtering techniques. The filtered signal F is then forwarded to an N-level quantizer 7. The N-level quantizer 7 generates from the filtered signal F a multi-bit word x[n] at each clock period n. The multi-bit word x[n] can represent N different integers, depending on active bits of the multi-bit word, where N is a natural number. The multi-bit word x[n] is forwarded via the feedback path 3 to the DAC 4, which is configured to convert the multi-bit word x[n] into the analog feedback signal y[n].

[0112] The DAC 4 within the feedback path 3 comprises a mismatch shaping logic block 8. The mismatch shaping logic block is configured to generate a selection vector s[n] with a predefined number of bits. The number of bits is based on the multi-bit word x[n]. The DAC 4 further comprises a plurality of output elements 9 and a signal combiner 10. The number of output elements 9 corresponds to the number of bits of the selection vector s[n]. The output elements 9 are configured to generate respective analog portions y.sub.i[n] based on the selection vector s[n], where i is the numbering of the output elements 9. This means that each bit of the selection vector s[n] is associated with a corresponding output element 9. Each output element 9 generates an analog portion y.sub.i[n] if the corresponding bit of the selection vector s[n] is active. If the corresponding bit of the selection vector s[n] is inactive, the output element 9 generates no analog portion y.sub.i[n] or an analog portion y.sub.i[n] of opposite sign. The signal combiner 10 combines all analog portions y.sub.i[n] generated by the output elements 9 to the analog feedback signal y[n].

[0113] This means that the signal combiner 10 sums up all analog portions y.sub.i[n].

[0114] The iADC 1 further comprises a decimation filter 11. The decimation filter 11 receives the multi-bit word x[n] of each clock period n within the conversion cycle of the iADC 1. The decimation filter 11 is configured to filter the multi-bit words x[n] in order to generate a digital system output signal D. Filtering techniques, which can be used by the decimation filter 11, are known by the skilled person in general.

[0115] In FIG. 2 a schematic of an embodiment of the DAC 4 is shown. In this example, the DAC 4 has a limited resolution. However, the DAC 4 can be adjusted easily in order to achieve a lower or a higher resolution. Thus, the shown schematic of FIG. 2 has to be understood as an exemplary embodiment without loss of generality.

[0116] The DAC 4 comprises several components, namely the mismatch shaping logic block 8, the plurality of output elements 9 and the signal combiner 10. These components are connected by several signals. The mismatch shaping logic block 8 comprises a predetermined number of switching blocks 12, which are arranged cascaded. The number of switching blocks 12 is predetermined by the multi-bit word representing integers within a range of integers. For the same reason the number of output elements 9 is predetermined. In this example, the mismatch shaping logic block 8 comprises seven switching blocks 12a-g and eight output elements 9a-h.

[0117] With the DAC of FIG. 2 it is possible to convert a multi-bit word x[n] representing integers within a range covering nine different integers. The integers covered by the range of integers corresponds to the levels of the N-level quantizer 7. In this example the N-level quantizer 7 is a 9-level quantizer generating a 4-bit word.

[0118] The switching blocks 12 are arranged cascaded forming layers of switching blocks L.sub.j. The first layer of switching blocks L.sub.1 comprises one switching block 12a. From layer L.sub.j to layer L.sub.j+1 the number of switching blocks 12 is doubled. Thus, in this example, the second layer L.sub.2 comprises two switching blocks 12b-c and the third layer L.sub.3 comprises four switching blocks 12d-g.

[0119] In FIG. 2, the number of bits of incoming and outgoing signals of each switching block is indicated by numerals next to lines crossing the signal line. The switching block 12a of the first layer L.sub.1 receives the multi-bit word x[n] coming from the N-level quantizer, which is a 4-bit signal in this case. The multi-bit word x[n] is split by the switching block 12a into two portions x.sub.1234 [n] and x.sub.5678[n] of the multi-bit word, which are forwarded to the switching blocks 12b-c of the second layer L.sub.2. The portions x.sub.1234 [n] and x.sub.5678 [n] of the multi-bit word x[n] are 3-bit signals, thus having one bit less than the multi-bit word x[n]. In the next step, the portion x.sub.1234[n] is split by the switching block 12b into the sub-portions x.sub.12[n] and x.sub.34[n], whereas the portion x.sub.5678[n] is split by the switching block 12c into the sub-portions x.sub.56[n] and x.sub.78[n]. The sub-portions x.sub.12[n], x.sub.34[n], x.sub.56 [n] and x.sub.78 [n] are 2-bit signals. They are forwarded to the switching blocks 12d-g of the third layer L.sub.3. The switching block 12d splits the sub-portion x.sub.12[n] into the further sub-portions x.sub.1[n] and x.sub.2[n], both further sub-portions being 1-bit signals. The switching block 12e splits the sub-portion x.sub.34[n] into the further sub-portions x.sub.3[n] and x.sub.4[n], both further sub-portions being 1-bit signals. The switching block 12f splits the sub-portion x.sub.56[n] into the further sub-portions x.sub.5[n] and x.sub.6[n], both further sub-portions being 1-bit signals. The switching block 12g splits the sub-portion x.sub.78[n] into the further sub-portions x.sub.7[n] and x.sub.8[n], both further sub-portions being 1-bit signals.

[0120] Each further sub-portion x.sub.1-8[n] is a component of the selection vector s[n], as shown in FIG. 3. Each further sub-portion x.sub.1-8[n] is forwarded to one respective output element 9a-h. The output elements 9 can be 1-bit DACs. The output elements 9 are triggered depending on the selection vector s[n], i.e. the bits of the selection vector comprising the further sub-portion x.sub.1-8[n]. Each output element 9 generates an analog portion y.sub.i[n] if the corresponding bit, i.e. x.sub.i[n], of the selection vector s[n] is active. If the corresponding bit, i.e. x.sub.i[n], of the selection vector s[n] is inactive, the output element 9 generates no analog portion y.sub.i[n] or an analog portion y.sub.i[n] of opposite sign.

[0121] The signal combiner 10 combines all analog portions y.sub.i[n] generated by the output elements 9 to the analog feedback signal y[n]. The analog feedback signal y[n] is further forwarded to the combiner 5 of the iADC.

[0122] In FIG. 3 an example of the selection vector s[n] is shown. In this example, the selection vector s[n] has at least eight components x.sub.i[n], controlling at least eight output elements 9. In case that the DAC 4 has a higher resolution than the DAC 4 from FIG. 2, the mismatch logic block 8 comprising more than seven switching blocks 12 and more than eight output elements 9. In this case the selection vector s[n] comprises as much components as output elements 9, which is indicated by the dots at the end of the selection vector s[n].

[0123] In FIG. 4 a schematic of an exemplary switching block 12 according to an embodiment of the DAC 4 is shown. The switching block 12 shown has to be understood as exemplary embodiment according to the basic idea of the proposed MMS logic. Further implementations of the proposed MMS logic, which are different from FIG. 4 but have the same function, may become readily apparent for the skilled reader.

[0124] Furthermore, the switching block 12 shown can be any switching block 12 within the mismatch shaping logic block 8 of the DAC 4. This means that the switching block 12 of FIG. 4 can be arranged in any layer L.sub.j of the mismatch shaping logic block 8. The switching block 12 has a first input 13 for receiving the multi-bit word x[n] or at least a portion x.sub.k[n] of the multi-bit word x[n]. Without loss of generality the switching block 12 of FIG. 4 receives an incoming signal, which comprises the portion x.sub.abcd[n] of the multi-bit word x[n], and which has L bits, where L is a natural number higher than 1.

[0125] The switching block 12 further comprises a second input 14 for providing a weight factor W[n] at each clock period n of the conversion cycle of the iADC 1. The weight factor W[n] can be a signal comprising K bits, where K is natural number. The switching block further comprises a third input 15 for providing a clock signal CLK.

[0126] The portion x.sub.abcd[n] of the multi-bit word x[n] is forwarded to a detector 16. The detector 16 detects whether the portion x.sub.abcd[n] represents an even or an odd integer. If the portion x.sub.abcd[n] represents an even integer, the detector 16 outputs “0”. Otherwise, if the portion x.sub.abcd[n] represents an odd integer, the detector 16 outputs “1”. The output of the detector 16 can be understood as remainder ε of a division of the portion x.sub.abcd[n].

[0127] The portion x.sub.abcd[n] of the multi-bit word x[n] is also forwarded to a divider 17. The divider 17 splits the portion x.sub.abcd[n] into two equal preliminary sub-portions x.sub.ab[n] and x.sub.cd[n]. The splitting can be done by right-shifting the bits of the portion x.sub.abcd[n]. This means that the integer represented by the portion x.sub.abcd[n] is divided by 2 and rounded down. The result of this division is assigned to both preliminary sub-portions x.sub.ab[n] and x.sub.cd[n]. In case that the portion x.sub.abcd[n] represents an even integer, there is a remainder ε=0 left from this division, i.e. the two preliminary sub-portions x.sub.ab[n] and x.sub.cd[n] together add up to the portion x.sub.abcd[n]. In case that the portion x.sub.abcd[n] represents an odd integer, there is a remainder ε=1 left from this division. This remainder ε is outputted by the detector 16, as described above.

[0128] The switching block 12 further comprises an adder 18. The adder 18 is configured to add the remainder ε of the division conducted by the divider 17 to one of the preliminary sub-portions x.sub.ab[n] or x.sub.cd[n]. The adder comprises a first AND-gate 19 and a second AND-gate 20. One of the input terminals of the first AND-gate 19 is inverted. The outputted remainder ε of the detector 16 is forwarded to one input terminal each of both AND-gates 19, 20, which is not inverted. The adder further comprises a first sum operator 21 configured to add the remainder ε to the first preliminary sub-portion x.sub.ab[n].

[0129] The output of the first AND-gate 19 is connected to the first sum operator 21. The adder further comprises a second sum operator 22 configured to add the remainder ε to the second preliminary sub-portion x.sub.cd[n]. The output of the second AND-gate 20 is connected to the second sum operator 22.

[0130] The switching block 12 further comprises a selector 23 configured to select one of the preliminary sub-portions x.sub.ab[n] or x.sub.cd[n], to which the remainder ε is to be added. Herein, the selection is based on accumulated adjusted weight factors W[n] of preceding clock periods. The selector 23 outputs 0, if the remainder ε is to be added to the first preliminary sub-portion x.sub.ab[n]. Instead, the selector 23 outputs 1, if the remainder ε is to be added to the second preliminary sub-portion x.sub.cd[n]. The outputted selection signal δ of the selector 23 is forwarded to the other respective input terminals of the AND-gates 19, 20 of the adder 18. Thus, the selection signal δ is forwarded to the inverted input terminal of the first AND-gate 19 and to the second input terminal of the second AND-gate 20, which is not inverted.

[0131] Only if both input terminals of one of the AND-gates 19, 20 are “1”, the respective AND-gate forwards “1” to the corresponding sum operator 21, 22, leading to an addition to the corresponding preliminary sub-portion x.sub.ab[n] or x.sub.cd[n], respectively. This means that in case that the remainder ε is “0” there is no addition at all. In case that the remainder ε is “1” and the selection signal δ is “0”, the first AND-gate is activated since the selection signal δ is inverted, thus becoming “1”. In case that the remainder ε is “1” and the selection signal δ is “1”, the second AND-gate is activated.

[0132] The switching block 12 further comprises a first output 24 forwarding the first sub-portion x.sub.ab[n]. Additionally, the switching block 12 comprises a second output 25 forwarding the second sub-portion x.sub.cd[n]. Both sub-portions x.sub.ab[n], x.sub.cd[n] have L−1 bits, thus having one bit less than the portion x.sub.abcd[n] of the multi-bit word x[n]. Furthermore, in case that the portion x.sub.abcd[n] represents an even integer, both sub-portions x.sub.ab[n], x.sub.cd[n] have an equal value. In case that the portion x.sub.abcd[n] represents an odd integer, one of the sub-portions x.sub.ab[n], x.sub.cd[n] is larger by 1 than the corresponding other.

[0133] The weight factor W[n] provided by the second input 14 of the switching block 12 is adjusted by multiplying it with the difference between the two outputted sub-portions x.sub.ab[n], x.sub.cd[n]. This is achieved by use of a first logical operator 26 and a second logical operator 27. The first logical operator 26 is connected to the selection signal δ for evaluating. If the selection signal δ is “0”, the weight factor W[n] is multiplied by −1 and forwarded to the second logical operator 27. If the selection signal δ is “1”, the weight factor W[n] is multiplied by +1, i.e. is left unchanged, and forwarded to the second logical operator 27. The second logical operator 27 receives the remainder ε for evaluating. If the remainder is “1” since the integer represented by the portion x.sub.abcd[n] is odd, the second logical operator 27 outputs the by the first logical operator 26 adjusted weight factor W′[n]. If the remainder is “0” since the integer represented by the portion x.sub.abcd[n] is even, the weight factor W′[n] is multiplied by 0 and forwarded further. In this case the second logical operator 27 outputs “0”.

[0134] The switching block 12 further comprises a weight accumulator 28 provided for accumulating successive adjusted weight factors W′[n]. The weight accumulator 28 comprises a sum operator 29 and a storage 30. The sum operator 29 sums up the adjusted weight factor W′[n] coming from the second logical operator 27 and the accumulation R.sub.n-1 of adjusted weight factors W′[n] from preceding clock periods outputted by the storage 30. The sum is then stored as new accumulation R.sub.n-1 for the next clock period n+1 in the storage 30. The storage 30 receives the clock signal CLK for timed storing of the new accumulation R.sub.n-1. Storing the new accumulation R.sub.n-1 into the storage 30 is conducted later than selecting one of the preliminary sub-portions x.sub.ab[n], x.sub.cd[n] by the selector 23. The storage 30 forwards the accumulation R.sub.n-1 of adjusted weight factors W′[n] to the selector 23 for the subsequent clock period n+1.

[0135] In FIG. 5 a schematic of another exemplary switching block 12 according to an embodiment of the DAC 4 is shown. In particular, the switching block 12 of FIG. 5 can be the switching block 12 of the first layer L.sub.1 of the mismatch shaping logic block 8 receiving the multi-bit word x[n].

[0136] The switching block 12 of FIG. 5 is different from the switching block 12 of FIG. 4 in that it further comprises a further detector 41 receiving the multi-bit word. In one embodiment the further detector 41 detects sequences of multi-bit words x[n] representing even integers, which are not the minimum or maximum integer within the range of integers. In another embodiment the further detector 41 detects multi-bit words x[n] representing even integers, which are not the minimum or maximum integer within the range of integers, and further comprises a ditherer 42 determining by random how to split the detected multi-bit word. The further detector 41 outputs “0” or “1” depending on the detection. The outputted signal is denoted as a unit u. The further detector 41 is described in more detail in FIG. 6.

[0137] The switching block 12 of FIG. 5 differs from FIG. 4 also in comprising an OR-gate 43. The first input terminal of the OR-gate 43 is connected to an output of the further detector 41. The second input terminal is connected to the detector 16. The output terminal of the OR-gate 43 is connected to respective input terminals of the AND-gates 19, 20 of the adder 18. This means that in this embodiment the adder 18 is also configured to add the unit u outputted by the further detector 41 to one of the two preliminary sub-portions x.sub.1234[n] or x.sub.5678[n] generated by the divider 17.

[0138] Furthermore, the switching block 12 of FIG. 5 comprises a subtractor 44. The subtractor 44 is configured to subtract the unit u from the other one of the two preliminary sub-portions x.sub.1234[n] or x.sub.5678[n], respectively. The subtractor 44 comprises a first AND-gate 45 and a second AND-gate 46. One of the input terminals of the second AND-gate 46 is inverted. The outputted unit u of the further detector 41 is forwarded to one input terminal each of both AND-gates 45, 46, which is not inverted. The subtractor 44 further comprises a first difference operator 47 configured to subtract the unit u from the first preliminary sub-portion x.sub.1234[n]. The output of the first AND-gate 45 is connected to the first difference operator 47. The subtractor 44 further comprises a second difference operator 48 configured to subtract the unit u from the second preliminary sub-portion x.sub.5678[n]. The output of the second AND-gate 20 is connected to the second difference operator 48.

[0139] The outputted selection signal δ of the selector 23 is forwarded to the other respective input terminals of the AND-gates 45, 46 of the subtractor 44. Thus, the selection signal δ is forwarded to the inverted input terminal of the second AND-gate 46 and to the second input terminal of the first AND-gate 45, which is not inverted.

[0140] The switching block 12 of FIG. 5 also comprises a third logical operator 49 arranged between the first logical operator 26 and the second logical operator 27. The third logical operator 49 is connected to the output of the further detector 41, i.e. the unit u, for evaluating. If the unit u is “0”, the adjusted weight factor W′[n] coming from the first logical operator 26 is multiplied by 1, i.e. is left unchanged, and forwarded to the second logical operator 27.

[0141] If the unit u is “1”, the adjusted weight factor W′[n] coming from the first logical operator 26 is multiplied by 2 and forwarded to the second logical operator 27.

[0142] In FIG. 6a a flow chart of the logical operation of the further detector 41 according to one embodiment is shown. This embodiment refers to a further detector 41, which detects sequences of multi-bit words x[n] representing even integers, which are not the minimum or maximum integer within the range of integers.

[0143] The further detector 41 receives the multi-bit word x[n]. In the first step it is checked whether the multi-bit word represents an even integer. If the multi-bit word x[n] does not represent an even integer, a counter EvenCNT, which initially has the value 0, is reset to 0 and the further detector 41 outputs “0”, leading to equal splitting. If the multi-bit word x[n] represents an even integer, the counter is incremented by 1. In the latter case it is checked in a second step, whether the counter EvenCNT is larger than a parameter CNTLimit. For example, the parameter CNTLimit can be 1, if each second multi-bit word x[n] of a detected sequence shall be split into portions of unequal value. If the counter EvenCNT is less than or equal to the parameter CNTLimit, the further detector 41 outputs “0”. Otherwise, it is checked in a third step if the integer represented by the multi-bit word x[n] is smaller than the maximum and larger than the minimum integer of the range of integers. If so, the further detector 41 outputs “1”, leading to unequal splitting. Otherwise, the further detector 41 outputs “0”. The order of the second and third step can be reversed without impacting the overall result. The third step could alternatively also be executed before the first step without significantly impacting the overall performance.

[0144] In FIG. 6b a flow chart of the logical operation of the further detector 41 according to another embodiment is shown. This embodiment refers to a further detector 41, which detects multi-bit words x[n] representing even integers, which are not the minimum or maximum integer within the range of integers and where a ditherer 42 determines by random how to split the detected multi-bit word.

[0145] The further detector 41 receives the multi-bit word x[n]. In the first step it is checked whether the multi-bit word x[n] represents an even integer. If the multi-bit word x[n] does not represent an even integer the further detector 41 outputs “0”. Otherwise, a ditherer 42 determines by random how to split the multi-bit word x[n], i.e. to split it into two sub-portions of equal or unequal value. The ditherer 42 can be random number generator generating random numbers from 0 to 1. If the random number is smaller than 0.5 the further detector 41 outputs “0”, leading to equal splitting. Otherwise, it is checked in a next step if the integer represented by the multi-bit word x[n] is smaller than the maximum and larger than the minimum integer of the range of integers. If so, the further detector 41 outputs “1”, leading to unequal splitting. Otherwise, the further detector 41 outputs “0”. The steps can be rearranged in their order without affecting the overall functionality.

[0146] In FIG. 7 a schematic of a weight generator 31 according to an embodiment of the DAC 4 is shown. The weight generator 31 shown in FIG. 7 represents a preferred embodiment of a weight generator 31. However, different embodiments are likewise possible. For example, the weight generator 31 may comprise a memory element (not shown), where different weight factors W[n] are stored.

[0147] The weight generator 31 of FIG. 7 comprises a generator input 32 for receiving a digital starting factor 33. The starting factor 33 can be provided by an extern hardware or extern software or it can be hardcoded in an integration register within the weight generator. The starting factor is required for successive calculating of monotonically decreasing weight factors W[n] for each clock period n. For that, the weight generator 31 comprises a generator output 34 forwarding the weight factor W[n] to the second input 14 of the switching block 12.

[0148] The weight generator 31 of FIG. 7 comprises three integration stages 35a-c coupling the generator input to the generator output. Each integration stage 35 comprises a stage input 36, as denoted for the first integration stage 35a. The stage input 36 receives a digital input signal from the generator input 32 or from a preceding integration stage 35, respectively. Furthermore, each integration stage 35 comprises a stage output 37, as also denoted for the first integration stage 35a. The stage output 37 provides a digital output signal for a subsequent integration stage 35 or the generator output 34, respectively. This means that the digital output signal of the last integration stage 35c is the weight factor W[n]. Each integration stage 35 further comprises a stage combiner 38 configured to combine the digital input signal and a feedback from the digital output signal. A stage combiner 38 is denoted for the first integration stage 35a. In particular, the stage combiner 38 subtracts the digital input signal from the feedback from the digital output signal. Each integration stage 35 further comprises a register 39 configured to process the combination of the digital input signal and the feedback from the digital output signal. The register 39 provides the respective digital output signal of each integration stage 25. Each register receives a register factor 40a-c. The register factors 40a-c may be required for the first clock period n=1 within the conversion cycle of the iADC 1 in order to initialize the registers 39 with a start value. The register factors 40a-c can be derived by the starting factor 33 and the condition that the weight factor W[n] of the last clock period n=OSR within the conversion cycle of the iADC 1 has to be 1. For each new conversion cycle of the iADC 1, i.e. for each clock period n=1, the registers 39 of each integration stage 35 may be re-initialized. However, re-initialization may also take place at other time intervals. For example, re-initialization takes place every X-th conversion cycle. For example, the registers 39 can be re-initialized after each second or third conversion cycle. The exact time of re-initialization has no significant influence on the functionality of the iADC.

[0149] FIG. 8 shows a schematic diagram of an exemplary embodiment of an electronic device (50) comprising the iADC (1) and being connected to at least one sensor (51). The iADC (1) is configured to perform an analog-to-digital conversion of a signal provided by the at least one sensor (51).

[0150] The embodiments of the DAC disclosed herein have been discussed for the purpose of familiarizing the reader with novel aspects of the idea. Although preferred embodiments have been shown and described, many changes, modifications, equivalents and substitutions of the disclosed concepts may be made by one having skill in the art without unnecessarily departing from the scope of the claims.

[0151] It will be appreciated that the disclosure is not limited to the disclosed embodiments and to what has been particularly shown and described hereinabove. Rather, features recited in separate dependent claims or in the description may advantageously be combined. Furthermore, the scope of the disclosure includes those variations and modifications, which will be apparent to those skilled in the art and fall within the scope of the appended claims.

[0152] The term “comprising”, insofar it was used in the claims or in the description, does not exclude other elements or steps of a corresponding feature or procedure. In case that the terms “a” or “an” were used in conjunction with features, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope.