MULTIPATH D/A CONVERTER

Abstract

A multipath D/A converter is provided and has input terminals for a first and a second digital signal, and a signal combination unit D/A converting the digital signals supplied to the input terminals, and combining the generated analog signals. The signal combination unit includes a clock signal with a period having a first half period and a second half period. The signal combination unit combines the analog first and second signals by aggregating them with respective weighting coefficients. The signal combination unit has an output terminal for issuing an analog signal based on the aggregation. The signal combination unit applies a first set of weighting coefficients during the first half period of each period and a second set of weighting coefficients during said second half period of each period. The first set of weighting coefficients differs from the second set of weighting coefficients in at least one coefficient.

Claims

1. Multipath D/A converter, having: input terminals for a least a first and a second digital signal, and a signal combination unit arranged for D/A converting the first and second digital signal and then combining the resulting analog signals supplied to the input terminals, the signal combination unit being furthermore supplied with a clock signal from a clock unit of the multipath D/A converter, the clock signal a period having a first part period and a second part period, wherein the combination unit combines the supplied first and second analog signals by aggregating them with respective weighting coefficients, wherein the combination unit has an output terminal for issuing an analog signal based on the aggregation, wherein the combination unit is designed to apply a first set of weighting coefficients during said first part period of each period and a second set of weighting coefficients during said second part period of each period, wherein the first set of weighting coefficients differs from said second set of weighting coefficients in at least one coefficient.

2. The converter of claim 1, wherein the first set of weighting coefficients differs from said second set of weighting coefficients at least in one sign of a coefficient, or in one sign of one coefficient only.

3. The converter of claim 1, wherein in one of the first and the second part period of the clock signal the first and the second digital signals are added, wherein in the respectively other of first and second part period of the clock signal the first and the second digital signal are subtracted from each other.

4. The converter of claim 1, wherein the converter comprises a digital filter for at least one of the first and the second digital signal.

5. The converter of claim 4, wherein the converter comprises a first digital filter for first digital signal and a second digital filter for the second digital signal, wherein the first and the second digital filter have the same or different transfer functions.

6. The converter of claim 4, wherein filter coefficients of the digital filter are set are selected based on the weighting coefficients.

7. The converter of claim 1, comprising respectively a down-sampling unit for the first and the second digital signal, respectively.

8. The converter according to claim 7, wherein the sampling rate of the first and the second digital signal is higher, preferably twice the frequency of the clock signal.

9. The converter of claim 1, comprising a digital pre-emphasis unit for each of the first and second digital signal.

10. The converter according to claim 9, wherein the pre-emphasis unit is implemented by a digital filter.

11. The converter of claim 10, wherein the digital filter implementing a pre-emphasis unit is part of a down-sampling unit.

12. A multipath D/A converter, having: input terminals for a least a first and a second digital signal, and a signal combination unit D/A arranged for converting the at least first and second digital signal and then combining the resulting analog signals, the signal combination unit being furthermore supplied with a clock signal with a period having a first part period and a second part period, wherein the combination unit combines the supplied first and second analog signals by aggregating them with respective weighting coefficients, wherein the combination unit has an output terminal for issuing an analog signal based on the aggregation, wherein the combination unit is designed such that in one of the first and the second part period of the clock signal the first and the second signal are added, wherein in the respectively other of first and second part period of the clock signal the first and the second signal are subtracted from each other.

13. A method for combining at least two digital data streams, comprising the steps of: providing a least a first and a second digital signal, A/D converting the at least first and a second digital signal and combining the thus converted analog signals with a clock signal with a period having a first part period and a second half period, wherein the step of combining comprises the step of combining the first and second digital signals by aggregating them with respective weighting coefficients, wherein a first set of weighting coefficients is applied during said first part period of each period, and a second set of weighting coefficients is applied during said second part period of each period, wherein the first set of weighting coefficients differs from said second set of weighting coefficients in at least one coefficient.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Aspects of the invention will now be explained with reference to the figures of the enclosed drawings.

[0041] FIG. 1 shows schematically a signal-combination unit, such as for example a multipath D/A converter, and

[0042] FIG. 2 shows signal diagrams according to an example of an operation of the device of FIG. 1.

DETAILED DESCRIPTIONS OF EMBODIMENTS

[0043] In FIG. 1 a device 1 for combining a plurality of digital data signal paths 2, 3 is shown. The plurality of digital signal paths 2, 3 are fed to respective input terminals of a signal combination unit, which may be part of a D/A converter 6. Thus, in the combination unit 6, the digital signals are respectively D/A converted and then combined as analog signals. Further, a clock unit 7 is provided supplying a clock signal 8 to a clock signal input port 9 of the combination unit 6.

[0044] In the example of a D/A converter 6, an output port 10 is provided for issuing an analog signal 11, which may optionally be subjected to further processing stages, such as for example an analog filter 12. As shown in FIG. 1, a plurality or all of the multiple digital signal paths 2, 3 may be provided with digital filters 13, 14, such as e.g. low pass filters.

[0045] Preferably, in each of the multiple digital signal paths 2, 3 down-sampling (resampling) units 15, 16 may be provided. Preferably, these are arranged downwards of the filter units 13, 14.

[0046] In an example, the resampling units 15, 16 reduce the original sampling rates of the signals 2, 3 to half of the original value (down-sampling via factor 2).

[0047] The clock signal 8 issued by the clock unit 7 is a periodic high/low signal with a defined period. The clock signal thus has two half periods, one of which starts with one of a rising or falling edge of the logical high state, and the respective other half period starts with the respective other of rising and falling edge of this digital high/low clock signal 8.

[0048] The combination unit 6 combines the supplied and D/A converted signals X.sub.0 and X.sub.1 by aggregating, wherein this combination comprises the step of aggregating X.sub.0 and X.sub.1 by applying respective weighting coefficients.

[0049] Thus, an aggregated value y=A.sub.1X.sub.1+A.sub.2X.sub.2 is produced by the combination unit.

[0050] While in the first half period, this formula

y=A.sub.1X.sub.1+A.sub.2X.sub.2 [0051] is applied, [0052] in the respective other half period of the clock signal 6, the formula

y=A.sub.3X.sub.1+A.sub.4X.sub.2 [0053] is applied, under the condition, that:

A.sub.1A.sub.3 and/or

A.sub.2A.sub.4.

[0054] A.sub.1, A.sub.2, A.sub.3 and A.sub.4 are positive or negative non-zero values. The difference between A.sub.1 and A.sub.3 and/or A.sub.2 and A.sub.4 may be not the absolute value, but just the sign. However, at least one difference may also be the absolute value. Most preferred these weighting coefficients are set to be at least partly orthogonal.

[0055] The first half period and the second half period are examples for a first part period and a second part period, respectively, of a clock signal. The first part period and the second part period typically are delimited by one raising and one falling edge of the clock signal. Thus, a first part (half) period or second part (half) period does not extend beyond a raising or falling edge of the clock signal.

[0056] Such edge may trigger the switching between the different sets of weighting coefficients. The current value of x1 or x2, respectively may be held, e.g. in a register, until the next one of a falling or raising edge of the clock signal is detected.

[0057] Therefore, A.sub.1, A.sub.2 may be respectively +1.

[0058] A.sub.3 may be +1, while A.sub.4 may be chosen as 1. This is one example of an at least partially if not completely orthogonal set of weighting coefficients.

[0059] Another example of the coefficient set is [0060] 1 [0061] 0.5 [0062] 0.75 [0063] 0.175

[0064] This is an example where all coefficients have the same sign. The coefficients can be integer values, non-integer values or a mix thereof.

[0065] In other words, in one example in one of the half periods of the clock signal, the two signal values are added, while in the respective other half period the two signal values are subtracted from each other (in an analog manner).

[0066] Note that addition and subtraction does encompass the case where prior to the addition or subtraction the respective values of X.sub.1, X.sub.2 are waited by non-zero waiting coefficients which are not zero.

[0067] The digital filter units 13, 14 may implement pre-emphasis (pre-distortion) units.

[0068] The original digital signals 2, 3 may have a higher sampling rate then the rate of the clock signal 8 supplied by the clock unit 7. For example, the sampling rate of the original digital signals may be twice as high as the clock rate of the clock signal 8 supplied by the clock unit 7.

[0069] The original digital signals 2, 3 are preferably produced by splitting, via splitting dividing unit 20 a supplied single digital signal 21.

[0070] The digital filters 13, 14 are applying respective filter coefficients. These filter coefficients of the digital filter 13, 14 may be selected based on the weighting coefficients A.sub.1, A.sub.2, A.sub.3, A.sub.4 as applied by the combination unit 6.

[0071] The digital filter 13, 14, especially when implementing a respective pre-emphasis (pre-distortion) units may be part of the respective re-sampling unit 15, 16.

[0072] The filter coefficients may be set such that in each second sample the sign of the filter coefficient is inverted.

[0073] The pre-emphasis unit can be designed such that it applies a multiplication with a co-sign signal on to the supplied digital signals.

[0074] The above-explained combination unit thus preferably is an analog combination unit.

[0075] One single clock signal is applied to the analog combination unit, thus there is not a plurality of clock signals with e.g. phase shifts. The digital filter 13, 14 may be set such that one of the digital filters is a high-pass filter, while the respectively other is a low-pass filter. Alternatively, both digital filter 13, 14 may be low-pass filter.

[0076] Now turning to FIG. 2, a signal chart is shown indicating the digital high/low clock signal CLK, an example of a supplied first D/A converted signal X.sub.0, an example for a supplied second D/A converted signal X.sub.1 as well as the aggregated value y produced in the combination unit 6.

[0077] As can be seen, the waiting coefficients for the aggregation are set as follows:

A.sub.1,A.sub.3=+1

A.sub.2=+1

A.sub.4=1

[0078] This can be expressed, in this example, in that in a first half period of the clock signal, which is in this example the high-value time period of the clock signal, the two signals X.sub.0, X.sub.1 are added.

[0079] In this example, in the low period of the clock signal, the second signal X.sub.1 is subtracted from the first signal X.sub.0.

[0080] By applying different weighting coefficients in the combining (aggregation) step, the combination unit (and thus for example a D/A converter using such combination unit) effectively works as a combination unit (D/A converter) having twice the operation frequency of the supplied clock frequency.