INVERTER WITH LEG CURRENT DETECTION

Abstract

To allow reliable current measurement of the output current of the switching stage of an inverter, especially at switching frequencies of the semiconductor switches in the 100 kHz range, a voltage at the choke is measured and integrated over time to be representative for the leg current in the choke. The time integral is processed in a processing unit, whereas the processed time integral is used in an inverter controller for controlling the inverter. The voltage at the choke is analogously integrated over time by two serially connected integrator capacitors, whereas across each of the integrator capacitors a reset switch is provided, for alternately resetting the corresponding integrator capacitor.

Claims

1. An inverter having a switching stage with at least one switching leg, whereas the at least one switching leg comprises at least two serially connected semiconductor switches and an AC pole between the serially connected semiconductor switches, whereas the AC pole is serially connected to a choke, and whereas a current detection device is provided for detecting a leg current in the choke, wherein the current detection device comprises a voltage measurement unit that measures the voltage at the choke, and further comprises an integrator that integrates the measured voltage at the choke over time, whereas the time integral of the voltage at the choke represents the leg current in the choke, and further comprises a processing unit for processing the time integral provided by the integrator, whereas the processed time integral is used in an inverter controller for controlling the inverter, wherein two integrator capacitors in series are arranged in the integrator, whereas across each of the integrator capacitors a reset switch is provided, for alternately resetting the corresponding integrator capacitor.

2. The inverter according to claim 1, wherein the voltage measurement unit is analogously implemented as differential amplifier or instrumentation amplifier using at least one operational amplifier and resistors.

3. The inverter according to claim 1, wherein the integrator is analogously implemented as serial RC circuit using two integrator capacitors serially connected to an integrator resistor or as operational amplifier circuit using at least one operational amplifier with two serially connected integrator capacitors in a feedback branch connecting an output port of the operational amplifier to an input port of the operational amplifier.

4. The inverter according to claim 1, wherein the reset switches are implemented as switchover switch, preferably as Make-Before-Break switch.

5. The inverter according to claim 1, wherein alternately resetting the serially connected integrator capacitors is synchronized with zero crossings of the leg current.

6. The inverter according to claim 1, wherein the processing unit is analogously implemented as comparator circuit, whereas the comparator circuit provides an output signal when the leg current in the choke exceeds a given positive maximum current and/or when the leg current in the choke exceeds a given negative maximum current.

7. The inverter according to claim 1, wherein an analog-to-digital converter is provided for digitizing the time integral, whereas the digitized time integral is processed in the processing unit.

8. A method for operating an inverter having a switching stage with at least one switching leg, whereas the at least one switching leg comprises at least two serially connected semiconductor switches and an AC pole between the serially connected semiconductor switches, whereas the AC pole is serially connected to a choke, and whereas a leg current in the choke is detected, wherein a voltage at the choke is measured and integrated over time to be representative for the leg current in the choke, and wherein the time integral is processed in a processing unit, whereas the processed time integral is used in an inverter controller for controlling the inverter, wherein the voltage at the choke is analogously integrated over time by two serially connected integrator capacitors, whereas across each of the integrator capacitors a reset switch is provided, for alternately resetting the corresponding integrator capacitor.

9. The method according to claim 8, wherein the voltage at the choke is analogously integrated over time by a serial RC circuit having two integrator capacitors serially connected to an integrator resistor or by an operational amplifier circuit having at least one operational amplifier with two serially connected integrator capacitors in a feedback branch connecting an output port of the operational amplifier to an input port of the operational amplifier.

10. The method according to claim 8, wherein the two serially connected integrator capacitors are alternately reset at zero crossings of the leg current.

11. The method according to claim 8, wherein the time integral is compared to a given positive maximum leg current and/or to a given negative maximum leg current for overcurrent protection.

12. The method according to claim 8, wherein the time integral is digitized and digitally provided to the processing unit for processing.

Description

[0012] The present invention is described in greater detail below with reference to the FIGS. 1 through 11, which show exemplary, schematic and non-limiting advantageous embodiments of the invention. In the drawings

[0013] FIG. 1 shows a typical implementation of an inverter,

[0014] FIG. 2 a leg voltage and a leg current at an AC pole of a switching leg,

[0015] FIG. 3 an output current of the inverter as a result of the leg current,

[0016] FIG. 4 an inverter with an inventive current detection device,

[0017] FIG. 5 the time integral of the voltage at the choke,

[0018] FIG. 6 the voltage measurement unit implemented as differential amplifier,

[0019] FIG. 7 an analog implementation of the integrator using operational amplifier and one capacitor in the feedback branch with reset switch,

[0020] FIG. 8 an analog implementation of the integrator using operational amplifier and with two serially connected capacitors in the feedback branch with reset switch,

[0021] FIG. 9 an comparator circuit for detecting over currents,

[0022] FIG. 10 digitization of the time integral and

[0023] FIG. 11 digital integration of the measured voltage at the choke.

[0024] An inverter 1 is connected at the input to a DC source 2, e.g. a PV module (photovoltaic module) or a battery energy storage, and at the output to an electric load 8, e.g. an electric grid. The inverter 1 converts the DC input voltage U.sub.DC into an AC output voltage u.sub.AC and output current i.sub.AC. The inverter 1 may also be implemented bidirectional, e.g. for supplying electric energy from an electric grid to a battery energy storage (in this case input and output of the inverter 1 would be switched). The inverter 1 usually comprises a switching stage 5 that is connected to a DC link 4 at the input stage of the inverter 1. At the input side of the inverter 1 there may optionally be arranged a DC filter 3, e.g. an EMC (electromagnetic compatibility) filter. At the output side of the inverter 1 there may optionally be arranged an AC filter 6, e.g. for smoothing the output voltage u.sub.AC and output current i.sub.AC. The AC filter 6 may comprise a differential-mode filter (usually in form of capacitors connected between the phases) and/or an EMC filter (usually in form of capacitors connected between the phases and inductors in series to the phases). Between the inverter 1 and the load 8, there may optionally be arranged an AC relay 7 which allows for disconnecting the inverter 1 from the electric load 8. The AC relay 7, if present, may also be integrated in the inverter 1.

[0025] There are many different implementations of inverter 1 known. Inverter may differ in the number of phases they provide, e.g. a three-phase inverter for providing electric energy to a three-phase electric grid. Inverter 1 may also differ in the implementation of the switching stage 5.

[0026] A switching stage 5 comprises at least one switching leg SLn (n≥1), e.g. SL1, SL2 as in FIG. 1, connected in parallel to the DC link voltage U.sub.DL of the DC link 4. In a switching leg SLn at least two semiconductor switches Snm (m≥2) (at least one high-side and at least one low-side switch) are connected in series, e.g. switches S11, S12, S21, S22 as in FIG. 1. Between the high-side and low-side semiconductor switches Snm of a switching leg SLn an AC poles ACPn, e.g. ACP1, ACP2 as in FIG. 1, is formed at which the AC leg current i.sub.Ln and voltage u.sub.Ln, e.g. i.sub.L1 and u.sub.L1 as in FIG. 1, of the switching leg SLn are provided. With one high-side and one low-side semiconductor switch Snm the AC leg voltage u.sub.Ln can have two voltage levels. There are also known switching stages 5 with more than one high-side and low-side semiconductor switches Snm which allow for more than two voltage levels of the AC leg voltage u.sub.Ln at the AC pole ACPn (so called multi-level inverter).

[0027] The inverter 1 may also have multiple switching legs SLn for providing multiple phases of the AC output voltage u.sub.AC (multi-phase inverter), e.g. three for providing a three-phase output voltage u.sub.AC, or may also have several cascaded switching stages 5. The AC poles ACPn of several switching legs SLn of the switching stage 5 may also be connected to together form a phase of the output voltage u.sub.AC. In this case the leg voltages u.sub.Ln of the connected switching legs SLn may also be phase shifted (interleaved inverter).

[0028] The actual implementation of the switching stage 5 is however not relevant for the invention.

[0029] The AC leg currents i.sub.Ln and voltages u.sub.Ln provided at the AC poles ACPn of the switching legs SLn are usually filtered by serially connected chokes L (inductors) in order to remove high frequency components of the AC waveforms. There is usually at least one choke L per phase of the output voltage u.sub.AC.

[0030] The DC link 4 comprises at least one DC link capacitor C.sub.L that is connected in parallel to the input voltage U.sub.DC (optionally after filtering in the DC filter 3). The DC link voltage U.sub.DCL is provided at the Dc link 4. It is also known to use more link capacitors C.sub.L in series in the DC link 4. In such an implementation it would be possible to connect the pole between two capacitors C.sub.L in the DC link 4 with the neutral line at the output of the inverter 1 or with a star point of an AC output filter 6 (in case of e.g. three phases).

[0031] An inverter controller 10 is used for operating the inverter 1. Different measurement signals M, e.g. measured voltages and/or currents, of the inverter 1 may be used to that end, e.g. the DC link voltage U.sub.DCL, the DC input voltage U.sub.DC, the output voltage u.sub.AC, the output current i.sub.AC or leg currents i.sub.Ln. A leg current i.sub.Ln of a switching leg SLn may for example be used for overcurrent protection and regulation of the semiconductor switches Snm of this switching leg SLn. Voltage and current sensors used for measuring the required quantities are well known.

[0032] In the inverter controller 10 a switching controller 11 is implemented that generates the control signals CSnm, e.g. CS11, CS12, CS21, CS22 as in FIG. 1, for switching the semiconductor switches Snm in the switching stage 5 in order to generate the required output voltage u.sub.AC and/or output current i.sub.AC of the inverter 1. The control signals CSnm are usually provided to well-known gate driver (not shown for the sake of simplicity) for each semiconductor switch Snm that effectuate the switching of the semiconductor switches Snm. The gate drivers could also be integrated in the switching controller 11.

[0033] The inverter controller 10 can be implemented on a microprocessor-based hardware, like a computer, microcontroller, digital signal processor, programmable logic controller (PLC), etc, that is programmed with control software for operating the inverter 1. Also, implementations with application-specific integrated circuits (ASIC) or Field-programmable gate array (FPGA), or the like, are possible. The control software is stored in a memory of the inverter controller 10. The switching controller 11 and other functionalities of the inverter controller 10 can be implemented as software that is run on the inverter controller 10. The inverter controller 10 and the switching controller 11 could also be implemented as separate hardware. In this case the switching controller 11 could also be microprocessor-based hardware, like a microcontroller, a computer, digital signal processor, programmable logic controller (PLC) etc., or an application-specific integrated circuit (ASIC) or Field-programmable gate array (FPGA), or the like. The inverter controller 10 and/or the switching controller 11 could, however, also be implemented as analog circuits.

[0034] By way of example only, FIG. 1 shows a typical design of an inverter 1, in this case a single-phase inverter. In this example, the inverter 1 is supplied with DC power from a DC power source 2 and provides electric energy to an electric load 8 via an AC relay 7. At the input of the inverter 1 there is arranged a DC filter 3. The DC input voltage U.sub.DC after filtering in the DC filter 3 is supplied to a DC link 4 with at least one capacitor C.sub.L in parallel to the DC input voltage U.sub.DC provided by the DC power source 2. The DC link 4 is followed by a switching stage 5 having a number of semiconductor switches S11, S12, S21, S22. In the example of FIG. 1 the switching stage 5 has two switching legs SL1, SL2, whereas each switching leg SL1, SL2 is connected in parallel to the DC link 4, i.e. in parallel to the DC link voltage U.sub.DCL. In each switching leg SL1, SL2 a high-side semiconductor switch S11, S21 and a low-side semiconductor switch S12, S22 are connected in series. Between the semiconductor switches S11, S21 and S12, S22 of a switching leg SL1, SL2 AC poles ACP1, ACP2 are formed. At one AC pole ACP1 the AC leg current i.sub.L1 is provided. The other AC pole ACP2 serves as return path for the leg current. For a single-phase inverter 1, the second switching leg SL2 could of course also be omitted in well-known manner. With one semiconductor switch S11, S12 above and below the AC pole ACP, the AC waveforms at the AC pole ACP1 can have two voltage levels. A choke L is serially connected to the AC pole ACP1 of the switching leg SL1. There could also be provided an additional second choke L in the return path serially connected to the second AC pole ACP2 of the second switching leg SL2.

[0035] Because of the switching of the semiconductor switches Snm AC leg voltage u.sub.Ln with rising and falling edges, e.g. square wave or step wave (e.g. in the case of an multi-level inverter) waveforms, are generated at the AC poles ACPn of the switching legs SLn of the switching stage 5 as exemplarily shown in FIG. 2 above. Due to the choke L, also leg currents i.sub.Ln with rising and falling edges, e.g. like triangle waveforms, are generated as exemplarily shown in FIG. 2 below. The frequency of the AC leg voltages and currents of the switching legs SLn correspond to the switching frequency f.sub.S (=1/T.sub.S) of the semiconductor switches Snm. The semiconductor switches Snm are switched in such a way, for example by using PWM, that the desired output voltage u.sub.AC or current i.sub.AC, for example a 50 Hz sinus, are generated, as shown in FIG. 3. This means that the output current i.sub.AC of a phase the inverter 1, for example, is synthesized by a number of pulses of the corresponding leg current(s) i.sub.Ln of a switching leg SLn. In the example of FIGS. 2 and 3, a zero-voltage switching strategy is employed which causes zero crossings of the leg current i.sub.Ln in every switching period T.sub.S (as indicated in FIGS. 2 and 3).

[0036] The present invention aims at measuring a leg current i.sub.Ln of a switching leg SLn of a switching stage 5 of an inverter 1 that flows through a choke L connected in series to the AC pole ACPn of this switching leg SLn. The inventive current measurement allows for reliable and low-loss measurements even of high frequency currents (with frequencies in the range of 100 kHz). With the inventive current measurement also the peak measurements, for example for over current protection, are possible at such high frequencies.

[0037] With reference to FIG. 4, an inventive current detection device 9 for measuring AC leg current i.sub.Ln provided at an AC pole ACPn of a switching leg SLn of a switching stage 5 of an inverter 1 and flowing through a choke L is described. The switching leg SLn has at least two semiconductor switches Snm, i.e. at least one high-side and least one low side switch. Shown in FIG. 4 is only one switching leg SLn, whereas the current measurement could of course be applied to further switching legs SLn of an inverter 1. As already mentioned above, a DC filter 3 and an AC filter 6 (a possible implementation is exemplarily shown) are optional.

[0038] The current detection device 9 comprises of a voltage measurement unit 12, e.g. a voltage sensor, a differential amplifier and the like, that measures the leg voltage u.sub.Ln (as shown in FIG. 2) across the choke L of the switching leg SLn. The current detection device 9 further comprises an integrator 13 that forms the integral ∫u.sub.Ln over time t of the measured voltage u.sub.Ln at the choke L. The time integral ∫u.sub.Ln is supplied to a processing unit 14 for processing.

[0039] The time integral ∫u.sub.Ln of the pulse shaped leg voltage u.sub.Ln at the choke L is a triangle shaped signal (FIG. 5). Hence, the shape of the time integral ∫u.sub.Ln corresponds to the shape of the leg current i.sub.Ln (as shown in FIG. 2) that flows in the choke L. The time integral ∫u.sub.Ln is therefore representative for the leg current i.sub.Ln. This means that by integrating the voltage u.sub.Ln at the choke L over time t a measurement can be obtained that corresponds to the leg current i.sub.Ln in the choke L. The difference between the leg current i.sub.Ln and the time integral ∫u.sub.Ln is a proportionality factor P that depends on the implementation of the voltage measurement unit 12 and the integrator 13, i.e. i.sub.Ln=P.Math.∫u.sub.Ln, and can be regarded as being known. Therefore, the time integral ∫u.sub.Ln corresponds to the leg current i.sub.Ln. The time integral ∫u.sub.Ln can be evaluated and used in different ways in the processing unit 14 as will be described below. The processing unit 14 may apply the known proportionality factor P in order to obtain current measurements of the leg current i.sub.Ln from the time integral ∫u.sub.Ln.

[0040] The voltage measurement unit 12 may be implemented as well-known differential amplifier (as shown in FIG. 6) or instrumentation amplifier using operational amplifier OP with the voltage u.sub.Ln across the choke L as input, for example. The voltage measurement unit 12 is in this case an analog circuit. The output of the voltage measurement unit 12 is a voltage u.sub.V that is representative for the measured leg voltage u.sub.Ln at the choke L. For a differential amplifier, the output voltage u.sub.V is a known function f.sub.D of the resistors of the circuit and the input u.sub.Ln to the differential amplifier, i.e. u.sub.V=f.sub.D (H R1, R2, R3, R4). The same applies to an instrumentation amplifier. V.sub.Ref in FIG. 6 is a provided and known reference voltage. By using a differential or instrumentation amplifier, the high voltage u.sub.Ln at the choke L may be scaled down (dependent on the resistors used) to a lower voltage, for example to a voltage range between zero and five volts, that can be easier processed in the following stages. The output voltage u.sub.V auf the differential or instrumentation amplifier represents a measurement of the leg voltage u.sub.Ln.

[0041] The integrator 13 could also be implemented as analog circuit in well-known manner with an operational amplifier OP as shown in FIG. 7. Typically, the integrator 13 has a capacitor C.sub.I in the feedback branch connecting the output port of the operational amplifier OP to an input port of the operational amplifier OP. The output of the integrator 13 is a known function f.sub.I of the input voltage u.sub.V, the resistor R.sub.I, the capacitor C.sub.I in the feedback branch and the time Δt between two measurements, i.e. time integral ∫u.sub.Ln=f.sub.I(u.sub.V, R, C, Δt). To avoid a drift of the integrator 13 over time, and hence an increasing offset in the time integral ∫u.sub.Ln, the capacitor C.sub.I can be reset at given times. The reset could be done by means of a reset switch S.sub.I connecting the two poles of the capacitor C.sub.I (as indicated with dashed lines in FIG. 7). The reset times could be synchronized with zero crossings of the leg current i.sub.Ln flowing in choke L. For that a zero-crossing detector 9 (FIG. 6), e.g. implemented as comparator circuit, could be used for detecting zero crossings of the leg current i.sub.Ln.

[0042] As closing the switch S.sub.I for discharging the capacitor C.sub.I and opening the reset switch S.sub.I for recharging the capacitor C.sub.I takes some time, a certain offset error remains despite the reset, especially at higher frequencies. Hence, to improve the reset, two capacitors C.sub.I1, C.sub.I2 are used in accordance with the invention that are alternately reset, as shown in FIG. 8.

[0043] In the embodiment of FIG. 8 one capacitor C.sub.I1 is charged at positive voltages u.sub.V (rising edge of ∫u.sub.Ln) and the other capacitor C.sub.I2 is charged at negative voltages u.sub.V (falling edge of ∫u.sub.Ln). One of the capacitors C.sub.I1, C.sub.I2 is reset (short circuited by the corresponding switch S.sub.I1, S.sub.I2) and the other is charged. At every zero crossing of the leg current i.sub.Ln resetting and charging of the capacitors C.sub.I1, C.sub.I2 is switched over. By using two capacitors C.sub.I1, C.sub.I2 and two switches S.sub.I1, S.sub.I2 the offset introduced by the reset can be reduced.

[0044] The two switches S.sub.I1, S.sub.I2 could be implemented using a switchover switch, e.g. a single pole, double throw switch. In such a switch always one of the two output contacts is connected to the input contact and by switching the output contact that is connected to the input contact changes. In an advantageous embodiment a Make-Before-Break switch is used as switchover switch. In a Make-Before-Break switch the new connection is made before the previous connection is broken, so that the input contact is momentarily connected to both output contacts. By that it is avoided that one of the capacitors C.sub.I1, C.sub.I2 charges the other capacitor C.sub.I1, C.sub.I2 at switching which would occur when both switches S.sub.I1, S.sub.I2 were simultaneously open (which would be the case when using a Break-Before-Make switch).

[0045] The integrator 13 could, however, also be implemented as a well-known simple RC circuit with an integrator resistor R.sub.I connected in series to two serially connected integrator capacitors C.sub.I (as shown in FIG. 8) that are alternatively reset by two reset switches S.sub.I (as in FIG. 8). The voltage across the capacitor C.sub.I corresponds to the time integral ∫u.sub.Ln of the input voltage u.sub.V of the RC circuit. Also, in this case use of a Make-Before-Break switch would be advantageous.

[0046] In an alternative embodiment (not in accordance with the invention), the integrator 13 could be implemented digitally, as shown in FIG. 11. For that the input voltage u.sub.V measured with the voltage measurement unit 12 is provided to an analog-to-digital converter 16 (A/D converter) for digitizing the input voltage u.sub.V. The digitized input voltage u.sub.V is provided to the digital integrator 13, e.g. software that is run on a separate piece of hardware or on the hardware of the controller 10.

[0047] The time integral ∫u.sub.Ln which represents a measurement of the leg current i.sub.Ln can then be processed in the processing unit 14, in the embodiment shown in the controller 10.

[0048] The processing unit 14 may be used for overcurrent protection or for current measurement, for example.

[0049] For overcurrent detection the processing unit 14 could be implemented as comparator circuit 15 as analog circuit using operational amplifiers OP as exemplarily shown in FIG. 9. The comparator circuit 15 is designed to output an output signal, when the leg current i.sub.Ln exceeds a given maximum current ±i.sub.Lnmax, that can be a positive and/or negative current. In the embodiment shown, the time integral ∫u.sub.Ln signal obtained from the analog integrator 13 is supplied to a first input port, e.g. the positive input port, of a first operational amplifier OP1 of a first comparator of the comparator circuit 15. The second input port, e.g. the negative input port, of the first operational amplifier OP1 is supplied with the output voltage of a voltage divider using two resistors Ra1, Rb1 and a reference voltage V.sub.Ref. The values of the resistors Ra1, Rb1 are chosen such that the output voltage OV1 of the first operational amplifier OP1 is at a high level when the leg current i.sub.Lnn exceeds a given maximum current i.sub.Lmax. Usually the leg current i.sub.Ln can also become negative. Therefore, a second comparator using an operational amplifier OP2 and resistors Ra2, Rb2 may be provided in the comparator circuit 15 for detecting a negative maximum current −i.sub.Lnmax In this case the voltage divider formed by the resistors Ra2, Rb2, whose output is provided to a first input port, e.g. the negative input port, of the operational amplifiers OP2, is supplied with the time integral ∫u.sub.Ln signal. The second input port, e.g. the positive input port, of the operational amplifier OP2 is supplied with a reference voltage V.sub.Ref. The output voltage OV2 of the second operational amplifier OP2 of the comparator circuit 15 is preferably at a high level when the AC current i.sub.Ln exceeds a given negative maximum current −i.sub.Lnmax.

[0050] The output of the comparator circuit 15 may be provided to and processed in the inverter controller 10. The inverter controller 10 could trigger a certain action if an overcurrent situation is detected. The inverter controller 10 could switch the inverter 1 into a safety mode or reduce the output current i.sub.AC in case of an over current.

[0051] The signal of the time integral ∫u.sub.Ln obtained from the analog integrator 13 could also be digitised using an analog-to-digital converter 16 (A/D converter) and provided in digital form to the processing unit 14 (as in FIG. 10), e.g. the inverter controller 10, where the digital signal could be processed, e.g. for overcurrent protection of for controlling the switching stage 5 of the inverter 1. This could be used as continues current measurement of the leg current i.sub.Ln. The A/D converter 16 could of course also be integrated in the inverter controller 10, e.g. as software and/or as hardware.

[0052] There are numerous designs of A/D converters 16 known and the invention is not limited to a specific A/D converter. The conversion rate of the A/D converter 16 used should however be fast enough in order to be able to capture the measured voltage u.sub.V or the leg current i.sub.Ln in its given frequency band.