MICRO-LED AND METHOD OF MANUFACTURE

Abstract

A method of manufacturing a micro-LED comprises the steps of forming an n-doped connecting layer of III-nitride material over a porous region of III-nitride material, and forming an electrically-insulating mask layer on the n-doped connecting layer. The method comprises the steps of removing a portion of the mask to expose an exposed region of the n-doped connecting layer, and forming an LED structure on the exposed region of the n-doped connecting layer. A method of manufacturing an array of micro-LEDs comprises the step of removing a portion of the mask to expose an array of exposed regions of the n-doped connecting layer, and forming an LED structure on each exposed region of the n-doped connecting layer. A micro-LED and array of micro-LEDs are also provided.

Claims

1. A method of manufacturing a micro-LED, comprising the steps of: forming an n-doped connecting layer of III-nitride material over a porous region of III-nitride material; forming an electrically-insulating mask layer on the n-doped connecting layer; removing a portion of the mask to expose an exposed region of the n-doped connecting layer; and forming an LED structure on the exposed region of the n-doped connecting layer.

2. A method according to claim 1, in which the step of forming the LED structure comprises forming, on the exposed region of the n-doped connecting layer: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion.

3. A method according to claim 1, comprising the first step of electrochemically porosifying a region of III-nitride material, to form the porous region of III-nitride material.

4. A method according to claim 1, comprising the step of forming the porous region of III-nitride material by electrochemical porosification through a non-porous layer of III-nitride material, such that the non-porous layer of III-nitride material forms a non-porous intermediate layer between the porous region and the n-doped III-nitride connecting layer.

5. A method according to claim 4, in which the non-porous intermediate layer has a thickness of between 1 nm and 3000 nm, preferably between 5 nm and 2000 nm.

6. A method according to claim 1 any preceding claim, in which the n-doped connecting layer of III-nitride material is formed over a stack of multiple porous layers of III-nitride material.

7. A method according to claim 6, in which the stack of porous layers comprises a porous Distributed Bragg Reflector (DBR), such that the method comprises the step of forming an n-doped connecting layer of III-nitride material over a porous DBR of III-nitride material.

8. A method according to claim 6 in which the stack of porous layers is a stack of alternating porous and non-porous layers, preferably in which the stack comprises between 5 and 50 pairs of porous and non-porous layers.

9. A method according to claim 8 in which the porous layers have a thickness of between 10 nm and 200 nm, and the non-porous layers have a thickness of between 5 nm and 180 nm.

10. A method according to claim 1, in which the porous region or each porous layer has a porosity of between 10% and 90% porous.

11. A method according to claim 1, in which the n-doped connecting layer of III-nitride material has a thickness of between 200 nm and 2000 nm and a charge carrier concentration of >1×10.sup.18 cm.sup.−3.

12. A method according to claim 1, in which the mask layer is formed from one of: SiO.sub.2, SiN , SiON , AlO.sub.x.

13. A method according to claim 1, in which the mask layer has a thickness of between 5 nm and 1000 nm, preferably between 200 nm and 800 nm, particularly preferably between 400 nm and 600 nm.

14. A method according to claim 1, in which the mask layer is deposited by PECVD, sputtering, ALD, evaporation or in-situ MOCVD.

15. A method according to claim 1, any preceding claim, in which the step of removing a portion of the mask layer involves wet etching or dry etching, for example inductively coupled dry etching (ICP-RIE).

16. A method according to claim 1, in which the exposed regions of the connecting layer are circular, square, rectangular, hexagonal, or triangular in shape.

17. A method according to claim 1, in which the exposed regions have a width of between 0.05 μm and 100 μm, preferably between 0.05 μm and 30 μm, particularly preferably less than 10 μm, for example between 0.1 μm and 10 μm or between 0.5 μm and 10 μm.

18. A method according to claim 1, comprising the step of, after the n-doped portion, the light emitting region and the p-doped portion have been formed, removing a second portion of the mask to expose a second exposed region of the n-doped connecting layer; and forming an electrical contact in the second exposed region of the n-doped connecting layer.

19. A method of manufacturing an array of micro-LEDs, comprising the step of: forming an n-doped connecting layer of III-nitride material over a porous region of III-nitride material; forming an electrically-insulating mask layer on the n-doped III-nitride layer; removing a portion of the mask to expose an array of exposed regions of the n-doped connecting layer; and forming an LED structure on each exposed region of the n-doped connecting layer.

20. A micro-LED, comprising: an n-doped connecting layer of III-nitride material over a porous region of III-nitride material; an electrically-insulating mask layer on the n-doped III-nitride layer; and an LED structure, in which at least a portion of the LED structure extends through a gap in the electrically-insulating mask layer, and is in contact with the n-doped connecting layer.

21. A micro-LED according to claim 20, in which the LED structure comprises: an n-doped portion; a p-doped portion; and a light emitting region located between the n-doped portion and a p-doped portion.

22. A micro-LED according to claim 20, comprising a non-porous intermediate layer of III-nitride material positioned between the porous region and the connecting layer.

23. A micro-LED according to claim 21, in which the n-doped portion comprises an n-doped III-nitride layer, preferably in which the n-doped portion comprises n-GaN, or n-InGaN, or a stack of alternating layers of n-GaN/n-InGaN, or a stack of alternating layers of n-InGaN/n-InGaN containing different concentrations of indium.

24. A micro-LED according to claim 21, in which the light-emitting region comprises one or more III-nitride light-emitting layers, and in which the or each light-emitting layer comprises a quantum well, or a nanostructured layer comprising quantum structures such as quantum dots, fragmented or discontinuous quantum wells.

25. A micro-LED according to claim 24, in which the or each light-emitting layer comprises a III-nitride material with an atomic indium content of between 10-40%, or between 12-18%, preferably above 13%, or between 20-30%, preferably above 22%, or between 30-40%, preferably above 33%.

26. A micro-LED according to claim 24, in which the one or more light-emitting layers have the composition In.sub.xGa.sub.1-xN, in which 0.10≤x≤0.40, preferably 0.20≤x≤0.40 or 0.22≤x≤0.40, particularly preferably 0.30≤x≤0.40.

27. A micro-LED according to claim 21, in which the light-emitting region comprises one or more InGaN quantum wells, preferably between 1 and 7 quantum wells.

28. A micro-LED according to claim 21, in which the LED comprises a cap layer of III-nitride material between the quantum wells and the p-doped portion, preferably in which the cap layer is undoped and has a thickness of between 5 nm and 30 nm.

29. A micro-LED according to claim 21, in which the p-doped portion comprises a p-doped III-nitride layer and a p-doped aluminium gallium nitride layer positioned between the p-doped III-nitride layer and the light emitting region.

30. A micro-LED according to claim 29, in which the p-doped aluminium nitride layer is an electron-blocking-layer (EBL) between the cap layer and the p-type layer, in which the electron-blocking-layer contains 5-25 at % aluminium, preferably in which the electron-blocking-layer has a thickness of between 10 nm and 100 nm.

31. An array of micro-LEDs, comprising a plurality of micro-LEDs according to claim 21, formed on a substrate.

32. An array of micro-LEDs, comprising: an n-doped connecting layer of III-nitride material over a porous region of III-nitride material; an electrically-insulating mask layer on the n-doped III-nitride layer; a plurality of gaps in the electrically-insulating mask layer, and a plurality of LED structures, in which at least a portion of each LED structure extends through a gap in the electrically-insulating mask layer, and is in contact with the n-doped connecting layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0155] Specific embodiments of the invention will now be described with reference to the figures, in which:

[0156] FIG. 1 illustrates a porous template suitable for a micro-LED, or an array of micro-LEDs, according to the present invention;

[0157] FIGS. 2-18 illustrate the steps of manufacturing an array of two micro-LEDs according to a preferred embodiment of the present invention; and

[0158] FIGS. 19 to 25 illustrate a method of manufacturing a micro-LED according to a preferred embodiment of the present invention.

[0159] FIG. 1 illustrates a porous template suitable for a micro-LED according to the present invention.

[0160] The porous template comprises a porous region of III-nitride material on a substrate, with a non-porous layer of III-nitride material arranged over the top surface of the porous region. Optionally there may be further layers of III-nitride material between the substrate and the porous region.

[0161] As described in more detail above, the porous region may be provided by epitaxially growing an n-doped region of III-nitride material and then an undoped layer of III-nitride material, and porosifying the n-doped region using the porosification process as set out in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728).

[0162] The porous region may comprise one or more layers one or more III-nitride materials, and may have a range of thicknesses. In preferred embodiments, the porous region may for example comprise GaN and/or InGaN.

[0163] In a preferred embodiment, micro-LEDs according to the present invention comprise the following layers, and may be manufactured using the step by step process described below.

[0164] The following description of the LED structure of the micro-LED relates to a Top emission architecture being described from the bottom up, but the invention is equally applicable to a bottom emission architecture.

FIG. 2—Substrate & III-Nitride Layer for Porosification

[0165] A compatible substrate is used as a starting surface for epitaxy growth. The substrate may be Silicon, Sapphire, SiC, β-Ga2O3, GaN, glass or metal. The crystal orientation of the substrates can be polar, semi-polar or non-polar orientation. The substrate size may vary from 1 cm.sup.2, 2 inch, 4 inch, 6 inch, 8 inch, 12 inch, 16 inch diameters and beyond, and the substrate may have a thickness of greater than 1 μm, for example between 1 μm and 15000 μm. Preferably the substrate is a semiconductor wafer. An advantage of the present invention is that an array of micro-LEDs may be manufactured simultaneously on a fully sized semiconductor wafer. While the illustrated example shows two micro-LEDs being formed on a shared template, the same method may be used to manufacture arrays of many micro-LEDs simultaneously on the same wafer.

[0166] A layer or stack of layers of III-nitride material is epitaxially grown on the substrate. The III-nitride layer may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layer).

[0167] The thickness T of the III-nitride stack is preferably at least 10 nm, or at least 50 nm, or at least 100 nm, for example between 10-10000 nm, preferably 4000 nm.

[0168] The III-nitride layer comprises a doped region having an n-type doping concentration between 1×10.sup.17 cm.sup.−3-5×10.sup.20 cm.sup.−3. The III-nitride layer may also comprise an undoped layer (not shown) of III-nitride material over the doped region.

[0169] The doped region may terminate at the exposed upper surface of the III-nitride layer, in which case the surface of the layer will be porosified during electrochemical etching.

[0170] Preferably, the doped region of the III-nitride material is covered by an undoped intermediate (or “cap”) layer of III-nitride material, so that the doped region is sub-surface in the semiconductor structure. The sub-surface starting depth (d) of the doped region may be between 1-2000 nm for example.

[0171] In the example illustrated in FIGS. 2 to 19, the III-nitride layer that is porosified is formed by a stack of III-nitride layers of alternating highly-doped and undoped layers. Between 5 and 50 pairs of doped and undoped alternating layers preferably make up the stack, with the highly doped layers having a charge carrier concentration of around 1×10.sup.20 cm.sup.−3, and the undoped layers having a charge carrier concentration of around 1×10.sup.17 cm.sup.−3. The thickness of the highly doped layers is preferably between 10 nm and 200 nm and the thickness of the undoped layers is preferably between 5 and 180 nm.

FIG. 3—Porosification to Porous Layer

[0172] After it is deposited on the substrate, the III-nitride stack of layers is porosified with a wafer scale porosification process as set out in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728). During this process, the doped layers of the III-nitride stack become porous, while any undoped region of III-nitride material does not become porous. The degree is porosity of the porous layers is controlled by the electrochemical etching process and may preferably be between 10%-90%.

[0173] Following the porosification step, the structure therefore contains a non-porous intermediate layer overlying a stack of alternating porous and non-porous layers. The stack of alternating porous and non-porous layers forms a DBR, as discussed above. As the uppermost layer of the stack is non-porous, this layer is not porosified, and remains on top of the stack as a non-porous intermediate layer.

FIG. 4—Connecting Layer

[0174] As shown in FIG. 3, after porosification, the wafer is overgrown with a connecting layer 1. The connecting layer is a n-doped III-nitride (preferably GaN) layer with a thickness of between 200 and 2000 nm (layer 1 in FIG. 3), and an n-type charge carrier concentration of at least >1×10.sup.18 cm.sup.−3.

[0175] The connecting layer 1 is formed of III-nitride material and may contain one or a combination of these elements: Al, Ga, In (binary, ternary or quaternary layer). The connecting layer is doped with suitable n-type dopant materials , e.g Si, Ge, C, O.

FIG. 5—Mask Layer

[0176] An electrically-insulating mask layer 2 is then deposited on the wafer surface, to cover the connecting layer 1. The purpose of the mask layer 2 is to protect certain regions of the wafer in the next steps as a mask and to enable selective area epitaxy on top of this template.

[0177] This mask layer 2 can be SiO.sub.2, SiN , SiON , AlO.sub.x or any other suitable layer. The thickness of this layer can be between 5-1000 nm, preferably around 500 nm.

[0178] The method used for deposition of this layer can be PECVD, sputtering, ALD, evaporation or an in-situ MOCVD approach.

FIG. 6—Exposing Regions of the Connecting Layer

[0179] Standard lithographic techniques are used to create openings in the non-conducting mask layer 2. The openings can be created either with a wet etching or a dry etching method.

[0180] In a particularly preferred example inductively coupled dry etching (ICP-RIE) is used to remove SiO.sub.2 from two areas, which creates two exposed regions on the surface of the connecting layer 1 that are no longer covered by the mask layer 2.

[0181] The shape of the exposed regions can be circular, square, rectangular, hexagonal, triangular etc. The width or diameter of the openings are preferably less than 100 μm so that the LED structures formed on the exposed areas are classed as micro-LEDs. The exposed regions may preferably have a width of 0.05 μm-30 μm, particularly preferably of 10 μm or less.

[0182] These exposed regions will eventually become pLED pixels

FIGS. 7 & 8—N-doped Region

[0183] After the exposed regions of the connecting layer 1 are formed, an n-doped layer 3 of III-nitride material is deposited in the exposed regions.

[0184] In the particular example shown, a 400 nm thick n-doped GaN layer (layer 3) is grown by

[0185] MOCVD. The growth takes place only inside the exposed regions, on the surface of the n-doped connecting layer 1. Si is used as a dopant in the n-doped layer 3, with a doping concentration of at least >1×10.sup.19 cm.sup.−3.

[0186] After the growth of n-doped layer 3, a bulk III-nitride layer 4 containing Indium or a stack of thin III-nitride layers with or without indium, or a variation in atomic percentage of indium is across the bulk layer or the stack is grown. The Indium atomic percentage may vary between 0.5-25%. The total thickness may vary between 2 nm-200 nm. If the stack is used then the thickness of individual layer in the stack may vary between 1-40 nm. The layer 4 may have n-doping concentration between 1×10.sup.17 cm.sup.−3-5×10.sup.20 cm.sup.−3.

FIG. 9—Light Emitting Region

[0187] After growth of n-type layer 4, a light-emitting region 5 is grown.

[0188] The light-emitting region 5 may contain at least one light emitting layer. Each light emitting layer may be a quantum well (QVV), preferably an InGaN quantum well (QVV). Preferably the light emitting region may comprise between 1-7 quantum wells. Adjacent quantum wells are separated by barrier layers of III-nitride material having a different composition to the quantum wells.

[0189] The light emitting layer(s) may be referred to as “quantum wells” throughout the present document, but may take a variety of forms. For example, the light emitting layers may be continuous layers of InGaN, or the layers may be continuous, fragmented, broken layers, contain gaps, or nanostructured so that the quantum well effectively contains a plurality of 3D nanostructures behaving as quantum dots.

[0190] The quantum wells and barriers are grown in a temperature range of 600-800 ° C.

[0191] Each quantum well preferably consists of an InGaN layer with atomic indium percentage between 10-40%. In specific examples the atomic indium content is between 12-18%, preferably above 13%, or between 20-30%, preferably above 22%, or between 30-40%, preferably above 33%.

[0192] The thickness of each quantum well layer may be between 1.5-8 nm, preferably between 1.5 nm and 6 nm, or between 1.5 nm and 4 nm.

[0193] The quantum wells may or may not be capped with a thin (0.5-3 nm) III-nitride QW capping layer, which may contain one or a combination of these elements: Al, Ga, In (ternary of quaternary layer).

[0194] The QW capping layer, which (if present) is the layer added immediately after QW growth, can be AlN, AlGaN of any Al % 0.01-99.9%, GaN, InGaN of any In % 0.01-30%.

[0195] The III-nitride QW barriers separating the light emitting layers (quantum wells) may contain one or a combination of these elements: Al, Ga, In (ternary of quaternary layer).

[0196] The QW capping layer(s) and QW barriers are not indicated with individual reference numerals in the Figures, as these layers form part of the light emitting region 5.

FIG. 10—Capped Layer and EBL

[0197] After growth of quantum wells a non-doped cap layer 6 is grown. Non-doped cap layer 4 may be termed a light-emitting-region cap layer, as this layer is formed after growth of the complete light emitting region, for example after the growth of the stack of QWs, QW capping layers and QW barrier layers.

[0198] The cap layer (light-emitting-region cap layer) 6 is a standard layer which is very well known in the growth schemes for III-nitride LEDs.

[0199] The thickness of cap layer can be between 5-30 nm, preferably between 5-25 nm or 5-20 nm.

Electron Blocking Layer (EBL)

[0200] After the cap layer 6, an electron blocking III-nitride layer 7 (EBL) containing Aluminium is grown. The thickness is of EBL can be between 10-100 nm. The Al % can be between 5-25% for example, though higher Al content is possible.

[0201] The EBL is doped with a suitable p-type doping material. The doping concentration can be between 5×10.sup.18 cm.sup.−3-8×10.sup.20 cm.sup.−3.

FIG. 11—P-doped Layer

[0202] A p-doped layer 8 is grown above the electron blocking layer (EBL) 7.

[0203] The p-type region is preferably doped with Mg, and the p-type doping concentration of the p-type layer is preferably between 5×10.sup.18 cm.sup.−3-8×10.sup.20 cm.sup.−3.

[0204] The p-doped III-nitride layer may contain In and Ga.

[0205] The doping layer is preferably between 20-200 nm thick, particularly preferably between 50-100 nm thick. The doping concentration may vary across the p-type layer and can have a spike in doping levels in the last 10-30 nm of the layer towards the LED surface, in order to allow better p-contact.

[0206] For activation of Mg acceptors in the p-doped layer, the structure may be annealed inside of MOCVD reactor or in an annealing oven. The annealing temperature may be in the range of 700-850 C in N2 or in N2/O2 ambient.

[0207] As both the EBL and the p-doped layer are p-type doped, these layers may be referred to as the p-doped region.

FIG. 12—Passivation Layer

[0208] The next step is to deposit a passivation layer 9 or a combination of passivation layers. The starting passivation layer can be Al.sub.2O.sub.3 (10-100 nm) (deposited by atomic layer depositions) followed by sputtered or plasma enhanced chemical vapor deposited SiO.sub.2, SiN or SiON (50-300 nm).

[0209] The Al.sub.2O.sub.3 can be deposited between 50-150 C. The SiO.sub.2, SiN and SiON can be deposited between 250-350 C. The sputter process can done at room temperature.

[0210] In a particularly preferred example the passivation layer 9 is made up of a 30 nm thick Al.sub.2O.sub.3 layer and 200 nm thick SiO.sub.2 layer.

FIGS. 13—Openings in Passivation Layer

[0211] The next step is to create openings in the dielectric layers to expose the p- and n-GaN. This can be done via wet etching, dry etching, or a combination of both. For wet etching buffered oxide etch, diluted hydrofluoric acid phosphoric acid or a mixture of these can be used.

[0212] In the topology illustrated in the Figures, two separate lithography steps are used to form ohmic contact on p and n doped layers.

[0213] FIG. 13 shows openings created through the passivation layer 9 to expose a region of the p-type layer 8.

FIG. 14—Transparent Conducting Layer

[0214] The exposed region of the p-type layer 8 is then covered with a transparent conducting layer 10. The transparent conducting layer can be made of Ni/Au, indium tin oxide, indium zinc oxide, graphene, Pd, Rh, silver, ZnO etc., or a combination of these materials.

[0215] The thickness of the transparent conducting layer can typically be between 10-250 nm.

[0216] Transparent conducting layers are well known in the art, and any suitable material and thickness may be used.

[0217] An annealing step may be required for making the p-contact ohmic.

FIG. 15—Second Exposed Region

[0218] The next step is to create openings to expose second exposed regions of the n-doped connecting layer 1, so that electrical connections can be made to the connecting layer 1. This is done by removing a portion of the passivation layer 9 and the mask layer 2. This can be done via wet etching, dry etching, or a combination of both.

FIG. 16—N-Contact

[0219] A metal n-contact 11 is deposited on the second exposed regions of the n-doped connecting layer 1. This metal contact can be combination of titanium, platinum and gold.

FIG. 17—P-Contact

[0220] In the final step only a portion of ITO is covered with a metal p-contact 12. This is used in a topology where light is extracted out from p-side, as shown in FIG. 17.

[0221] This metal contact can be combination of Nickel, titanium, platinum and gold.

Micro-LED—Specific Example

[0222] A particular preferred example of a micro-LED according to the present invention can be manufactured according to the steps set out above. The details of the layers in the exemplary micro-LED structure are as follows:

[0223] Substrate: 4 inch diameter planar sapphire substrate, under 1 μm thick undoped GaN buffer layer;

[0224] Porous Stack: 15 pair stack of alternating layers of undoped GaN layers (thickness 45 nm) and Si doped n+GaN layers (thickness 62.5 nm) with a charge carrier concentration of >1×10.sup.19 cm.sup.−3, electrochemically porosified so that the n-doped layers are porous and the undoped layers (including the top-most layer in the stack) are non-porous;

[0225] Connecting Layer 1 (the layer overgrown on top of the non-porous/porous template): n-doped GaN layer, thickness of 500 nm, Si doped with a charge carrier concentration of >5×10.sup.18 cm.sup.−3;

[0226] Mask Layer 2: 500 nm thick SiO.sub.2 layer deposited vie PECVD;

[0227] Exposed Regions: inductively coupled dry etching (ICP-RIE) was used to remove SiO.sub.2 from designated areas to expose circular exposed regions with a diameter of 10 μm;

[0228] N-doped Layer 3: 400 nm thick n-doped GaN (Si dopant) layer, grown in MOCVD, doping concentration of at least >1×10.sup.19 cm.sup.−3;

[0229] N-type Layer 4: stack of layers with atomic indium content of less than 5%, total stack thickness of 120 nm and doping concertation of mid 1×10.sup.18 cm.sup.−3;

[0230] Light-Emitting Region 5: 5 InGaN QWs (indium content of 17.5 at. %) with PL emission wavelength between 440-465 nm; GaN as a barrier layer, no capping layer;

[0231] Capping layer 6: 20 nm thick GaN;

[0232] EBL 7: AIGaN containing 15% Al, with a thickness of 60 nm;

[0233] P-doped Layer 8: p-GaN layer, thickness of 50 nm, Mg doped with p-type charge carrier concentration of >1×10.sup.19cm.sup.−3, followed by a layer of p++GaN, thickness of 6 nm, Mg doped with p-type charge carrier concentration of >1×10.sup.20 cm.sup.−3;

[0234] Passivation Layer 9: 30 nm thick Al.sub.2O.sub.3 and 200 nm thick SiO.sub.2 layers;

[0235] Transparent conducting layer 10: ITO, thickness of 150 nm;

[0236] Metal contact 11 to n-doped layer: 50 nm Ti, 100 nm Pt and 500 nm Au;

[0237] Metal contact 12 to p-type layer: 2 nm Ni, 50 nm Ti, 100 nm Pt and 500 nm Au.

[0238] The illustrated micro-LED in FIGS. 2-17 is designed to have an emission wavelength between 440-465 nm, and to emit light from the p-side of the device (the top of the micro-LED as shown). The stack of porous/non-porous layers forms a DBR that exhibits >90% reflectivity/transmission at −450 nm, so the DBR acts as a reflective mirror under the micro-LED that enhances the brightness of the emitted light. Both the emission wavelength of the light-emitting region, and the wavelength reflected by DBR, may be tuned as desired to obtain LEDs of other colours.

FIG. 19—Bottom-Side Topology

[0239] FIG. 19 illustrates an alternative micro-LED topology in which the light is being extracted out of the bottom side (substrate side).

[0240] The stack of porous/non porous layers can be used to form a DBR for which the reflectivity is >90% in a wavelength range of, for example, 440-465 nm.

[0241] In an exemplary embodiment, the QWs are chosen to have an emission wavelength of between 520-540 nm. The manufacture steps described above in relation to FIGS. 2 to 17 also apply to this embodiment, except that the n-type underlayer 3 and the light-emitting region 5 is appropriately adjusted for the desired output wavelength.

[0242] This bottom-side emission topology will offer following benefits: [0243] Pure green light is transmitted through the DBR and out of the device, as any other wavelength below 520 nm is blocked and reflected due to the DBR design; [0244] No damage to sidewalls of pixel during manufacture, hence no performance degradation for micro pixels.

Preferred Embodiment

[0245] FIGS. 19 to 25 illustrate a method of manufacturing a micro-LED according to a preferred embodiment of the present invention.

[0246] FIG. 19—A DBR is formed on a substrate using the porosification technique set out in Cambridge Enterprise's pending patent application no PCT/GB2017/052895. A layer of n-GaN is deposited on top of the porosified DBR.

[0247] FIG. 20—A layer of SiO2 (or another dielectric material) is deposited on the top surface of the n-GaN.

[0248] FIG. 21—The SiO2 is patterned by lithography, and a section of the SiO2 with lateral dimensions of 50 μm×50 μm is removed by wet chemical or dry etching process.

[0249] FIG. 22—A Quantum Well made from one of InGaN, AIGaN, InN, InAlN, AlInGaN, and surrounded by quantum barriers of GaN, AlN, AlGaN, AlInGaN, InAlN, is deposited on the exposed section of n-GaN. A layer of p-GaN is deposited on top of the QW.

[0250] FIG. 23—A second layer of SiO2 is deposited on top of the first layer of SiO2, so that SiO2 covers the edges of the QW and p-GaN layers. An electrical p-contact is formed over the p-GaN so that it is in electrical contact with the layer of p-GaN. This second SiO2 layer is the passivation layer.

[0251] FIG. 24—A section of SiO2 is removed by wet chemical or dry etching processes to expose a section of the n-GaN layer, and an electrical n-contact is deposited in the exposed section so that it is in electrical contact with the n-GaN.

[0252] FIG. 25—The second layer of SiO2 is passivated with known techniques. A plasma etch is used for chip singulation and transfer.