Time-Interleaved ADC

Abstract

A time interleaved ADC includes sub-ADCs that sample an analog input signal at a timing synchronized with a clock signal to convert the analog input signal into a digital output signal, delay circuits that apply a time difference to the analog input signal such that the analog input signal is input to each of the sub-ADCs with a delay of a first delay time in an arrangement order of the sub-ADCs, and delay circuits that apply a time difference to the clock signal such that the clock signal is input to each of the sub-ADCs with a delay of a second delay time in the arrangement order of the sub-ADCs.

Claims

1-5. (canceled)

6. A time interleaved ADC comprising: a plurality of analog to digital converters (ADCs) configured to sample an analog input signal at a timing synchronized with a clock signal and convert the analog input signal into a digital output signal; a plurality of first delay circuits configured to apply a time difference to the analog input signal such that the analog input signal is input to each of the plurality of ADCs according to a first delay time in an arrangement order of the plurality of ADCs; and a plurality of second delay circuits configured to apply a time difference to the clock signal such that the clock signal is input to each of the plurality of ADCs according to a second delay time in the arrangement order of the plurality of ADCs.

7. The time interleaved ADC according to claim 6, wherein the plurality of first delay circuits is capable of adjusting a delay time based on a delay control signal input from outside the time interleaved ADC.

8. The time interleaved ADC according to claim 6, wherein the plurality of second delay circuits is capable of adjusting a delay time based on a delay control signal input from outside the time interleaved ADC.

9. The time interleaved ADC according to claim 6, wherein the plurality of first delay circuits is capable of adjusting a gain based a gain control signal input from outside the time interleaved ADC.

10. The time interleaved ADC according claim 6, further comprising: a plurality of third delay circuits provided at respective outputs of the plurality of ADCs and configured to correct a time difference between output signals of the plurality of ADCs.

11. A time interleaved ADC comprising: a plurality of analog to digital converters (ADCs) configured to sample an analog input signal at a timing synchronized with a clock signal and convert the analog input signal into a digital output signal; a plurality of first delay circuits configured to apply a time difference to the analog input signal such that the analog input signal is input to each of the plurality of ADCs with a delay of a first delay time in an arrangement order of the plurality of ADCs; and a plurality of second delay circuits configured to apply a time difference to the clock signal such that the clock signal is input to each of the plurality of ADCs with a delay of a second delay time in an input order reverse to that of the analog input signal.

12. The time interleaved ADC according to claim 11, wherein the plurality of first delay circuits is capable of adjusting a delay time based on a delay control signal input from outside the time interleaved ADC.

13. The time interleaved ADC according to claim 11, wherein the plurality of second delay circuits is capable of adjusting a delay time based on a delay control signal input from outside the time interleaved ADC.

14. The time interleaved ADC according to claim 11, wherein the plurality of first delay circuits is capable of adjusting a gain based a gain control signal input from outside the time interleaved ADC.

15. The time interleaved ADC according claim 11, further comprising: a plurality of third delay circuits provided at respective outputs of the plurality of ADCs and configured to correct a time difference between output signals of the plurality of ADCs.

16. A method of operating a time interleaved ADC, the method comprising: sampling, by a plurality of analog to digital converters (ADCs), an analog input signal at a timing synchronized with a clock signal; converting, by the plurality of ADCs, the analog input signal into a digital output signal; applying, by a plurality of first delay circuits, a time difference to the analog input signal such that the analog input signal is input to each of the plurality of ADCs according to a first delay time in an arrangement order of the plurality of ADCs; and applying, by a plurality of second delay circuits, a time difference to the clock signal such that the clock signal is input to each of the plurality of ADCs according to a second delay time in the arrangement order of the plurality of ADCs or according to a third delay time in an arrangement order that is reverse of the arrangement order of the plurality of ADCs.

17. The method according to claim 16, further comprising adjusting, by the plurality of first delay circuits, the first delay time based on a delay control signal input from outside the time interleaved ADC.

18. The method according to claim 16, further comprising adjusting, by the plurality of second delay circuits, the second delay time based on a delay control signal input from outside the time interleaved ADC.

19. The method according to claim 16, further comprising adjusting, by the plurality of first delay circuits, a gain based a gain control signal input from outside the time interleaved ADC.

20. The method according to claim 16, further comprising: correcting, by a plurality of third delay circuits provided at respective outputs of the plurality of ADCs, a time difference between output signals of the plurality of ADCs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 is a block diagram illustrating a configuration of a time interleaved ADC according to a first embodiment of the present invention.

[0023] FIG. 2 is a block diagram illustrating another configuration of the time interleaved ADC according to the first embodiment of the present invention.

[0024] FIG. 3 is a block diagram illustrating a configuration of a time interleaved ADC according to a second embodiment of the present invention.

[0025] FIG. 4 is a block diagram illustrating a configuration of a time interleaved ADC according to a third embodiment of the present invention.

[0026] FIG. 5 is a block diagram illustrating another configuration of the time interleaved ADC according to the third embodiment of the present invention.

[0027] FIG. 6 is a block diagram illustrating a configuration of a time interleaved ADC according to a fourth embodiment of the present invention.

[0028] FIG. 7 is a block diagram illustrating another configuration of the time interleaved ADC according to the fourth embodiment of the present invention.

[0029] FIG. 8 is a block diagram illustrating a configuration of a time interleaved ADC according to a fifth embodiment of the present invention.

[0030] FIG. 9 is a diagram for describing the operation of the ADC.

[0031] FIG. 10 is a block diagram illustrating a configuration of a time interleaved ADC.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

First Embodiment

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a time interleaved ADC according to a first embodiment of the present invention. The time interleaved ADC of the present embodiment includes N (where N is an integer of 2 or more) sub-ADCs 1-1 to 1-N that sample an analog input signal at a timing synchronized with a clock signal to convert the analog input signal into digital output signals out-1 to out-N, delay circuits 2-1 to 2-(N1) that apply a time difference to the analog input signal such that the analog input signal is input to the individual sub-ADCs 1-1 to 1-N with a delay of a first delay time in in the arrangement order of the sub-ADCs 1-1 to 1-N, and delay circuits 3-1 to 3-(N1) that apply a time difference to the clock signal such that the clock signal is input to the individual sub-ADCs 1-1 to 1-N with a delay of a second delay time ck in the arrangement order of the sub-ADCs 1-1 to 1-N.

[0033] The analog input signal in is input from an input signal source (not illustrated) to the time interleaved ADC. The clock signal ck is input from a clock generation circuit (not illustrated) to the time interleaved ADC.

[0034] A difference from the ADC illustrated in FIG. 10 is that the delay circuits 2-1 to 2-(N1) are provided between the sub-ADCs not only for the clock signal but also for the analog input signal. A delay time of the delay circuit 2-i between the sub-ADC 1-i (where i is an integer of 1 to (N1)) and the sub-ADC 1-(i+1) is in(i), and a delay time of the delay circuit 3-i is ck(i). The delay times in(i) of the respective delay circuits 2-i may have different values or the same value. Similarly, the delay times ck(i) of the respective delay circuits 3-i may have different values or the same value.

[0035] All the delay circuits 2-i and 3-i are designed such that the delay times in(i) and ck(i) satisfy the following formula.

|in(i)ck(i)|=1/NTck(4)

[0036] As described above, N is the number of interleaves, and Tck is the clock cycle. In particular, in the most typical form, the ADC is designed to satisfy the following formula:

ck(i)in(i)=1/NTck(5)

[0037] In the present embodiment, since a relative difference between the delay times of the analog input signal and the clock signal is 1/NTck in each of the sub-ADCs 1-2 to 1-N, it is possible to obtain a sampling rate that is N times the clock frequency, similarly to the conventional time interleaved ADC.

[0038] As will be obvious, if in(i)=0 is set for all i, a configuration equivalent to that of the conventional time interleaved ADC illustrated in FIG. 10 is obtained, and Formula (4) coincides with Formula (2).

[0039] A feature of the present embodiment is that an input signal source only needs to drive the sub-ADC 1-1 and the delay circuit 2-1 at the first stage regardless of the number of interleaves N. That is, a load on the input signal source does not increase even if the number of interleaves N increases unlike the conventional time interleaved ADC. In addition, each delay circuit 2-i only needs to drive the sub-ADC 1-(i+1) and the delay circuit 2-(i+1) at the next stage. Therefore, the time interleaved ADC of the present embodiment can maintain favorable input characteristics even when the number of interleaves N increases.

[0040] In order to maintain more favorable input characteristics, an input buffer may be provided between the input signal source that outputs the analog input signal in and the analog input signal terminal of the sub-ADC 1-1 at the first stage. A configuration in this case is illustrated in FIG. 2. In the case of the configuration in FIG. 2, the input signal source only needs to drive an input buffer 4.

Second Embodiment

[0041] The first embodiment has the following problem. In the case of designing a time interleaved ADC that achieves a desired sampling rate, values of the number of interleaves N and the clock cycle Tck are determined by the determined specification, and thus the delay times in(i) and ck(i) of the delay circuits 2-i and 3-i may be determined such that Formula (5) is established.

[0042] A problem of the first embodiment is that the delay time ck(i) of the delay circuit 3-i is longer than the delay time 1/NTck of the conventional delay circuit 201-i by in(i).

[0043] In general, characteristics such as a delay time of a circuit vary depending on accuracy of a circuit manufacturing technique, fluctuation in a temperature during operation, fluctuation in a power supply voltage, and the like. For example, even if the variation is 1% or 3%, an absolute value of the variation increases as the delay time ck(i) increases.

[0044] When the variation in the delay time of the delay circuit 3-i increases, a sampling timing error of each sub-ADC is caused. That is, an input signal is sampled at a timing shifted from a time point at which the analog input signal should originally be sampled, and an error is superimposed on an output waveform due to the deviation in timing. The larger the timing error, the larger the error of the output waveform, and the performance of the ADC deteriorates.

[0045] The second embodiment of the present invention is directed to solving the problem of the first embodiment. FIG. 3 is a block diagram illustrating a configuration of a time interleaved ADC according to the present embodiment. The time interleaved ADC of the present embodiment includes sub-ADCs 1-1 to 1-N, delay circuits 2-1 to 2-(N1), and delay circuits 5-(N1) to 5-1 that apply a time difference to a clock signal such that the clock signal is input to the individual sub-ADCs 1 to 1-1 with a second delay time ck in an input order reverse to the analog input signal.

[0046] Similarly to the first embodiment, the analog input signal is input to the sub-ADCs 1-1, 1-2, . . . , and 1-N in this order. On the other hand, the clock signal is input to the sub-ADCs 1-N, . . . , 1-2, and 1-1 in this order. That is, the second embodiment is different from the first embodiment in that the order of input to the individual sub-ADCs is reversed between the analog input signal and the clock signal.

[0047] Similarly to the first embodiment, a delay time of the delay circuit 2-i between the sub-ADC 1-i (where i is an integer from 1 to (N1)) and the sub-ADC 1-(i+1) is in(i). In addition, a delay time of the delay circuit 5-(i) between the sub-ADC 1-i and the sub-ADC 1-(i+1) is ck(i). The delay times ck(i) of the delay circuits 5-i may have different values or the same value.

[0048] All the delay circuits 2-i and 5-i are designed such that the delay times in(i) and ck(i) satisfy the following formula.

in(i)+ck(i)=1/NTck(6)

[0049] By designing the delay circuits 2-i and 5-i s to satisfy Formula (6), it is possible to obtain a sampling rate that is N times the clock frequency, similarly to the conventional time interleaved ADC and the first embodiment.

[0050] As can be seen from Formula (6), a feature of the present embodiment is that the delay time ck(i) of the delay circuit 5-i can be set to a value shorter than the delay time 1/NTck of the conventional delay circuit 201-i. Therefore, in the present embodiment, an error in the delay time of the delay circuit 5-i can be reduced compared with the conventional time interleaved ADC or the first embodiment. As a result, it is possible to design an ADC with high accuracy.

[0051] In the same manner as in the first embodiment, an input buffer may be provided between the input signal source and the analog input signal terminal of the sub-ADC 1-1 at the first stage.

Third Embodiment

[0052] Regarding the variation in the delay time described in the second embodiment, in both the first and second embodiments, it is conceivable to make the delay time of the delay circuit for either the analog input signal or the clock signal or the delay circuit for both the analog input signal and the clock signal variable according to a control signal input from the outside. By making the delay time variable, variations in the delay time can be calibrated in a use state after manufacturing the circuit.

[0053] FIG. 4 is a block diagram illustrating a configuration of a time interleaved ADC according to a third embodiment of the present invention. The time interleaved ADC of the present embodiment includes sub-ADCs 1-1 to 1-N and variable delay circuits 2a-1 to 2a-(N1) and 3a-1 to 3a-(N1).

[0054] The configuration in FIG. 4 is obtained by replacing the delay circuits 2-1 to 2-(N1) with the variable delay circuits 2a-1 to 2a-(N1) and replacing the delay circuits 3-1 to 3-(N1) with the variable delay circuits 3a-1 to 3a-(N1) in the first embodiment.

[0055] The delay time in(i) of the variable delay circuit 2a-i between the sub-ADC 1-i (where i is an integer from 1 to (N1)) and the sub-ADC 1-(i+1) can be adjusted by using a delay control signal ctrl_in(i). Similarly, the delay time ck(i) of the variable delay circuit 3a-i can be adjusted by using the delay control signal ctrl_ck(i).

[0056] By adjusting the delay control signals ctrl_in(i) and ctrl_ck(i) such that noise of the output signals out-1 to out-N due to errors of the delay times in(i) and ck(i) is minimized while observing the signals out-1 to out-N actually output from the time interleaved ADC, it is possible to manufacture a highly accurate ADC.

[0057] FIG. 5 illustrates a configuration in a case where the present embodiment is applied to the second embodiment. The configuration in FIG. 5 is obtained by replacing the delay circuits 2-1 to 2-(N1) with the variable delay circuits 2a-1 to 2a-(N1) and replacing the delay circuits 5-(N1) to 5-1 with the variable delay circuits 5a-(N1) to 5a-1 in the second embodiment.

[0058] In FIGS. 4 and 5, the delay times of the delay circuits for both the analog input signal and the clock signal are variable, but the delay circuit for only one of the analog input signal and the clock signal may be a variable delay circuit.

[0059] In the same manner as in the first embodiment, an input buffer may be provided between the input signal source and the analog input signal terminal of the sub-ADC 1-1 at the first stage.

Fourth Embodiment

[0060] In the first to third embodiments, analog input signals input to the individual sub-ADCs all need to have the same waveform except for different time delays. That is, all gains of the delay circuits for the analog input signal are required to be 1. However, in a case where the gains of the individual delay circuits are shifted due to the influence of the circuit variation, the analog input signal input to the subsequent sub-ADC integrates gain errors, and thus noise superimposed on the output signal increases. Regarding such variations in the gain of the delay circuit, it is conceivable to make the gain (amplification factor) of the delay circuit variable such that the mismatch between the gains of the sub-ADCs can be calibrated to some extent.

[0061] FIG. 6 is a block diagram illustrating a configuration of a time interleaved ADC according to a fourth embodiment of the present invention. The time interleaved ADC of the present embodiment includes sub-ADCs 1-1 to 1-N, delay circuits 2b-1 to 2b-(N1) of which gains can be adjusted by using a gain control signal input from the outside, and delay circuits 3-1 to 3-(N1).

[0062] The configuration in FIG. 6 is obtained by replacing the delay circuits 2-1 to 2-(N1) in the first embodiment with the delay circuits 2b-1 to 2b-(N1).

[0063] A gain of the delay circuit 2b-i between the sub-ADC 1-i (where i is an integer from 1 to (N1)) and the sub-ADC 1-(i+1) can be adjusted by using a gain control signal ctrl_g(i). The delay circuit 2b-i can be realized by, for example, a combination of a delay circuit including an inverter chain circuit and the like and a variable gain amplifier.

[0064] FIG. 7 illustrates a configuration in a case where the present embodiment is applied to the second embodiment.

[0065] The present embodiment may be combined with the third embodiment. That is, in FIGS. 6 and 7, the delay circuits 2b-1 to 2b-(N1) may be variable delay and variable gain delay circuits. In addition, the delay circuits 3-1 to 3-(N1) and 5-1 to 5-(N1) may be variable delay circuits.

[0066] In the same manner as in the first embodiment, an input buffer may be provided between the input signal source and the analog input signal terminal of the sub-ADC 1-1 at the first stage.

Fifth Embodiment

[0067] In the first to fourth embodiments, the analog input signal passes through the delay circuits 2-1 to 2-(N1), 2a-1 to 2a-(N1), and 2b-1 to 2b-(N1). Thus, the output signals out-1 to out-N of the individual sub-ADCs 1-1 to 1-N are output at timings relatively shifted by the delay times of the delay circuits 2-1 to 2-(N1), 2a-1 to 2a-(N1), and 2b-1 to 2b-(N1). Processing of the digital signal processing circuit that integrates the output signals out-1 to out-N becomes complicated due to a timing shift between the output signals out-1 to out-N. In order to simplify the processing of the digital signal processing circuit, it is conceivable to provide a delay circuit for correcting a time difference between the output signals out-1 to out-N at an output of each sub-ADC.

[0068] FIG. 8 is a block diagram illustrating a configuration of a time interleaved ADC according to a fifth embodiment of the present invention. The time interleaved ADC of the present embodiment includes sub-ADCs 1-1 to 1-N, delay circuits 2-1 to 2-(N1) and 3-1 to 3-(N1), and delay circuits 6-1 to 6-N that are provided at the outputs of the sub-ADCs 1-1 to 1-N, respectively, and correct time differences between output signals out-1 to out-N of the sub-ADCs 1-1 to 1-N.

[0069] For example, the sub-ADC 1-2 receives the analog input signal delayed by in(1) from the sub-ADC 1-1. Therefore, the output signal out-2 of the sub-ADC 1-2 is delayed by in(1) compared with the output signal out-1 of the sub-ADC 1-1. Therefore, if delay circuits 6-1 and 6-2 are provided at the outputs of the sub-ADCs 1-1 and 1-2, respectively, and a delay time of the output of the sub-ADC 1-1 is made longer than a delay time of the output of the sub-ADC 1-2 by in(1), the outputs of the sub-ADCs 1-1 and 1-2 can be processed on the same time axis.

[0070] When the description of the sub-ADCs 1-1 and 1-2 is generalized for all the sub-ADCs 1-1 to 1-N, the delay circuits 6-1 to 6-N are designed to satisfy the following conditions for all the integers M of 2 or more and N or less.

Equation 1

.sub.j=1.sup.M-1.sub.in(j)+.sub.out(M)=.sub.out(1)(7)

[0071] out(1) is a delay time of the delay circuit 6-1 connected to the output of the sub-ADC 1-1, and out(M) is a delay time of the delay circuit 6-M connected to the output of the sub-ADC 1-M (where M is an integer of 2 to N).

[0072] As described above, in the present embodiment, since the output signals out-1 to out-N of the sub-ADCs 1-1 to 1-N can be processed on the same time axis, the subsequent processing is simplified.

[0073] In the example in FIG. 8, the present embodiment is applied to the first embodiment, but the delay circuits 6-1 to 6-N may be provided in the second to fourth embodiments.

[0074] In the same manner as in the first embodiment, an input buffer may be provided between the input signal source and the analog input signal terminal of the sub-ADC 1-1 at the first stage.

[0075] In the first to fifth embodiments, the analog input signal and the clock signal are single-phase signals, but either one of the analog input signal and the clock signal or both of the analog input signal and the clock signal may be differential signals. Consequently, it is expected to improve a signal-to-noise ratio by removing in-phase noise.

[0076] In a case where the analog input signal is a differential signal, the delay circuits 2-1 to 2-(N1), 2a-1 to 2a-(N1), and 2b-1 to 2b-(N1) are differential input differential output delay circuits. The sub-ADCs 1-1 to 1-N are differential input ADCs.

[0077] In a case where the clock signal is a differential signal, the delay circuits 3-1 to 3-(N1), 3a-1 to 3a-(N1), 5-1 to 5-(N1), and 5a-1 to 5a-(N1) are differential input differential output delay circuits. The sub-ADCs 1-1 to 1-N are differential clock input ADCs.

INDUSTRIAL APPLICABILITY

[0078] Embodiments of the present invention are applicable to an ADC.

REFERENCE SIGNS LIST

[0079] 1-1 to 1-N Sub-ADC [0080] 2-1 to 2-(N1), 2b-1 to 2b-(N1), 3-1 to 3-(N1), 5-1 to 5-(N1), 6-1 to 6-N Delay circuit [0081] 2a-1 to 2a-(N1), 3a-1 to 3a-(N1), 5a-1 to 5a-(N1) Variable delay circuit [0082] 4 Input buffer.