RADIATION-EMITTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING A RADIATION-EMITTING SEMICONDUCTOR CHIP

Abstract

A radiation-emitting semiconductor chip may include a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer, a first metallic mirror with which charge carriers can be embedded into the first semiconductor layer, a first metallic contact layer disposed atop the first metallic mirror, and a second metallic contact layer disposed atop the first metallic contact layer. A first seed layer may be disposed between the first metallic contact layer and the first metallic mirror. A second seed layer may be disposed between the first metallic contact layer and the second metallic contact layer. The radiation-emitting semiconductor chip may include a radiation exit face having a multitude of emission regions. The first metallic mirror may have a multitude of cutouts that each define a lateral extent of one of the emission regions.

Claims

1. A radiation-emitting semiconductor chip comprising: a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer; a first metallic mirror with which charge carriers can be embedded into the first semiconductor layer; a first metallic contact layer disposed atop the first metallic mirror; and a second metallic contact layer disposed atop the first metallic contact layer; wherein: a first seed layer is disposed between the first metallic contact layer and the first metallic mirror; and a second seed layer is disposed between the first metallic contact layer and the second metallic contact layer; the radiation-emitting semiconductor chip comprises a radiation exit face having a multitude of emission regions; and the first metallic mirror has a multitude of cutouts that each define a lateral extent of one of the emission regions.

2. The radiation-emitting semiconductor chip as claimed in claim 1, further comprising a multitude of second metallic mirrors, each of which can be used to embed charge carriers into the second semiconductor layer; and a multitude of third metallic contact layers; wherein: one of the third metallic contact layers is disposed atop each of the second metallic mirrors and a third seed layer is disposed in each case between the first metallic contact layers and the second metallic mirrors.

3. The radiation-emitting semiconductor chip as claimed in claim 1, wherein the second metallic contact layer surrounds all second metallic mirrors in lateral directions.

4. The radiation-emitting semiconductor chip as claimed in claim 1, further comprising a first insulating layer disposed between the first metallic mirror and/or the second metallic mirror and the semiconductor layer sequence.

5. The radiation-emitting semiconductor chip as claimed in claim 1, further comprising an interlayer disposed atop the first insulating layer .

6. The radiation-emitting semiconductor chip as claimed in claim 1, further comprising a second insulating layer disposed between the first metallic contact layer and the third metallic contact layers.

7. The radiation-emitting semiconductor chip as claimed in claim 1, further comprising a current spreading layer disposed between the second metallic mirror and the semiconductor layer sequence.

8. The radiation-emitting semiconductor chip as claimed in claim 1, wherein a radiation exit face of the semiconductor layer sequence is free of any growth substrate.

9. A method of producing a radiation-emitting semiconductor chip, wherein the method comprises: providing a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer; creating a first recess that exposes regions of the first semiconductor layer; creating a first metallic mirror in the first recess; applying a first seed layer to the first metallic mirror; depositing a first metallic contact layer on the first seed layer; applying a second seed layer to the first metallic contact layer; depositing a second metallic contact layer on the second seed layer; applying a first insulating layer to the semiconductor layer sequence; and creating a multitude of second recesses in the first insulating layer that each expose regions of the second semiconductor layer.

10. The method as claimed in claim 9, wherein the first recess extends along grid lines of a regular grid.

11. The method as claimed in claim 9, further comprising : creating a second metallic mirror in any one of the second recesses; applying a third seed layer to any one of the second metallic mirrors; and depositing a third metallic contact layer on any one of the third seed layers.

12. The method as claimed in claim 9, further comprising planarizing the second metallic contact layer and the third metallic contact layers.

13. The method as claimed in claim 11, further comprising depositing the first metallic contact layer, the second metallic contact layer and/or the third metallic contact layers; wherein the depositing occurs by electroplating.

14. The method as claimed in claim 9, further comprising applying one solder layer atop the second metallic contact layer and one atop the third metallic contact layers.

15. The method as claimed in claim 9, further comprising applying an auxiliary carrier atop the second metallic contact layer and the third metallic contact layers.

16. The method as claimed in claim 9, wherein a growth substrate of the semiconductor layer sequence is detached.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0088] The method of assembling a radiation-emitting semiconductor chip and the radiation-emitting semiconductor chip are elucidated in detail hereinafter by working examples and the associated figures.

[0089] The figures show: FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 and 11: schematic section diagrams of method stages in the production of a radiation-emitting semiconductor chip in one working example,

[0090] FIG. 12: schematic section diagram of a radiation-emitting semiconductor chip in one working example, and

[0091] FIGS. 13 and 14: schematic diagrams in top view of a radiation-emitting semiconductor chip in one working example.

[0092] Elements that are the same, of the same type or have the same effect are given the same reference numerals in the figures. The figures and size ratios of the elements shown in the figures with respect to one another should not be considered to be true to scale. Instead, individual elements, for better representability and/or for better comprehensibility, may be shown in excessively large size.

DETAILED DESCRIPTION

[0093] In the method steps according to FIG. 1, a semiconductor layer sequence 2 with a first semiconductor layer 3 and a second semiconductor layer 4 is provided. A current spreading layer 8 is applied to the second semiconductor layer 4. The current spreading layer 8 is in direct contact with the second semiconductor layer 4. The current spreading layer 8 is formed by ITO, for example. In addition, the current spreading layer 8 has an extent in vertical direction of about 60 nm.

[0094] Subsequently, a first insulating layer 9 is applied atop the current spreading layer 8. The first insulating layer 9 has multiple sublayers. For example, one sublayer facing the semiconductor layer sequence 2 comprises SiO.sub.2, with a height in vertical direction of about 600 nm. A sublayer remote from the semiconductor layer sequence 2 comprises, for example, SiNx with a height in vertical direction of about 20 nm.

[0095] In a further step, a multitude of second recesses 7 is created in the first insulating layer 9, each of which expose regions of the current spreading layer 8. For creation of second recesses 7, a photoresist, for instance hexamethyldisilazane (HMDS for short), with a height in vertical direction of about 6 .Math.m, is applied to the first insulating layer 9. The photoresist is exposed in such a way that it forms a second photoresist mask. By means of the second photoresist mask, the first insulating layer 9 is removed by means of an etching process, especially a plasma etching process, such that regions of the current spreading layer 8 are exposed.

[0096] The second recesses 7 are disclosed at grid points of a second regular grid, as shown, for example, in conjunction with the working example of FIG. 13. The second regular grid is, for example, a square grid.

[0097] As shown in FIG. 2, a first recess 6 is created, which exposes regions of the first semiconductor layer 3. For creation of the first recess 6, a photoresist, for instance HMDS, with a height in vertical direction of about 6 .Math.m, is applied to the first insulating layer 9 and the exposed current spreading layer 8. The photoresist is exposed in such a way that it forms a first photoresist mask. By means of the first photoresist mask, the first insulating layer 9, the current spreading layer 8, the second semiconductor layer 4 and the first semiconductor layer 3 are removed by means of an etching process, especially a plasma etching process, such that regions of the first semiconductor layer 3 are exposed. The first recess 6 has, for instance, a maximum extent in lateral directions of about 1.8 .Math.m.

[0098] The first recess 6 extends along grid lines of a first regular grid. The first regular grid is especially a square grid.

[0099] In a further method stage, FIG. 3, after the creation of the first recess 6, a dielectric mirror layer 13 is applied in the first recess 6. After the application, the dielectric layer covers the lateral face and the floor of the first recess 6. In this working example, the dielectric mirror layer 13 is formed by SiO.sub.2. The SiO.sub.2 layer is applied here by a PECVD process. In “PECVD”, the dielectric mirror layer 13 is produced using tetraethyl orthosilicate (TEOS). The TEOS is the source of the silicon.

[0100] The dielectric mirror layer 13 thus created is removed at the floor of the first recess 6 such that the first semiconductor layer 3 is exposed there. The removing of the dielectric mirror layer 13 at the floor is implemented via anisotropic etching method. The dielectric mirror layer 13 after the etching process has a thickness in lateral direction of about 500 nanometers.

[0101] Subsequently, a first metallic mirror 14 is created in the first recess 6. In addition, a multitude of second metallic mirrors 15 is created in the second recesses 7.

[0102] The first metallic mirror 14 is created with a third photoresist mask. For example, a photoresist, for instance HMDS, is applied with a height in vertical direction of about 4.8 .Math.m to the first insulating layer 9 and the exposed current spreading layer 8. The photoresist is exposed in such a way that it forms the third photoresist mask.

[0103] The second metallic mirrors 15 are created with a fourth photoresist mask.

[0104] The first mirror 14 and the second mirrors 15 comprising a layer sequence. For example, the layers of the layer, have the following layer sequence: 20 nm of ITO, 200 nm of Ag, 50 nm of Pt, 100 nm of Ti, 120 nm of Ni, 5 nm of Ti.

[0105] Once created, the first metallic mirror 14 completely fills the first recess 6. In addition, the first metallic mirror 14 surmounts the first recess 6 in vertical direction. The part of the metallic mirror 14 that surmounts the first recess 6 in vertical direction surmounts the first recess 6 in lateral directions as well. This means that the first metallic mirror 14 is disposed in regions of the first electrically insulating layer 9. The part of the first metallic mirror 14 disposed atop the first electrically insulating layer 9 is spaced apart in lateral directions from any of the parts of the second metallic mirrors 15 disposed atop the first electrically insulating layer 9. For example, the spacing in lateral directions is about 5 .Math.m.

[0106] Once created, the second metallic mirrors 15 completely fill the second recesses 7. Any one of the second metallic mirrors 15 surmounts any one of the second recesses 6 in vertical direction and in lateral directions. This means that each of the second metallic mirrors 15 is disposed atop regions of the first electrically insulating layer 9.

[0107] In the method stage according to FIG. 4, a further first insulating layer 10 is applied atop the first insulating layer 9, the first metallic mirror 14 and the second metallic mirrors 15. The further first insulating layer 10 comprises, for example, SiNx and has a height in vertical direction of about 350 nm.

[0108] Subsequently, the further first insulating layer 10 is structured by means of a fifth photoresist layer in such a way that a first opening is created in the further first insulating layer 10. For creation of the first opening, a photoresist, for instance HMDS, with a height in vertical direction of about 8 .Math.m, is applied to the first insulating layer 9, the first metallic mirror 14 and the second metallic mirrors 15. The photoresist is exposed in such a way that it forms the fifth photoresist mask. By means of a plasma etching process, the first opening is created.

[0109] The first opening here exposes regions of the first metallic mirror 14. The exposed region of the first metallic mirror 14 has a width in lateral directions of about 50 .Math.m in the outer region. In addition, regions of the first metallic mirror 14 are exposed by the first recess in an inner region as well. The outer region 28 is described in detail, for example, in conjunction with FIG. 13.

[0110] In a further method stage according to FIG. 5, a photoresist, for instance HMDS, is applied with a height in vertical direction of about 3.9 .Math.m atop the further first insulating layer 10 and the exposed first metallic mirror 14. The photoresist is exposed in such a way that it forms a sixth photoresist mask. The sixth photoresist mask here covers exclusively regions between the first metallic mirror 14 and the second metallic mirrors 15, and regions above the second metallic mirrors 15. Regions above the first metallic mirror 14 here are free of the sixth photoresist mask.

[0111] A first seed layer 19 is subsequently applied atop the sixth photoresist mask and the exposed regions. The first seed layer 19 here comprises three sublayers which, viewed from the first metallic mirror 14, have the following layer sequence: 20 nm of Ti, 20 nm of Pt, 200 nm of Au.

[0112] Subsequently, the sixth photoresist mask is removed, such that the first seed layer 19 is disposed above the region of the first metallic mirror 14.

[0113] In the method stage according to FIG. 6, an interlayer 11 is disposed atop the further first insulating layer 10 and the first seed layer 19. The seed layer 19 is disposed atop the first metallic mirror 14 in regions between the interlayer 11 and the first seed layer 19. The interlayer 11 is an antireflective layer comprising SiNx. The interlayer 11 has a height in vertical direction of about 20 nm and is applied by a chemical vapor deposition process (CVD).

[0114] Subsequently, a photoresist, for instance HMDS, is applied with a height in vertical direction of about 15 .Math.m atop the interlayer 11. The photoresist is exposed in such a way that it forms a seventh photoresist mask. Regions on which a first metallic contact layer 16 is grown are not covered by the seventh photoresist mask. In these regions, the interlayer 11 is removed by means of an etching process in such a way that the first seed layer 19 is exposed.

[0115] In a further step, the first metallic contact layer 16 is created on the exposed first seed layer 19. Here, the first metallic contact layer 16 is deposited by means of electroplating. The first metallic contact layer 16 comprises Ni. After deposition, the first metallic contact layer 16 has an extent in the direction of about 10 .Math.m.

[0116] Subsequently, it is possible that a Ti layer is deposited on a top face of the first metallic contact layer 16. The Ti layer is especially an adhesion promoter. The seventh photoresist mask is detached again after the application of the Ti layer.

[0117] In a further method stage according to FIG. 7, a second insulating layer 12 is disposed atop the interlayer 11 and the first metallic contact layer 16. The second insulating layer 12 is a dielectric mirror layer. The second insulating layer 12 comprises multiple sublayers. A sublayer facing the semiconductor layer sequence 2 comprises SiO.sub.2 with a height and/or width of 660 nm, and a sublayer facing the semiconductor layer sequence 2 comprises SiN.sub.x with a height and/or width of 250 nm. The SiO.sub.2 layer is applied here by a PECVD process using tetraethyl orthosilicate (TEOS).

[0118] Subsequently, a photoresist, for instance HMDS, is applied with a height in vertical direction of about 8 .Math.m, atop the second insulating layer 12. The photoresist is exposed in such a way that it forms an eighth photoresist mask.

[0119] By means of the eighth photoresist mask, a third recess 30 and a multitude of fourth recesses 31 are created by a plasma etching process. The third recess 30 completely penetrates the second insulating layer 12 disposed above the first metallic contact layer 16, such that the third recess 30 exposes regions of the first metallic contact layer 16. In addition, any one of the fourth recesses 31 exposes regions of any one of the second metallic mirrors 15. Lateral faces of the fourth recesses 31 in this case are formed by the further first insulating layer 10, the interlayer 11 and the second insulating layer 12.

[0120] The third recess 30 has, for example, an extent in lateral directions of about 90 .Math.m. Any one of the fourth openings 31 has, for example, an extent in lateral directions of about 10 .Math.m.

[0121] In the method stage according to FIG. 8, a second seed layer 20 and third seed layers 21 are applied atop the second insulating layer 12, in the third recess 30 and in the fourth recesses 31. In this case, the second seed layer 20 and the third seed layers 21 are applied in a common process. The second seed layer 20 here is disposed above the first metallic contact layer 16, and the third seed layers 21 above the second metallic mirror 15. The second seed layer 20 in the third recess 30 is in direct contact with the first metallic contact layer 16. In addition, any one of the third seed layers 21 in any one of the fourth openings 31 is in direct contact with any one of the second metallic mirrors 15.

[0122] Subsequently, a photoresist having a height in vertical direction of about 75 .Math.m is applied atop the second seed layer 20 and the third seed layers 21. The photoresist is exposed in such a way that it forms a ninth photoresist mask. A region in which a second metallic contact layer 17 is grown is not covered by the ninth photoresist mask. The second seed layer 20 is exposed in this region. In addition, regions in which the metallic contact layers 18 are grown are not covered by the ninth photoresist mask. The third seed layers 21 are exposed in these regions.

[0123] In a further step, the second metallic contact layer 17 is created on the exposed second seed layer 20. Here, the second metallic contact layer 17 is deposited by means of electroplating. The second metallic contact layer 17 comprises Ni. After deposition, the second metallic contact layer 17 has an extent in vertical direction of about 15 .Math.m.

[0124] In the same process step in which the second metallic contact layer 17 is created, the third metallic contact layers 18 are created atop the exposed third seed layers 21. Here, the third metallic contact layers 18 are likewise deposited by means of electroplating. This means that the third metallic contact layers 18 also comprise Ni and each have an extent in vertical direction of about 15 .Math.m.

[0125] Subsequently, the eighth photoresist layer is removed.

[0126] In the method stage of FIG. 9, the second seed layer 20 disposed alongside the second metallic contact layer 17 in lateral directions is removed by means of a wet-chemical etching process. In addition, the third seed layers 21 disposed alongside the third metallic contact layers 18 are removed by means of a wet-chemical etching process.

[0127] In a further step, the second metallic contact layer 17 and the third metallic contact layers 18 are planarized. For example, the second metallic contact layer 17 and the third metallic contact layers 18 are planarized by means of a grinding process in such a way that a top face of the second metallic contact layer 17 and a top face of the third metallic contact layers 18 are in a common plane.

[0128] Subsequently, it is possible that the top face of the second metallic contact layer 17 and the top face of the third metallic contact layers 18 are polished by means of a chemical-mechanical polishing process.

[0129] In the method stage according to FIG. 10, a solder layer 22 is applied atop the second metallic contact layer 17 and atop the third metallic contact layers 18. The solder layers 22 here comprise sublayers, for example. A sublayer of the solder layers 22 facing the semiconductor layer sequence 2 comprises Ni with an extent in vertical direction of about 10 nm, and a sublayer of the solder layers 22 remote from the semiconductor layer sequence 2 comprises Au with an extent in vertical direction of about 100 nm. The solder layers 22 each completely cover the outer face of the second metallic contact layer 17 and the outer face of the third metallic contact layers 18.

[0130] In a further method stage according to FIG. 11, an auxiliary carrier 23 is applied atop the second metallic contact layer 17 and the third metallic contact layers 18. Here, the auxiliary carrier 23 is applied to the solder layers 22. Subsequently, a growth substrate 5 of the semiconductor layer sequence 2 is detached.

[0131] The radiation-emitting semiconductor chip 1 according to the working example of FIG. 12 may especially be produced by the method described in conjunction with FIGS. 1 to 11. The radiation-emitting semiconductor chip 1 has a semiconductor layer sequence 2 with a first semiconductor layer 3 and a second semiconductor layer 4. Between the first semiconductor layer 3 and the second semiconductor layer 4 is disposed an active region 25.

[0132] In addition, the radiation-emitting semiconductor chip 1 comprises a first metallic mirror 14 with which charge carriers can be embedded into the first semiconductor layer 3. Atop the first metallic mirror 14 is disposed a further first insulating layer 10 having a first opening. A first seed layer 19 is disposed in the first opening. The first seed layer 19 is also disposed in regions atop the further first insulating layer 10.

[0133] An interlayer 11 is also disposed in regions atop the first seed layer 19. The interlayer 11 here defines a lateral region of the first seed layer 19 on which a first metallic contact layer 16 is disposed.

[0134] Additionally disposed atop the first metallic contact layer 16 is a second insulating layer 12. In an outer region 28, the second insulating layer 12 has a third recess 30. In an inner region 29, the second insulating layer 12 covers the first metallic contact layer 16 completely. The outer region 28 and the inner region 29 are described in detail, for example, in conjunction with FIG. 13.

[0135] Disposed atop the first metallic contact layer 16 in the outer region 28 is a second seed layer 20. The second seed layer 20 is disposed in the third recess 30. In addition, the second seed layer 20 is disposed in regions atop the second insulating layer 12.

[0136] Disposed atop the second seed layer 20 is a second metallic contact layer 17. Disposed atop the second metallic contact layer 17 in turn is a solder layer 22.

[0137] Spaced apart in lateral directions from the first metallic mirror 14, the radiation-emitting semiconductor chip comprises second metallic mirrors 15 by which charge carriers can be embedded into the second semiconductor layer 4. Disposed atop the second metallic mirrors 15 in each case are the further first insulating layer 10, the interlayer 11 and the second insulating layer. In the further first insulating layer 10, the interlayer 11 and the second insulating layer, a fourth recess 31 is disposed in each case above the second metallic mirrors 15. A third seed layer 21 is disposed in each of the fourth openings 31. The third seed layers 21 are also disposed in regions atop the further first insulating layer 10.

[0138] A third metallic contact layer 18 is disposed atop each of the third seed layers 21. A solder layer 22 is disposed in turn atop each of the third metallic contact layers 18.

[0139] The first metallic mirror 14 extends in regions through the second semiconductor layer 2 into the first semiconductor layer 3. This means that the active region 25 is penetrated and structured by the first metallic mirror 14. The first metallic mirror 14 structures the active region 25 here in multiple subregions 26 of the active region 25. Each subregion 26 of the active region 25 is designed to generate electromagnetic radiation and to emit it via an assigned emission region 27. All emission regions 27 form a radiation exit face 24 of the radiation-emitting semiconductor chip 1.

[0140] The radiation-emitting semiconductor chip 1 in the working example of FIG. 13 comprises a multitude of emission regions 27 that are separated by the first metallic mirror 14 in lateral directions.

[0141] The first metallic mirror 14 and the first metallic contact element 16 extend along gridlines of a first regular grid. The emission regions 27 are disposed at grid points of a second regular grid. The grid points of the second regular grid are arranged here between the gridlines of the first regular grid. This means that the first metallic mirror 14 has a multitude of recesses 32, each of which defines a lateral extent of one of the emission regions 27.

[0142] The radiation-emitting semiconductor chip 1 has an outer region 28 and an inner region 29. The outer region 28 extends along outer gridlines of the first regular grid. The outer region 28 is spaced apart in lateral directions from the emission regions 27 of the radiation-emitting semiconductor chip 2. This means that the outer region 28 completely surrounds the emission regions 27 in the inner region 29 in lateral directions.

[0143] In addition, the line between points A and B indicates a section in vertical direction, the position of which is also shown in FIGS. 1 to 12.

[0144] In conjunction with FIG. 14, the dotted line between C and D indicates a section line in the schematic section diagrams according to FIGS. 1 to 12.

[0145] The features and working examples described in conjunction with the figures may be combined with one another in further working examples, even if not all combinations are explicitly described. In addition, the working examples described in conjunction with the figures may alternatively or additionally have further features according to the description in the general part.

[0146] The invention is not limited to the working examples by the description with reference thereto. Instead, the invention encompasses every new feature and every combination of features, which especially include any combination of features in the claims, even if this feature of this combination itself is not explicitly specified in the patent claims or working examples.

LIST OF REFERENCE NUMERALS

[0147] 1 radiation-emitting semiconductor chip [0148] 2 semiconductor layer sequence [0149] 3 first semiconductor layer [0150] 4 second semiconductor layer [0151] 5 growth substrate [0152] 6 first recess [0153] 7 second recess [0154] 8 current spreading layer [0155] 9 first insulating layer [0156] 10 further first insulating layer [0157] 11 interlayer [0158] 12 second insulating layer [0159] 13 dielectric mirror layer [0160] 14 first metallic mirror [0161] 15 second metallic mirror [0162] 16 first metallic contact layer [0163] 17 second metallic contact layer [0164] 18 third metallic contact layer [0165] 19 first seed layer [0166] 20 second seed layer [0167] 21 third seed layer [0168] 22 solder layer [0169] 23 auxiliary carrier [0170] 24 radiation exit face [0171] 25 active region [0172] 26 subregion of active region [0173] 27 emission region [0174] 28 outer region [0175] 29 inner region [0176] 30 third recess [0177] 31 fourth recess [0178] 32 cutout