Temperature Compensation Circuit and Method for Neural Network Computing-in-memory Array

Abstract

The disclosure discloses a temperature compensation circuit and method for a neural network computing-in-memory array. Reference arrays sparsely inserted in the computing-in-memory array are adopted to provide a reference voltage for ADCs, so that an input voltage and a reference voltage of the ADCs have a same temperature coefficient. Finally, after analog-to-digital conversion by the ADC, the digital output of the ADC is not affected by the external temperature, thereby ensuring the operational precision of the neural network. According to the temperature compensation circuit of the disclosure, the reference arrays have the same structure as the computing-in-memory array. The insertion density of the reference arrays is related to the temperature field where the computing-in-memory arrays are located. One reference array may provide the reference voltage of the ADC for a plurality of computing-in-memory arrays, thereby minimizing the increase of area and power consumption caused by inserting the reference arrays.

Claims

1. A temperature compensation circuit for a neural network computing-in-memory array, configured to perform temperature compensation on the neural network computing-in-memory array composed of N-type floating-gate devices, wherein the temperature compensation circuit comprises a reference array composed of two columns of N-type floating-gate devices for storing weights, a current subtractor circuit and an I-V conversion resistor R.sub.1; the two columns of N-type floating-gate devices for storing weights respectively comprise n N-type floating-gate devices MR.sub.1+-MR.sub.n+ and n N-type floating-gate devices MR.sub.1−-MR.sub.n−; in the reference array, gates of the n N-type floating-gate devices MR.sub.1+-MR.sub.n+ are connected to a same fixed voltage V.sub.GS, drains are connected to a same fixed voltage V.sub.DS, and sources are connected with each other and to a fixed voltage V.sub.S and connected into a positive input end of the current subtractor circuit; in the reference array, gates of the n N-type floating-gate devices MR.sub.1−-MR.sub.n− are connected to the same fixed voltage V.sub.GS, drains are connected to the same fixed voltage V.sub.DS, and sources are connected with each other and to the fixed voltage V.sub.s and connected into a negative input end of the current subtractor circuit; an output end of the subtractor circuit is connected to one end of the I-V conversion resistor R.sub.1, and connected through a voltage buffer into a reference end of an analog-to-digital converter (ADC) connected with the computing-in-memory array; the other end of the I-V conversion resistor R.sub.1 is grounded; and the I-V conversion resistor R.sub.1 has same parameters as an I-V conversion resistor R.sub.0 in a readout circuit of the computing-in-memory array.

2. The temperature compensation circuit according to claim 1, wherein the neural network computing-in-memory array is composed of n N-type floating-gate devices M.sub.1+-M.sub.n+ and n N-type floating-gate devices M.sub.1−-M.sub.n−; the readout circuit of the computing-in-memory array comprises one subtractor circuit, one I-V conversion resistor R.sub.0 and the analog-to-digital converter (ADC); in the neural network computing-in-memory array, gates of the n N-type floating-gate devices M.sub.1+-M.sub.n+ are respectively connected to voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to input voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to the fixed voltage V.sub.S, and connected into the positive input end of the current subtractor circuit; gates of the n N-type floating-gate devices M.sub.1−-M.sub.n− are respectively connected to the voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to the voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to the fixed voltage V.sub.S, and connected into the negative input end of the current subtractor circuit; an output end of the current subtractor circuit is connected to one end of the I-V conversion resistor R.sub.0 and connected into a data input end of the analog-to-digital converter (ADC); the other end of the I-V conversion resistor R.sub.0 is grounded; and the current subtractor circuit is configured to perform a subtraction operation on an input current of the positive input end and an input current of the negative input end.

3. A temperature compensation circuit for a neural network computing-in-memory array, configured to perform temperature compensation on the neural network computing-in-memory array composed of P-type floating-gate devices, wherein the temperature compensation circuit comprises a reference array composed of two columns of P-type floating-gate devices for storing weights, a current subtractor circuit and an I-V conversion resistor R.sub.1; the two columns of P-type floating-gate devices for storing weights respectively comprise n P-type floating-gate devices MR.sub.1+-MR.sub.n+ and n P-type floating-gate devices MR.sub.1−-MR.sub.n−; in the reference array, gates of the n P-type floating-gate devices MR.sub.1+-MR.sub.n+ are connected to a same fixed voltage V.sub.GS, drains are connected to a same fixed voltage V.sub.DS, and sources are connected with each other and to a fixed voltage V.sub.S and connected into a positive input end of the current subtractor circuit; in the reference array, gates of the n P-type floating-gate devices MR.sub.1−-MR.sub.n− are connected to the same fixed voltage V.sub.GS, drains are connected to the same fixed voltage V.sub.DS, and sources are connected with each other and to the fixed voltage V.sub.S and connected into a negative input end of the current subtractor circuit; an output end of the subtractor circuit is connected to one end of the I-V conversion resistor R.sub.1, and connected through a voltage buffer into a reference end of the analog-to-digital converter connected with the computing-in-memory array; the other end of the I-V conversion resistor R.sub.1 is grounded; and the I-V conversion resistor R.sub.1 has same parameters as an I-V conversion resistor R.sub.0 in a readout circuit of the computing-in-memory array.

4. The temperature compensation circuit according to claim 3, wherein the neural network computing-in-memory array is composed of n P-type floating-gate devices M.sub.1+-M.sub.n+ and n P-type floating-gate devices M.sub.1−-M.sub.e−; the readout circuit of the computing-in-memory array comprises one subtractor circuit, one I-V conversion resistor R.sub.0 and the analog-to-digital converter (ADC); in the neural network computing-in-memory array, gates of the n P-type floating-gate devices M.sub.1+-M.sub.n+ are respectively connected to voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to input voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to the fixed voltage V.sub.S, and connected into the positive input end of the current subtractor circuit; gates of the n P-type floating-gate devices M.sub.1−-M.sub.n− are respectively connected to the voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to the voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to the fixed voltage V.sub.S, and connected into the negative input end of the current subtractor circuit; an output end of the current subtractor circuit is connected to one end of the conversion resistor R.sub.0 and connected into a data input end of the analog-to-digital converter (ADC); the other end of the conversion resistor R.sub.0 is grounded; and the current subtractor circuit is configured to perform a subtraction operation on an input current of the positive input end and an input current of the negative input end.

5. A temperature compensation method for a neural network computing-in-memory array, applied to the temperature compensation circuit according to claim 1, the method comprising: step I: determining the number and position of reference arrays according to temperature field distribution of the computing-in-memory array in actual work; step II: calculating a gate voltage V.sub.GS, a drain voltage V.sub.DS and a threshold voltage difference ΔV.sub.TH of floating-gate devices MR.sub.1+-MR.sub.n+ and MR.sub.1−-MR.sub.n− in the reference array according to values of a reference voltage and an I-V conversion resistor R.sub.1 required by the analog-to-digital converter; step III: inputting the gate voltage V.sub.GS and the drain voltage V.sub.DS from the outside into gates and drains of the floating-gate devices according to the calculation result of step II, and regulating a threshold voltage V.sub.TH of the floating-gate devices to obtain the threshold voltage difference ΔV.sub.TH calculated in step II; and step IV: enabling the reference array to generate a reference current I.sub.REF according to the operation of step III; and converting the reference current I.sub.REF into the reference voltage V.sub.REF of the analog-to-digital converter by the resistor R.sub.1.

6. The temperature compensation method according to claim 5, wherein the reference array and the computing-in-memory array are located in a same temperature field, and the reference current I.sub.REF generated after the operation of the reference array and a current I.sub.OUT generated after the operation of the computing-in-memory array change in a same proportion, so that a ratio of the input voltage to the reference voltage of the analog-to-digital converter before and after the temperature change remains unchanged, so as to ensure the correctness of output data of the analog-to-digital converter.

7. The temperature compensation method according to claim 5, wherein one reference array is adopted to provide the reference voltage for the analog-to-digital converters connected to all the computing-in-memory arrays in the same temperature field.

8. The temperature compensation method according to claim 7, wherein when one reference array is adopted to provide the reference voltage for the analog-to-digital converters connected to all the computing-in-memory arrays in the same temperature field, the reference array is inserted in the middle of all the computing-in-memory arrays in the same temperature field.

9. The temperature compensation method according to claim 5, wherein the reference array generates a constant current to provide the constant reference voltage for the analog-to-digital converter when working normally, and regulates the gate voltage V.sub.GS to turn off the devices in the reference array when not working.

10. The temperature compensation method according to claim 5, wherein the reference array in the same temperature field as the computing-in-memory arrays is adopted to provide the reference voltage for the analog-to-digital converters connected to the computing-in-memory arrays, so as to compensate for temperature drift characteristics of mobility of the N-type or P-type floating-gate devices in the computing-in-memory arrays.

Description

BRIEF DESCRIPTION OF FIGURES

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the disclosure, the accompanying drawings required in the description of the embodiments will be briefly described below. Apparently, the accompanying drawings in the description below are only some embodiments of the disclosure, and those of ordinary skill in the art can obtain other accompanying drawings according to these drawings without any creative work.

[0045] FIG. 1 is a schematic structural diagram of a temperature compensation circuit based on N-type floating-gate devices according to the disclosure;

[0046] FIG. 2 is a schematic structural diagram of a temperature compensation circuit based on P-type floating-gate devices according to the disclosure;

[0047] FIG. 3 is a schematic structural diagram of a temperature compensation circuit based on N-type floating-gate devices according to Embodiment I of the disclosure;

[0048] FIG. 4 is a schematic structural diagram of a temperature compensation circuit based on P-type floating-gate devices according to Embodiment II of the disclosure;

[0049] FIG. 5 is a schematic structural diagram of a test circuit according to Embodiment III of the disclosure;

[0050] FIG. 6 is a schematic diagram showing the positional relationship when one reference array corresponds to a plurality of neural network computing-in-memory arrays according to the disclosure;

[0051] FIG. 7 is a simulation diagram showing a result of the test circuit at 25° C. according to Embodiment III of the disclosure;

[0052] FIG. 8 is a simulation diagram showing a result of the test circuit at 0° C. according to Embodiment III of the disclosure; and

[0053] FIG. 9 is a simulation diagram showing a result of the test circuit at 100° C. according to Embodiment III of the disclosure.

DETAILED DESCRIPTION

[0054] The implementations of the disclosure will be described clearly and completely with reference to the schematic diagrams of the disclosure below. Apparently, the implementations described are only a part of the implementations of the disclosure. All other implementations obtained by others in the art without creative work based on the implementations in the disclosure shall fall into the scope of the disclosure.

Embodiment I

[0055] This embodiment provides a temperature compensation circuit, configured to perform temperature compensation on a neural network computing-in-memory array composed of N-type floating-gate devices. As shown in FIG. 3, the neural network computing-in-memory array is composed of n N-type floating-gate devices M.sub.1+-M.sub.n+ and n N-type floating-gate devices M.sub.1−-M.sub.n−. Gates of the n N-type floating-gate devices M.sub.1+-M.sub.n+ are respectively connected to voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to input voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to a fixed voltage V.sub.S, and connected into a positive input end of a current subtractor circuit. Gates of the n N-type floating-gate devices M.sub.1−-M.sub.n− are respectively connected to the voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to the voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to the fixed voltage V.sub.S, and connected into a negative input end of the current subtractor circuit. The current subtractor circuit is configured to perform a subtraction operation on an input current of the positive input end and an input current of the negative input end. An output end of the current subtractor circuit is connected to one end of the conversion resistor R.sub.0 and connected into an input end of the analog-to-digital converter (ADC). The other end of the conversion resistor R.sub.0 is grounded.

[0056] The temperature compensation circuit includes: a reference array, a current subtractor circuit and an I-V conversion resistor R.sub.1. The reference array includes two (one positive and one negative) columns of floating-gate devices. One column of floating-gate devices includes n N-type floating-gate devices MR.sub.1+-MR.sub.n+, and the other column of floating-gate devices includes n N-type floating-gate devices M.sub.R1−-M.sub.Rn−.

[0057] As shown in FIG. 3, in the reference array, gates of then N-type floating-gate devices M.sub.R1+-MR.sub.n+ are connected to a same fixed voltage V.sub.GS_REF, drains are connected to a same fixed voltage V.sub.DS_REF, and sources are connected with each other and to a fixed voltage V.sub.DS_REF and connected into a positive input end of the current subtractor circuit. In the reference array, gates of the n N-type floating-gate devices MR.sub.1−-MR.sub.n− are connected to the same fixed voltage V.sub.GS_REF, drains are connected to the same fixed voltage V.sub.DS_REF, and sources are connected with each other and to the fixed voltage V.sub.S and connected into a negative input end of the current subtractor circuit. An output end of the subtractor circuit is connected to one end of the resistor R.sub.1, and connected through a voltage buffer into a reference end of the analog-to-digital converter (ADC). The other end of the resistor R.sub.1 is grounded. The resistor R.sub.1 has same parameters as an I-V conversion resistor R.sub.0 in a readout circuit of the computing-in-memory array.

[0058] The readout circuit of the computing-in-memory array includes one subtractor circuit, one I-V conversion resistor R.sub.0 and the analog-to-digital converter (ADC).

[0059] This embodiment further provides a temperature compensation method for a neural network computing-in-memory array, which is used for realizing the temperature compensation circuit for a computing-in-memory array composed of N-type floating-gate devices. The method includes the following steps:

[0060] Step I: Determine the number and position of reference arrays according to temperature field distribution of the computing-in-memory array in actual work.

[0061] If the computing-in-memory arrays in computing-in-memory equipment are located in the same temperature field, then one reference array is arranged in the temperature field. If the temperature field contains a plurality of computing-in-memory arrays, the reference array may be arranged in the middle of all the computing-in-memory arrays, as shown in FIG. 6.

[0062] If the computing-in-memory arrays in the computing-in-memory equipment are located in a plurality of temperature fields, then one reference array is arranged for each temperature field.

[0063] Step II: Calculate a gate voltage V.sub.GS_REF, a drain voltage V.sub.DS_REF and a threshold voltage difference ΔV.sub.THN_REF of floating-gate devices MR.sub.1+-MR.sub.n+ and MR.sub.1−-MR.sub.n− in the reference array according to values of a reference voltage and a resistor R.sub.1 required by the analog-to-digital converter.

[0064] Step III: Input the gate voltage V.sub.GS_REF and the drain voltage V.sub.DS_REF from the outside into gates and drains of the devices according to the calculation result of step II, and regulate a threshold voltage V.sub.TH of the devices by programming and erasing operations to obtain the threshold voltage difference ΔV.sub.THN_REF calculated in step II.

[0065] Step IV: Enable the reference array to generate a reference current I.sub.REF according to the operation of step III; and convert the reference current I.sub.REF into the reference voltage V.sub.REF of the analog-to-digital converter by the resistor R.sub.1.

[0066] The reference current I.sub.REF generated by the reference array is converted by the resistor R.sub.1 into the reference voltage V.sub.REF of the analog-to-digital converter.

[0067] According to the temperature compensation method of this embodiment, the reference array and the computing-in-memory array are located in the same temperature field, and the current I.sub.REF generated after the operation of the reference array and a current I.sub.OUT generated after the operation of the computing-in-memory array change in a same proportion, so that a ratio of the input voltage to the reference voltage of the analog-to-digital converter before and after the temperature change remains unchanged, so as to ensure the correctness of output data of the analog-to-digital converter.

[0068] The specific working process of the temperature compensation circuit of this embodiment is as follows:

[0069] In a non-readout mode, the gate voltage V.sub.GS_REF of all the floating-gate devices in the reference array are grounded, and at this time, no current is output from the reference array.

[0070] In a readout mode, the weights stored in the two columns of floating-gate devices in the computing-in-memory array are ΔV.sub.THN1-ΔV.sub.THNn, the weights stored in the two columns of floating-gate devices in the reference array are all ΔV.sub.THN_REF, and the computing-in-memory array obtains a corresponding output current I.sub.OUT through the subtractor circuit:

[00004]$I_{\mathrm{OUT}}={\mu }_N{C}_{\mathrm{ox}}\frac{W}{L}\left({\Delta V}_{\mathrm{THN}1}{V}_{DS1}+{\Delta V}_{\mathrm{THN}2}{V}_{DS2}+.Math.+{\Delta V}_{\mathrm{THNn}}{V}_{\mathrm{DSn}}\right)$

[0071] μN is the mobility of all the N-type floating-gate devices, C.sub.ox is the capacitance of the gate oxide layer, and W and L are respectively the width and length of the floating-gate device.

[0072] The output current I.sub.OUT is subjected to I-V conversion to obtain a corresponding output voltage V.sub.OUT:

[00005]$V_{\mathrm{OUT}}={\mu }_N{C}_{\mathrm{ox}}\frac{W}{L}{R}_0\left({\Delta V}_{\mathrm{THN}1}{V}_{DS1}+{\Delta V}_{\mathrm{THN}2}{V}_{DS2}+.Math.+{\Delta V}_{\mathrm{THNn}}{V}_{\mathrm{DSn}}\right);$

[0073] The reference array obtains a reference current I.sub.REF through the subtractor circuit:

[00006]$I_{\mathrm{REF}}={n\mu }_N{C}_{\mathrm{ox}}\frac{W}{L}\left({\Delta V}_{\mathrm{THN}\_\mathrm{REF}}{V}_{\mathrm{DS}\_\mathrm{REF}}\right),$

[0074] The reference current I.sub.REF is subjected to I-V conversion to obtain a reference voltage V.sub.REF:

[00007]$V_{\mathrm{REF}}={n\mu }_N{C}_{\mathrm{ox}}\frac{W}{L}{R}_1\left({\Delta V}_{{\mathrm{THN}}_{-}\mathrm{REF}}{V}_{D{S}_{-}\mathrm{REF}}\right),$

[0075] Assuming that the ADC is an m-bit ADC, then the ADC outputs the digital result:

[00008]$\mathrm{CODE}=V_{\mathrm{OUT}}/V_{\mathrm{REF}})\times \left(2^m-1\right)=\left[\left({\Delta V}_{\mathrm{THN}1}{V}_{\mathrm{DS}1}+{\Delta V}_{\mathrm{THN}2}{V}_{\mathrm{DS}2}+.Math.{\Delta V}_{\mathrm{THNn}}{V}_{\mathrm{DSn}}\right)/n\text{⁠}\left({\Delta V}_{\mathrm{THN}\_\mathrm{REF}}{V}_{\mathrm{DS}\_\mathrm{REF}}\right)\right]\times \left(2^m-1\right),$

as can be seen, the formula of the digital result output by the ADC does not contain any parameter related to temperature characteristic, so that the digital output of the ADC will not change with the temperature. That is, the temperature compensation method in the disclosure eliminates the temperature drift characteristic of the N-type floating-gate devices.

[0076] According to the temperature compensation method of this embodiment, one reference array is adopted to provide the reference voltage for the analog-to-digital converters connected to all the computing-in-memory arrays in the same temperature field, and a plurality of reference arrays may also be adopted according to the load of a current load circuit.

[0077] According to the temperature compensation method of this embodiment, the reference array is inserted in the middle of all the computing-in-memory arrays in the same temperature field.

[0078] According to the temperature compensation method of this embodiment, optionally, the reference array generates a constant current to provide the constant reference voltage for the analog-to-digital converter when working normally, and regulates the gate voltage V.sub.GS to turn off the devices in the reference array when not working, thereby reducing the power consumption.

[0079] According to the temperature compensation method of this embodiment, optionally, the reference array in the same temperature field as the computing-in-memory arrays is adopted to provide the reference voltage for the analog-to-digital converters connected to the computing-in-memory arrays, so as to compensate for temperature drift characteristic of mobility of the N-type floating-gate devices in the computing-in-memory arrays.

[0080] According to the temperature compensation circuit and method of this embodiment, the gate voltage of the floating-gate devices in the reference array may be controlled to determine whether the reference array works or not, and the reference array does not generate the reference current I.sub.REF when not working.

[0081] According to the temperature compensation circuit and method of this embodiment, since the working principle of the ADC is to calculate the ratio of the input voltage to the reference voltage, in the temperature compensation circuit and method of the disclosure and the current I.sub.REF generated after the operation of the reference array and the current I.sub.OUT generated after the operation of the computing-in-memory array located in the same temperature field as the reference array change in the same proportion, so that the ratio of the input voltage to the reference voltage before and after the temperature change remains unchanged, so as to ensure the correctness of output data of the ADC and also ensure the correctness of data transfer between the arrays.

[0082] According to the temperature compensation circuit and method of this embodiment, the temperature compensation is performed not by directly aiming at the output current of the array or the converted output voltage, but by eliminating the temperature drift characteristic of mobility of the floating-gate devices to realize temperature compensation in a way that the reference array provides the reference voltage for the ADCs to make the digital output of the ADCs not affected by the change of the external temperature.

[0083] According to the temperature compensation circuit and method of this embodiment, since it is only required to make I.sub.REF and I.sub.OUT change in the same proportion, there is no limit to the position of the peripheral circuits of the array, so that the current subtractor circuit and the peripheral circuits can be located in a different layer or a different temperature field from the device array.

Embodiment II

[0084] This embodiment provides a temperature compensation circuit, configured to perform temperature compensation on a neural network computing-in-memory array composed of P-type floating-gate devices. As shown in FIG. 4, the neural network computing-in-memory array is composed of n P-type floating-gate devices M.sub.1+-M.sub.n+ and n P-type floating-gate devices M.sub.1−-M.sub.n−. Gates of the n P-type floating-gate devices M.sub.1+-M.sub.n+ are respectively to connected to voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to input voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to a fixed voltage V.sub.S, and connected into a positive input end of a current subtractor circuit. Gates of the n P-type floating-gate devices M.sub.1−-M.sub.n− are respectively connected to the voltages V.sub.GS1-V.sub.GSn, drains are respectively connected to the voltages V.sub.DS1-V.sub.DSn, and sources are connected with each other and to the fixed voltage V.sub.S, and connected into the negative input end of the current subtractor circuit. The current subtractor circuit is configured to perform a subtraction operation on an input current of the positive input end and an input current of the negative input end. An output end of the current subtractor circuit is connected to one end of the conversion resistor R.sub.0 and connected into an input end of the analog-to-digital converter (ADC). The other end of the conversion resistor R.sub.0 is grounded.

[0085] The temperature compensation circuit includes: a reference array, a current subtractor circuit and an I-V conversion resistor R.sub.1. The reference array includes two (one positive and one negative) columns of floating-gate devices. One column of floating-gate devices includes n P-type floating-gate devices MR.sub.1+-MR.sub.n+, and the other column of floating-gate devices includes n P-type floating-gate devices M.sub.R1−-M.sub.Rn−.

[0086] In the reference array, gates of the n P-type floating-gate devices MR.sub.1+-MR.sub.n+ are connected to a same fixed voltage V.sub.GS_REF, drains are connected to a same fixed voltage V.sub.DS_REF, and sources are connected with each other and to a fixed voltage V.sub.S and connected into a positive input end of the current subtractor circuit. In the reference array, gates of the n P-type floating-gate devices MR.sub.1−-MR.sub.n− are connected to the same fixed voltage V.sub.GS_REF, drains are connected to the same fixed voltage V.sub.DS_REF, and sources are connected with each other and to the fixed voltage V.sub.S and connected into a negative input end of the current subtractor circuit. An output end of the subtractor circuit is connected to one end of the resistor R.sub.1, and connected through a voltage buffer into a reference end of the ADC. The other end of the resistor R.sub.1 is grounded. The resistor R.sub.1 has same parameters as an I-V conversion resistor R.sub.0 in a readout circuit of the computing-in-memory array.

[0087] The disclosure further provides a temperature compensation method for a neural network computing-in-memory array, which is applicable to both the temperature compensation circuit for a computing-in-memory array composed of N-type floating-gate devices and the temperature compensation circuit for a computing-in-memory array composed of P-type floating-gate devices. The method includes the following steps:

[0088] Step I: Determine the number and position of reference arrays according to temperature field distribution of the computing-in-memory array in actual work.

[0089] If the computing-in-memory arrays in computing-in-memory equipment are located in the same temperature field, then one reference array is arranged in the temperature field. If the temperature field contains a plurality of computing-in-memory arrays, the reference array may be arranged in the middle of all the computing-in-memory arrays, as shown in FIG. 6.

[0090] If the computing-in-memory arrays in the computing-in-memory equipment are located in a plurality of temperature fields, then one reference array is arranged for each temperature field.

[0091] Step II: Calculate a gate voltage V.sub.GS_REF, a drain voltage V.sub.DSREF and a threshold voltage difference ΔV.sub.THP of floating-gate devices MR.sub.1+-MR.sub.n+ and MR.sub.1−-MR.sub.n− in the reference array according to values of a reference voltage and a resistor R.sub.1 required by the analog-to-digital converter.

[0092] Step III: Input the gate voltage V.sub.GS_REF and the drain voltage V.sub.DS_REF from the outside into gates and drains of the devices according to the calculation result of step II, and regulate a threshold voltage V.sub.TH of the devices by programming and erasing operations to obtain the threshold voltage difference ΔV.sub.THP calculated in step II.

[0093] Step IV: Enable the reference array to generate a reference current I.sub.REF according to the operation of step III; and convert the reference current I.sub.REF into the reference voltage V.sub.REF of the analog-to-digital converter by the resistor R.sub.1.

[0094] According to the temperature compensation method of the disclosure, optionally, the reference array and the computing-in-memory array are located in a same temperature field, and the current I.sub.REF generated after the operation of the reference array and a current I.sub.OUT generated after the operation of the computing-in-memory array change in a same proportion, so that a ratio of the input voltage to the reference voltage of the analog-to-digital converter before and after the temperature change remains unchanged, so as to ensure the correctness of output data of the analog-to-digital converter.

[0095] In a non-readout mode, the gate voltage V.sub.GS_REF of all the floating-gate devices in the reference array are connected to VDD, and at this time, no current is output from the reference array.

[0096] In a readout mode, the weights stored in the two columns of floating-gate devices in the computing-in-memory array are ΔV.sub.THP1-ΔV.sub.THPn, the weights stored in the two columns of floating-gate devices in the reference array are all ΔV.sub.THP_REF, and the computing-in-memory array obtains a corresponding output current I.sub.OUT through the subtractor circuit:

[00009]$I_{\mathrm{OUT}}={\mu }_P{C}_{\mathrm{ox}}\frac{W}{L}\left({\Delta V}_{\mathrm{THP}1}{V}_{DS1}+{\Delta V}_{\mathrm{THP}2}{V}_{DS2}+.Math.+{\Delta V}_{\mathrm{THPn}}{V}_{\mathrm{DSn}}\right),$

[0097] μp is the mobility of all the P-type floating-gate devices, C.sub.ox is the capacitance of the gate oxide layer, and W and L are respectively the width and length of the floating-gate device.

[0098] The output current I.sub.OUT is subjected to I-V conversion to obtain an output voltage:

[00010]$V_{\mathrm{OUT}}={\mu }_P{C}_{\mathrm{ox}}\frac{W}{L}{R}_0\left({\Delta V}_{\mathrm{THP}1}{V}_{DS1}+{\Delta V}_{\mathrm{THP}2}{V}_{DS2}+.Math.+{\Delta V}_{\mathrm{THPn}}{V}_{\mathrm{DSn}}\right);$

[0099] The output currents of the positive and negative columns of floating-gate devices in the reference array subjected to subtraction to obtain a reference current:

[00011]$I_{\mathrm{REF}}={n\mu }_P{C}_{\mathrm{ox}}\frac{W}{L}\left({\Delta V}_{\mathrm{THP}\_\mathrm{REF}}{V}_{\mathrm{DS}\_\mathrm{REF}}\right),$

[0100] The reference current is subjected to I-V conversion to obtain a reference voltage:

[00012]$V_{\mathrm{REF}}={n\mu }_P{C}_{\mathrm{ox}}\frac{W}{L}{R}_1\left({\Delta V}_{{\mathrm{THP}}_{-}\mathrm{REF}}{V}_{D{S}_{-}\mathrm{REF}}\right),$

[0101] Assuming that the ADC is an m-bit ADC, then the ADC outputs the digital result:

[00013]$\mathrm{CODE}=V_{\mathrm{OUT}}/V_{\mathrm{REF}}\times \left(2^m-1\right)=\left[\left({\Delta V}_{\mathrm{THN}1}{V}_{\mathrm{DS}1}+{\Delta V}_{\mathrm{THN}2}{V}_{\mathrm{DS}2}+.Math.+{\Delta V}_{\mathrm{THNn}}{V}_{\mathrm{DSn}}\right)/n\left({\Delta V}_{\mathrm{THP}\_\mathrm{REF}}{V}_{\mathrm{DS}\_\mathrm{REF}}\right)\right]\times \left(2^m-1\right),$

the formula does not contain any parameter related to temperature characteristic, so that the digital output of the ADC will not change with the temperature. That is, the temperature compensation method in this embodiment eliminates the temperature drift characteristic of the P-type floating-gate devices.

[0102] The temperature compensation method of this embodiment is essentially the same as that of Embodiment I and can obtain the same effects, which will not be repeated here.

Embodiment III

[0103] In order to prove the beneficial effects of the compensation method by eliminating the temperature drift characteristic of floating-gate devices in the computing-in-memory array according to the disclosure, a test circuit is built based on the fact that the linear region of an MOS transistor has the same characteristic as the linear region of the floating gate transistor. As shown in FIG. 5, for example, the computing-in-memory array includes 1 NMOS transistor M.sub.1+ and 1 NMOS transistor M.sub.1−. Correspondingly, a reference array in the temperature compensation circuit includes 1 NMOS transistor MR.sub.1+ and 1 NMOS transistor M.sub.R1− Drain voltages of M.sub.1+, M.sub.1−, MR.sub.1+ and MR.sub.1− are all V.sub.DS, source voltages are all connected to ground, and source voltages are respectively V.sub.GS1+, V.sub.GS1−, V.sub.GS2+ and V.sub.GS2−. Voltages of V.sub.DS, V.sub.GS1+, V.sub.GS1−, V.sub.GS2+ and V.sub.GS2− are regulated to ensure that all the NMOS transistors are all in the linear region. All the NMOS transistors have a same width W and a same length L, and the mobility is μ.

[0104] Currents of the NMOS transistors M.sub.1+ and M1.sub.− pass through a subtractor circuit to obtain an output current

[00014]$I_{\mathrm{OUT}}={\mu C}_{\mathrm{ox}}\frac{W}{L}\left(V_{\mathrm{GS}1+}-V_{\mathrm{GS}1-}\right)V_{DS},{\mu C}_{\mathrm{ox}}\frac{W}{L}\left(V_{\mathrm{GS}1+}-V_{\mathrm{GS}1-}\right)$

represents the weight of the computing-in-memory array, and V.sub.DS represents the input data of the computing-in-memory array. Then, the output current passes through a resistor R to obtain an ADC input voltage

[00015]$V_{\mathrm{OUT}}={\mu C}_{\mathrm{ox}}\frac{W}{L}R\left(V_{\mathrm{GS}1+}-V_{\mathrm{GS}1-}\right)V_{\mathrm{DS}}.$

[0105] In this embodiment, there are two methods of generating the reference voltage V.sub.REF of the ADC. Method (1):

[0106] According to the method of generating the reference voltage V.sub.REF in the disclosure, currents of the NMOS transistors MR.sub.1+ and MR.sub.1− pass through a subtractor circuit and a resistor R to obtain

[00016]$V_{\mathrm{REF}}={\mu C}_{\mathrm{ox}}\frac{W}{L}R\left(V_{\mathrm{GS}2+}-V_{\mathrm{GS}2-}\right)V_{\mathrm{DS}},{\mu C}_{\mathrm{ox}}\frac{W}{L}\left(V_{\mathrm{GS}1+}-V_{\mathrm{GS}1-}\right)$

represents the weight of the reference array, and V.sub.DS represents the input data of the reference array.

[0107] Method (2): A constant current source I.sub.DC and a resistor R are used to generate an ADC reference voltage V.sub.REF, which is similar to the traditional method of directly inputting the reference voltage from the outside. Finally, an ideal DAC having the same range as the ADC is added after the ADC, so as to convert the digital output of the ADC into an analog output V.sub.OUT′. The V.sub.OUT′ is compared with the V.sub.OUT. The closer V.sub.OUT′ to V.sub.OUT, the less the output of the ADC is affected by temperature. In this way, the beneficial effects of the temperature compensation method in the disclosure can be exhibited more visually.

[0108] In this embodiment, transient-state simulation of an analog circuit is performed by virtuoso software of Cadence company. V.sub.OUT and V.sub.OUT are compared at 25° C. (normal temperature), 0° C. (low temperature) and 100° C. (high temperature) respectively. At 25° C., the parameters R, (V.sub.GS2+−−V.sub.GS2−), V.sub.DS and IDC are regulated, so that Methods (1) and (2) generate the same reference voltage, and V.sub.OUT′ at this time serves as the theoretical output. These parameters remain unchanged at other temperatures.

[0109] The simulation result at 25° C. is shown in FIG. 6. The horizontal axis is time (T), and the vertical axis is voltage (V). In the diagram, mark point M11 is the ADC input voltage V.sub.OUT=145.3 mV, mark point M12 is the reference voltage generated by the reference array, mark point M9 is the output of the DAC when Method (1) is used, and mark point M10 is the output of the DAC when Method (2) is used. As can be seen, at this time, the output V.sub.OUT′ in Method (1) and the output V.sub.OUT in Method (2) are the same, i.e., 144.1 mV.

[0110] The simulation result at 0° C. is shown in FIG. 7. The horizontal axis is time (T), and the vertical axis is voltage (V). In the diagram, mark point M15 is the ADC input voltage, mark point M16 is the reference voltage generated by the reference array, mark point M13 is the output voltage of the DAC when Method (1) is used, and mark point M14 is the output voltage of the DAC when Method (2) is used. As can be seen, at this time, due to the temperature drift characteristic of mobility, the ADC input voltage V.sub.OUT has seriously deviated to 181.4 mV. When Method (1) is used, the reference voltage deviates to 186.8 mV accordingly. At this time, the output voltage V.sub.OUT′ of the DAC is 144.1 mV, which indicates that the output voltage of the ADC is not affected by the temperature change. When Method (2) is used, the output voltage V.sub.OUT′ of the DAC has seriously deviated to 180.5 mV, which indicates that the output voltage of the ADC is affected by the temperature change.

[0111] The simulation result at 100° C. is shown in FIG. 8. The horizontal axis is time (T), and the vertical axis is voltage (V). In the diagram, mark point M24 is the input voltage of the ADC, mark point M23 is the reference voltage generated by the reference array, mark point M21 is the output voltage of the DAC when Method (1) is used, and mark point M22 is the output voltage of the DAC when Method (2) is used. As can be seen, at this time, due to the temperature drift characteristic of mobility, the input voltage V.sub.OUT of the ADC has seriously deviated to 75.8 mV. When Method (1) is used, the reference voltage deviates to 78.1 mV accordingly. At this time, the output voltage V.sub.OUT′ of the DAC is 125.4 mV. When Method (2) is used, the output voltage V.sub.OUT′ of the DAC has seriously deviated to 73.8 mV, which indicates that the method of generating the reference voltage by the reference array effectively compensates for the temperature drift characteristic of the mobility.

[0112] Analysis on the simulation results: Before the temperature compensation, at 0° C. to 100° C., the temperature coefficient of the digital output of the ADC is up to 0.6%/° C.; and after the temperature compensation, at 0° C. to 100° C., the temperature coefficient of the output of the ADC is down to 0.13%/° C.

[0113] Based on the above, the temperature compensation circuit and method by eliminating the temperature drift characteristic of the devices of the computing-in-memory array according to the disclosure have good effects.

[0114] Part of steps in the embodiments of the disclosure can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disk or a hard disk.

[0115] The above description is only the preferred embodiments of the disclosure and is not intended to limit the disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the disclosure should be included within the protection scope of the disclosure.