Pulse density modulation method and pulse density value signal conversion circuit

Abstract

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

Claims

1. A pulse density modulation method, comprising the following steps: S01, obtaining a number of bits n of a binary density value d, wherein a number of bits of a counter is set as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; S03, determining whether corresponding bits are equal wherein if a j.sup.th bit counted from left to right of the binary density value d is 1, then a bit of a signal output in a period is 1; if the j.sup.th bit counted from left to right of the binary density value d is 0, then the bit of the signal output in the period is 0; S04, adding the current value i of the counter by 1, proceeding to a next period, and turning to the S02.

2. The pulse density modulation method according to claim 1, wherein in the S02, an instruction in a CPU instruction set is configured to directly search and obtain the number of bits j of the rightmost 1 of the current value i of the counter counted from right to left; and in the S03, a bit test instruction is configured to check whether the j.sup.th bit counted from left to right of the binary density value d is 1.

3. The pulse density modulation method according to claim 1, wherein in the S02, searching for the rightmost 1 is realized by a loop test from left to right or a loop test from right to left; and in the S03, the binary density value d is shifted j1 bits to the left by a first shift instruction and a highest bit is retained, if a first result is 1, then the corresponding bits are equal, if the first result is 0, then the corresponding bits are not equal; or the binary density value d is shifted n-j bits to the right by a second shift instruction and a lowest bit is retained, if a second result is 1, then the corresponding bits are equal, if the second result is 0, then the corresponding bits are not equal.

4. The pulse density modulation method according to claim 1, wherein the S02 and the S03 are replaced by S11-S14 as follows: S11, inverting the binary density value d according to a bit sequence to obtain D; S12, subtracting the current value i of the counter by one, and then performing an exclusive-OR (XOR) with an original i to obtain k; S13, adding k by 1, and shifting one bit to the right to obtain m; and S14, performing an AND operation on m and D, wherein if a result is equal to m, then the bit of the signal output in the period is 1; if the result is not equal to m, the bit of the signal output in the period is 0.

5. The pulse density modulation method according to claim 1, wherein when the initial value of the counter is 0, a first bit of an output signal is set to 0 or 1.

6. A pulse density modulation method, wherein a period of a pulse signal is s, and a q.sup.th bit of an output signal is determined by the following steps: A01, multiplying a density value d with a density value q to obtain a product, dividing the product by s to obtain a quotient, and taking an integer part from the quotient as h; A02, determining whether h and a pulse count value are the same, wherein if h and the pulse count value are the same, the q.sup.th bit of the output signal is 0, if not, proceed to the A03; and A03, setting the CO bit of the output signal as 1, and setting the pulse count value as h; wherein a number of bits of the output signal is s, a value range of q is 1 to s, an initial value of the pulse count value is 0.

7. A pulse density value signal conversion circuit, comprising a search module and a comparison module, wherein the search module comprises a low-bit test module and a conversion module, an input terminal of the low-bit test module is connected to a counter, an output terminal of the low-bit test module is connected to the conversion module, and an output terminal of the conversion module is connected to an input terminal of the comparison module, the input terminal of the comparison module is further connected to a pulse density value signal, and an output terminal of the comparison module is an output terminal of the pulse density value signal conversion circuit; the low-bit test module comprises n1 signal lines, n count input terminals and n2 OR gates, and the conversion module comprises n1 AND gates, n1 NOT gates and n output terminals, wherein n is a number of bits of the counter, the n1 signal lines are marked as s[1] to s[n1] in sequence, the n count input terminals are marked as i[1] to i[n] in sequence and are respectively connected to 1.sup.st to n.sup.th bits of the counter, and the n output terminals are marked as o[1] to o[n] in sequence; the count input terminal i[1] is directly connected to the output terminal o[1] and the signal line s [1], the signal line s [1] is connected to a first input terminal of a first AND gate through a NOT gate, a second input terminal of the first AND gate is connected to the count input terminal i[2], and an output terminal of the first AND gate is connected to the output terminal o[2]; when j2, an output terminal of the (j1).sup.th OR gate is connected to the signal line s[j], the signal line s[j] is connected to a first input terminal of the j.sup.th AND gate through the NOT gate, a second input terminal of the j.sup.th AND gate is connected to the count input terminal i[j+1]; a first input terminal of the (j1).sup.th OR gate is connected to the output terminal o[j], and a second input terminal of the (j1).sup.th OR gate is connected to the signal line s[j1].

8. The pulse density value signal conversion circuit according to claim 7, wherein the comparison module comprises n pulse density value input terminals, n AND gates, and an OR gate having n input terminals, the pulse density value input terminals are marked as d[1] to d[n] in sequence and are respectively connected to 1.sup.st to n.sup.th bits of the pulse density value signal; a first input terminal of the k AND gate is connected to the output terminal o[k] of the search module, a second input terminal of the k.sup.th AND gate is connected to the pulse density value input terminal d[n+1k], an output terminal of the k.sup.th AND gate is connected to the k.sup.th input terminal of the OR gate having n input terminals; an output of the OR gate having n input terminals is a total output terminal of the pulse density value signal conversion circuit.

9. A pulse density value signal conversion circuit, comprising a search module and a comparison module, wherein the search module comprises a low-bit test module and a conversion module, an input terminal of the low-bit test module is connected to a counter, an output terminal of the low-bit test module is connected to the conversion module, and an output terminal of the conversion module is connected to an input terminal of the comparison module, the input terminal of the comparison module is further connected to a pulse density value signal, and an output terminal of the comparison module is an output terminal of the pulse density value signal conversion circuit; the low-bit test module comprises n1 signal lines, n count input terminals and n2 OR gates, and the conversion module comprises n1 AND gates, n1 NOT gates and n output terminals, wherein n is the number of bits of the counter, the n1 signal lines are marked as s[1] to s[n1] in sequence, the n count input terminals are marked as i[1] to i[n] in sequence and are respectively connected to 1.sup.st to n.sup.th bits of the counter, and the n output terminals are marked as o[1] to o[n] in sequence; the count input terminal i[1] is directly connected to the output terminal o[1] and the signal line s[1], the signal line s[1] is connected to a first input terminal of a first AND gate through a NOT gate, a second input terminal of the first AND gate is connected to the count input terminal i[2], and an output terminal of the first AND gate is connected to the output terminal o[2]; when j2, an output terminal of the (j1).sup.th OR gate is connected to the signal line s[j], the signal line s[j] is connected to a first input terminal of the j.sup.th AND gate through the NOT gate, a second input terminal of the j.sup.th AND gate is connected to the count input terminal i[j+1]; a first input terminal of the (j1).sup.th OR gate is connected to the count output terminal i[j], and a second input terminal of the (j1).sup.th OR gate is connected to the signal line s[j1].

10. The pulse density value signal conversion circuit according to claim 9, wherein the comparison module comprises n pulse density value input terminals, n AND gates, and an OR gate having n input terminals, the n pulse density value input terminals are marked as d[1] to d[n] in sequence and are respectively connected to 1.sup.st to n.sup.th bits of the pulse density value signal; a first input terminal of the k AND gate is connected to the output terminal o[k] of the search module, a second input terminal of the k.sup.th AND gate is connected to the pulse density value input terminal d[n+1k], an output terminal of the k.sup.th AND gate is connected to the k.sup.th input terminal of the OR gate having n input terminals; an output of the OR gate having n input terminals is a total output of the pulse density value signal conversion circuit.

11. A pulse density value signal conversion circuit, comprising a search module and a comparison module, wherein the search module comprises a low-bit test module and a conversion module, an input terminal of the low-bit test module is connected to a counter, an output terminal of the low-bit test module is connected to the conversion module, and an output terminal of the conversion module is connected to an input terminal of the comparison module, the input terminal of the comparison module is further connected to a pulse density value signal, and an output terminal of the comparison module is an output terminal of the pulse density value signal conversion circuit; the low-bit test module comprises n1 signal lines, n count input terminals and n2 OR gates, and the conversion module comprises n1 AND gates, n1 NOT gates and n output terminals, wherein n is the number of bits of the counter, the n1 signal lines are marked as s[1] to s[n1] in sequence, the n count input terminals are marked as i[1] to i[n] in sequence and are respectively connected to l.sup.st to n.sup.th bits of the counter, and the n output terminals are marked as o[1] to o[n] in sequence; the j.sup.th OR gate has j+1 input terminals; the count input terminal i[1] is directly connected to the output terminal o[1] and the signal line s[1], the signal line s[1] is connected to a first input terminal of a first AND gate through a NOT gate, a second input terminal of the first AND gate is connected to the count input terminal i[2], and an output terminal of the first AND gate is connected to the output terminal o[2]; when j2, an output terminal of the (j1).sup.th OR gate is connected to the signal line s[j], the signal line s[j] is connected to a first input terminal of the j.sup.th AND gate through the NOT gate, a second input terminal of the j.sup.th AND gate is connected to the count input terminal i[j+1]; the g.sup.th input terminal of the (j1).sup.th OR gate is connected to the count input terminal i[g].

12. The pulse density value signal conversion circuit according to claim 11, wherein the comparison module comprises n pulse density value input terminals, n AND gates, and an OR gate having n input terminals, the n pulse density value input terminals are marked as d[1] to d[n] in sequence and respectively connected to 1.sup.st to n.sup.th bits of the pulse signal density value; a first input terminal of the k.sup.th AND gate is connected to the output terminal o[k] of the search module, a second input terminal of the k.sup.th AND gate is connected to the signal input terminal d[n+1k], an output terminal of the k.sup.th AND gate is connected to the k.sup.th input terminal of the OR gate having n input terminals; an output of the OR gate having n input terminals is a total output terminal of the pulse density value signal conversion circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a flow chart of the present disclosure;

(2) FIG. 2 is a first circuit diagram of the present disclosure;

(3) FIG. 3 is a second circuit diagram of the present disclosure;

(4) FIG. 4 is a third circuit diagram of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(5) The technical solutions of the present disclosure will be further specifically described hereinafter with reference to the embodiments and drawings.

(6) Embodiment 1: a pulse density modulation method of the present embodiment, as shown in FIG. 1, includes the following steps of:

(7) S01, obtaining a number of bits n of a binary density value d, and setting a number of bits of a counter as n, wherein an initial value of the counter is 0 or 1; a number in the counter is a binary number;

(8) S02, searching for the rightmost 1: obtaining a number of bits j of a rightmost 1 of a current value i of the counter counted from right to left; wherein the minimum value of j is 1;

(9) S03, determining whether corresponding bits are equal: if the j.sup.th bit of d counted from left to right is 1, then a bit of a signal output in the period is 1; if the j.sup.th bit of d counted from left to right is 0, then a bit of the signal output in the period is 0;
S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

(10) A sequence formed by bits of signals output in various periods is an output signal, which is an output of the present solution. Each binary density value d corresponds to an output signal. The first bit of the output signal is the leftmost bit.

(11) When the initial value of i is set as 0, the number of bits of the output signal is 2.sup.n. When the initial value of i is 1, the number of bits of the output signal is 2.sup.n1. In the situation, a pulse density range is 0 (i.e. 0/2.sup.n1) to 1 (i.e. 2.sup.n1/2.sup.n1), and either an output signal in which each bit is 0, or an output signal in which each bit is 1 can be generated.

(12) After the value i of the counter reaches an upper limit, the counter returns to the initial value and a next period starts, or the process ends.

(13) The solution is applicable to a DC-DC converter or a digital-to-analog converter, the binary density value d is an input signal of the DC-DC converter or a digital signal generated by a front end of the digital-to-analog converter, after an output signal is obtained, the DC-DC converter or the digital-to-analog converter modulates an output voltage according to the output signal.

(14) The solution is mainly applicable to voltage control. For example, the DC-DC converter can control the output voltage by controlling a control signal duty cycle of a switch tube, and PWM is the most commonly employed of all the control methods, for example, the control signal is 11110000, which will become a dispersed 10101010 or other signal by using the present method, so that the fluctuation of the output voltage will be smaller.

(15) In the step S02, searching for the rightmost 1 is specifically as follows. An instruction in a CPU instruction set is used to directly search and obtain a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; in the step S03, determining whether the corresponding bits are equal is specifically as follows. A bit test instruction is used to check whether the j.sup.th bit of the density value d counted from left to right is 1.

(16) For example, the binary density valued is 0011 (2 in decimal), the number of bits n is 4, the number of bits of the counter is set as 4, the initial value is 0, the rightmost 1 cannot be searched, the 1.sup.st (i=0, i+1=1, wherein i is converted to decimal calculation) bit of the output signal is 0, and turning to the step S05, the value i of the counter is added by 1 to 0001 (1 in decimal), the number of bits counted from right to left of the rightmost 1 is 1, and the first bit counted from left to right of the density value d is 0, then the 2.sup.nd (i+1=2) bit of the output signal is 0; the value i of the counter is further added by 1 and turns to the step S02. It can be seen from the calculation that the 1.sup.st bit, the 2.sup.nd bit, the 3.sup.rd bit and the 4.sup.th bit of the output signal are all 0. When calculating the 5.sup.th bit, i is 0100 (4 in decimal), the rightmost 1 is the 3.sup.rd bit (j=3), the 3.sup.rd bit of the density value d is also 1, and then the 5.sup.th bit of the output signal is 1. Finally, an output signal of 0000 1000 0000 1000 is obtained when the binary density value d is 0011. Compared with pulse modulation (output signal is 1100 0000 0000 0000) or traditional density modulation, the output signal of the present solution has small fluctuation and good uniformity.

(17) When the initial value of i is 0, the 1.sup.st bit of the output signal is set as 0 or 1. Namely, when the initial value of i is 0, the bit of the signal output in the first period is fixed to be 0 or fixed to be 1.

(18) When the 1.sup.st bit of each output signal is set as 0, the density value range is 0 (i.e. 0/2.sup.n) to (2.sup.n1)/2.sup.n, a signal in which each bit is 0 can be generated, and a signal in which each bit is 1 cannot be generated. When the 1.sup.st bit of each output signal is set as 1, the density value range is 1/2n to 1 (i.e. 2.sup.n/2.sup.n), the uniformity will be slightly lower than that in the former situation, and an output signal in which each bit is 0 cannot be generated, but an output signal in which each bit is 1 can be generated. Users can choose according to actual needs.

(19) In the step S12, when i is set to the initial value, each bit of the value of i1 is 1, e.g. n=4, then i1=1111.

(20) n=4, the initial value of i is 0, when the 1.sup.st bit of the output signal is set as 0, according to different density values, the output signals are arranged in sequence as follows:

(21) 0000 0000 0000 0000 Description: density value 0000 has no 1, therefore the output is all 0;

(22) 0000 0000 1000 0000 Description: density value 0001, the 9.sup.th bit of the output signal is 1, the value of the counter is 1000, the rightmost 1 is the 4.sup.th bit counted from right to left, the 4.sup.th bit counted from left to right of the density value is also 1, so the 9.sup.th bit is 1, and other bits do not accord with the requirement, therefore are 0;
0000 1000 0000 1000 Description: density value 0010, the 5.sup.th bit and the 13.sup.th bit of the output signal are 1, the values of the counter are 0100 and 1100 respectively, their rightmost 1 are both the 3.sup.rd bit, and the 3.sup.rd bit counted from left to right of the density value is 1, therefore these two bits output 1;
0000 1000 1000 1000 Description: density value 0011, the rest can be done in the same manner;
0010 0010 0010 0010
0010 0010 1010 0010
0010 1010 0010 1010
0010 1010 1010 1010
0101 0101 0101 0101
0101 0101 1101 0101
0101 1101 0101 1101
0101 1101 1101 1101
0111 0111 0111 0111
0111 0111 1111 0111
0111 1111 0111 1111
0111 1111 1111 1111
n=4, the initial value of i is 0, when the 1.sup.st bit of the output signal is set as 1, the output signals are in sequence as follows:
1000 0000 0000 0000
1000 0000 1000 0000
1000 1000 0000 1000
1000 1000 1000 1000
1010 0010 0010 0010
1010 0010 1010 0010
1010 1010 0010 1010
1010 1010 1010 1010
1101 0101 0101 0101
1101 0101 1101 0101
1101 1101 0101 1101
1101 1101 1101 1101
1111 0111 0111 0111
1111 0111 1111 0111
1111 1111 0111 1111
1111 1111 1111 1111;
n=4, when the initial value of i is 1, the output signals are in sequence as follows:
000 0000 0000 0000
000 0000 1000 0000
000 1000 0000 1000
000 1000 1000 1000
010 0010 0010 0010
010 0010 1010 0010
010 1010 0010 1010
010 1010 1010 1010
101 0101 0101 0101
101 0101 1101 0101
101 1101 0101 1101
101 1101 1101 1101
111 0111 0111 0111
111 0111 1111 0111
111 1111 0111 1111
111 1111 1111 1111.

(23) Embodiment 2: a pulse density modulation method of the present embodiment includes the following steps of:

(24) S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, wherein an initial value of the counter is 0 or 1;

(25) S02, searching for the rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left;

(26) S03, determining whether corresponding bits are equal: if the j.sup.th bit counted from left to right of d is 1, then the i.sup.th bit of the output signal is 1; if the j.sup.th bit counted from left to right of d is 0, then the i.sup.th bit of the output signal is 0;

(27) S04, determining whether the value of the counter reaches an upper limit, if yes, then ending, otherwise proceeding to step S05;

(28) S05, adding the value i of the counter by 1, and turning to step S02.

(29) In step S02, searching for the rightmost 1 is obtained by a loop test from left to right or from right to left;

(30) in the step S03, determining whether the corresponding bits are equal is specifically as follows. d is shifted j1 bits to the left by a shift instruction and a highest bit is retained, if a result is 1, then the corresponding bits are equal, if the result is 0, then the corresponding bits are not equal; or d is shifted nj bits to the right by the shift instruction and a lowest bit is retained, if a result is 1, then the corresponding bits are equal, if the result is 0, then the corresponding bits are not equal.

(31) For example, d is 0110, i is 0100, then j is 3, and then d is shifted 3-1 bits to the left, and turns into 1000, the highest bit is retained, if it is 1, then the (i+1).sup.th bit outputs 1. It is also possible to shift d by nj bits to the right to turn into 0011, and then the lowest bit is retained, if it is 1 then the (i+1).sup.th bit outputs 1, and if it is 0 then the (i+1).sup.th bit outputs 0. The rest of the contents are the same as that in embodiment 1.

(32) Embodiment 3: a pulse density modulation method of the present embodiment includes the following steps of:

(33) S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, wherein an initial value of the counter is 0 or 1;

(34) S02, searching for the rightmost 1 and determining whether corresponding bits are equal;

(35) S03, determining whether the value of the counter reaches an upper limit, if yes, then ending, otherwise proceeding to step S04;

(36) S04, adding the value i of the counter by 1, and turning to the step S02.

(37) The step S02 is specifically as follows.

(38) S11, the density value d is inverted in bit sequence to obtain D; the inversion in bit sequence herein means putting the original 1.sup.st bit to the last bit, the original 2.sup.nd bit to the penultimate bit, and so on; d is set to 0011, the obtained D is 1100; n is 4, and i is set to 0100;
S12, the count value i is subtracted by one, and then XORed with the original i to obtain k; when i is 0, the (i+1).sup.th bit of the output signal is set as 0 or 1; 01001=0011, 0011 is XORed with 0100 to obtain 0111;
S13, k is added by 1, and then shift one bit to the right to obtain m; 0111+1=1000, and shift one bit to the right to obtain 0100;
S14, an AND operation is performed on m and D, if the result is equal to m, then the (i+1).sup.th bit of the output signal is 1; if the result is not equal to m, then the (i+1).sup.th bit of the output signal is 0. An AND operation is performed on 0100 and 1100, 0100 is obtained, the same as m, the 0101.sup.th (5 in decimal) bit of the output signal outputs 1.

(39) For another example, if d is 0001, i is 1000, then D is 1000, i1 is 0111, and 0111 is XORed with 1000 to obtain k as 1111, k+1=10000, and shift one bit to the right to obtain m as 1000. The AND operation is performed on 1000 and 1000 to obtain 1000, which is equal to m, and the 9.sup.th bit of the output signal is 1.

(40) The rest of the contents are the same as that in embodiment 1.

(41) Embodiment 4: a pulse density modulation method, wherein the period of the pulse signal is s, and the q.sup.th bit of the output signal is determined by the following manner:

(42) A01, a density value d is multiplied by a density value q, an obtained product is divided by s, and an integer part taken from an obtained quotient is h;

(43) A02, whether h and a pulse count value are the same is determined, if the same, then the q.sup.th bit of the output signal is 0, if not, then proceed to the step A03;

(44) A03, the q.sup.th bit of the output signal is set to 1, and the pulse count value is set to h; the number of bits of the output signal is s, i.e., a value range of q is 1 to s; an initial value of the pulse count value is 0.

(45) For example, s is 16, d is 3, the initial value of the pulse counter is 0, the 1.sup.st bit to the 5.sup.th bit of the output signal, 3q/16, the integer part is 0, which is equal to the value of the pulse counter, and the output is 0; the 6.sup.th bit, the integer part of 3q/16 is 1, which is not equal to the value of the pulse counter, the output is 1, and the value of the pulse counter is set to 1; the 7.sup.th-10.sup.th bits of the output signal all output 0; the 11.sup.th bit, the integer part of 3q/16 is 2, which is not equal to the value of the pulse counter, the output is 1, and the value of the pulse counter is set to 2; and so on.

(46) If the number of bits of the output signal is recorded from 0 to 2.sup.n1, i.e. s is still 2.sup.n, then the value of q is 0 to 2.sup.n1, and the formula becomes dq/(s1), and the other steps are the same. If s is not a power of 2 in a system, it can be considered as taking a part of the integrated version, and the retained part is handled in the same way as described above.

(47) In the present solution, the number of bits of the output signal begins from the 1.sup.st bit, and in actual programming, it tends to begin from the 0 bit, which is a conventional translation and still falls within the scope defined by the claims of the present application. Similarly, density ranges of 0 to (2.sup.n1) and 0 to 2.sup.n also fall within the scope defined by the claims.

(48) Embodiment 5: a pulse density value signal conversion circuit, as shown in FIG. 2, includes a search module and a comparison module, and the search module includes a low-bit test module and a conversion module, an input terminal of the low-bit test module is connected to a counter, an output terminal of the low-bit test module is connected to the conversion module, and an output terminal of the conversion module is connected to an input terminal of the comparison module, the input terminal of the comparison module is further connected to a pulse density value signal, and an output terminal of the comparison module is an output terminal of the pulse density value signal conversion circuit; the low-bit test module includes n1 signal lines, n count input terminals and n2 OR gates, and the conversion module includes n1 AND gates, n1 NOT gates and n output terminals, wherein n is the number of bits of the counter, the signal lines are marked as s[1] to s[n1] in sequence, the count input terminals are marked as i[1] to i[n] in sequence and are respectively connected to the 1.sup.st bit to n.sup.th bit of the counter, and the output terminals are marked as o[1] to o[n] in sequence;

(49) the count input terminal i[1] is directly connected to the output terminal o[1] and the signal line s[1], the signal line s[1] is connected to a first input terminal of a first AND gate through a NOT gate, a second input terminal of the first AND gate is connected to the count input terminal i[2], and an output terminal of the first AND gate is connected to the output terminal o[2];
when j2, an output terminal of the (j1).sup.th OR gate is connected to the signal line s[j], the signal line s[j] is connected to a first input terminal of the j.sup.th AND gate through a NOT gate, a second input terminal of the j.sup.th AND gate is connected to the count input terminal i[j+1]; a first input terminal of the (j1).sup.th OR gate is connected to the output terminal o[j], and a second input terminal of the (j1).sup.th OR gate is connected to the signal line s[j1].

(50) The comparison module includes n pulse density value input terminals, n AND gates, and an OR gate having n input terminals, the pulse density value input terminals are marked as d[1] to d[n] in sequence and are respectively connected to the 1.sup.st bit to the n.sup.th bit of the pulse density value signal;

(51) a first input terminal of the k.sup.th AND gate is connected to the output terminal o[k] of the search module, a second input terminal of the k.sup.th AND gate is connected to the input terminal d[n+1k] of the pulse density value, an output terminal of the k.sup.th AND gate is connected to the k.sup.th input terminal of the OR gate having n input terminals; an output of the OR gate having n input terminals is a total output terminal of the pulse signal conversion circuit. The OR gate having n input terminals can be implemented by stacking a number of 2 input terminals OR gates.

(52) The function of the search module is to find the position of the lowest-bit 1 of the counter i, and then zero clearing is performed on all except the bit; the low-bit test module detects whether there is 1 on each bit lower than it, and the output of the OR gate is caused by the conversion module to pass through the NOT gate and is input to the AND gate together with i to obtain the output o, and the output signal is finally obtained by using the comparison module.

(53) Embodiment 6: a pulse density value signal conversion circuit, as shown in FIG. 3, includes a search module and a comparison module, and the search module includes a low-bit test module and a conversion module, an input terminal of the low-bit test module is connected to a counter, an output terminal of the low-bit test module is connected to the conversion module, and an output terminal of the conversion module is connected to an input terminal of the comparison module, the input terminal of the comparison module is further connected to a pulse density value signal, and an output terminal of the comparison module is an output terminal of the pulse density value signal conversion circuit; the low-bit test module includes n1 signal lines, n count input terminals and n2 OR gates, and the conversion module includes n1 AND gates, n1 NOT gates and n output terminals, wherein n is the number of bits of the counter, the signal lines are marked as s[1] to s[n1] in sequence, the count input terminals are marked as i[1] to i[n] in sequence and are respectively connected to the 1.sup.st to n.sup.th bits of the counter, and the output terminals are marked as o[1] to o[n] in sequence;

(54) the count input terminal i[1] is directly connected to the output terminal o[1] and the signal line s[1], the signal line s[1] is connected to a first input terminal of a first AND gate through a NOT gate, a second input terminal of the first AND gate is connected to the count input terminal i[2], and an output terminal of the first AND gate is connected to the output terminal o[2];
when j2, an output terminal of the (j1).sup.th OR gate is connected to the signal line s[j], the signal line s[j] is connected to a first input terminal of the j.sup.th AND gate through a NOT gate, a second input terminal of the j.sup.th AND gate is connected to the count input terminal i[j+1]; a first input terminal of the (j1).sup.th OR gate is connected to the count output terminal i[j], and a second input terminal of the (j1).sup.th OR gate is connected to the signal line s[j1].

(55) The structure of the comparison module is the same as that of the embodiment 1. The function of each module is the same as that of the embodiment 5.

(56) Embodiment 7: a pulse density value signal conversion circuit, as shown in FIG. 4, includes a search module and a comparison module, and the search module includes a low-bit test module and a conversion module, an input terminal of the low-bit test module is connected to a counter, an output terminal of the low-bit test module is connected to the conversion module, and an output terminal of the conversion module is connected to an input terminal of the comparison module, the input terminal of the comparison module is further connected to a pulse density value signal, and an output terminal of the comparison module is an output terminal of the pulse density value signal conversion circuit; the low-bit test module includes n1 signal lines, n count input terminals and n2 OR gates, and the conversion module includes n1 AND gates, n1 NOT gates and n output terminals, wherein n is the number of bits of the counter, the signal lines are marked as s[1] to s[n1] in sequence, the count input terminals are marked as i[1] to i[n] in sequence and are respectively connected to the 1.sup.st to n.sup.th bits of the counter, and the output terminals are marked as o[1] to o[n] in sequence; the j.sup.th OR gate has j+1 input terminals; the count input terminal i[1] is directly connected to the output terminal o[1] and the signal line s[1], the signal line s[1] is connected to a first input terminal of a first AND gate through a NOT gate, a second input terminal of the first AND gate is connected to the count input terminal i[2], and an output terminal of the first AND gate is connected to the output terminal o[2]; when j2, an output terminal of the (j1).sup.th OR gate is connected to the signal line s[j], the signal line s[j] is connected to a first input terminal of the j.sup.th AND gate through a NOT gate, a second input terminal of the j.sup.th AND gate is connected to the count input terminal i[j+1]; the g.sup.th input terminal of the (j1).sup.th OR gate is connected to the count input terminal i[g].

(57) The structure of the comparison module is the same as that of the embodiment 1. The function of each module is the same as that of the embodiment 5.

(58) The present solution is used for converting a pulse density value signal to obtain a pulse density value signal with a preferable uniformity. The input of the present solution is a binary signal representing the pulse density value, and the output is a pulse signal after a density modulation, the current converted sequence number is stored in the counter, and the sequence number is added by 1 for each conversion.

(59) The specific embodiments described herein are merely illustrative to the spirit of the present disclosure. The persons skilled in the art can make various modifications or supplements to the specific embodiments described or make substitutions in a similar manner, without departing from the spirit of the present disclosure or exceeding the scope defined by the appended claims.

(60) Although the terminologies including counter, number of bits, gate circuit and the like are used more often herein, the possibility of using other terminologies is not excluded. These terminologies are only intended to describe and illustrate the essence of the present disclosure more conveniently; illustrating them as any additional limit is disobedient with the spirit of the present disclosure.