Low supply voltage ring oscillator and method thereof

Abstract

A circuit includes multiple stages cascaded in a ring topology such that each stage has a preceding stage, a succeeding stage, an alternate-preceding stage, and an alternate-succeeding stage. Each stage includes a MOS transistor of a first type, a MOS transistor of a second type and a resistor. The MOS transistor of a first type receives a first input that is output from the preceding stage, and outputs a second output to the alternate-preceding stage. The MOS transistor of a second type receives a second input that is output from the alternate-succeeding stage, and outputs a first output to the succeeding stage. The resistor provides coupling and level-shifting between the first output and the second output.

Claims

1. A circuit comprising: a first MOS (metal oxide semiconductor) transistor of a first type configured to receive a first voltage from a first node and output a second voltage to a second node; a first resistor inserted between the second node and a third node; a second MOS transistor of the first type configured to receive a third voltage from the third node and output a fourth voltage to fourth node; a second resistor inserted between the fourth node and a fifth node; a third MOS transistor of the first type configured to receive a fifth voltage from the fifth node and output a sixth voltage to a sixth node; a third resistor inserted between the sixth node and a seventh node; a fourth MOS transistor of the first type configured to receive a seventh voltage from the seventh node and output an eighth voltage to an eighth node; a fourth resistor inserted between the eighth node and the first node; a first MOS transistor of a second type configured to receive the sixth voltage from the sixth node and output the third voltage to the third node; a second MOS transistor of the second type configured to receive the eighth voltage from the eighth node and output the fifth voltage to the fifth node; a third MOS transistor of the second type configured to receive the second voltage from the second node and output the seventh voltage to the seventh node; and a fourth MOS transistor of the second type configured to receive the fourth voltage from the fourth node and output the first voltage to the first node.

2. The circuit of claim 1, wherein every MOS transistor of the first type is an NMOS (n-channel metal oxide semiconductor) transistor, and every MOS transistor of the second type is a PMOS (p-channel metal oxide semiconductor) transistor.

3. The circuit of claim 1, wherein every MOS transistor of the first type is a PMOS (p-channel metal oxide semiconductor) transistor, and every MOS transistor of the second type is an NMOS (n-channel metal oxide semiconductor) transistor.

4. A circuit comprising a plurality of stages cascaded in a ring topology such that each stage has a preceding stage, a succeeding stage, an alternate-preceding stage, and an alternate-succeeding stage, wherein each stage comprises: a MOS (metal oxide semiconductor) transistor of a first type configured to receives a first input that is output from the preceding stage and output a second output to the alternate-preceding stage; a MOS transistor of a second type configured to receive a second input that is output from the alternate-succeeding stage and outputs a first output to the succeeding stage; and a resistor configured to provide coupling and level-shifting between the first output and the second output.

5. The circuit of claim 4, wherein the MOS transistor of the first type is an NMOS (n-channel metal oxide semiconductor) transistor, and the MOS transistor of the second type is a PMOS (p-channel metal oxide semiconductor) transistor.

6. The circuit of claim 5, wherein the MOS transistor of the first type is a PMOS (p-channel metal oxide semiconductor) transistor, and the MOS transistor of the second type is an NMOS (n-channel metal oxide semiconductor) transistor.

7. A method comprising: incorporating a plurality of stages, each comprising a MOS (metal oxide semiconductor) transistor of a first type, a MOS transistor of a second type, and a resistor; cascading said plurality of stages in a ring topology so that each stage of said plurality of stages has a preceding stage, a succeeding stage, an alternate-preceding stage, and an alternate-succeeding stage; using the MOS transistor of the first type to receive a first input that is output from the preceding stage and output a second output to the alternate-preceding stage; using the MOS transistor of the second type to receive a second input that is output from the alternate-succeeding stage and output a first output to the succeeding stage; and using the resistor to provide coupling and level-shifting between the first output and the second output.

8. The method of claim 7, wherein the MOS transistor of the first type is an NMOS (n-channel metal oxide semiconductor) transistor, and the MOS transistor of the second type is a PMOS (p-channel metal oxide semiconductor) transistor.

9. The method of claim 7, wherein the MOS transistor of the first type is a PMOS (p-channel metal oxide semiconductor) transistor, and the MOS transistor of the second type is an NMOS (n-channel metal oxide semiconductor) transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A shows a schematic diagram of a prior art ring oscillator.

(2) FIG. 1B shows a schematic diagram of an inverter of FIG. 1A.

(3) FIG. 2 shows a schematic diagram of a ring oscillator in accordance with an embodiment of the present disclosure.

(4) FIG. 3A shows a waveform of a simulation of the ring oscillator of FIG. 2.

(5) FIG. 3B shows an additional waveform of the simulation of the ring oscillator of FIG. 2.

(6) FIG. 4 shows a flow diagram of a method in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

(7) The present disclosure is directed to ring oscillators. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

(8) This present disclosure is disclosed in an engineering sense. For instance, X is equal to Y means a difference between X and Y is smaller than a specified engineering tolerance; X is much smaller than Y means X divided by Y is smaller than an engineering tolerance; and X is zero means X is smaller than a specified engineering tolerance.

(9) Throughout this disclosure, V.sub.DD denotes a power supply node. For convenience, V.sub.DD can also refer to a power supply voltage provided at the power supply node. That is, V.sub.DD is 0.9V means a power supply voltage at the power supply node V.sub.DD is 0.9V.

(10) The present invention is directed to embodiments for overcoming a limitation set by a low supply voltage upon a ring oscillator.

(11) An NMOS transistor is a voltage-to-current conversion device that converts a gate-to-source voltage V.sub.gs into a drain current I.sub.d approximately in accordance with the following equation:

(12) $\begin{array}{cc}{I}_d=\{\begin{array}{cc}{K\left(V_{\mathrm{gs}}-V_{\mathrm{th}}\right)}^2& V_{\mathrm{gs}}>V_{\mathrm{th}}\\ 0& V_{\mathrm{gs}}{V}_{\mathrm{th}}\end{array}& \left(1\right)\end{array}$

(13) Here, V.sub.th is a threshold voltage, and K is a constant. V.sub.gsV.sub.th is an overdrive voltage that determines the drain current. In a circuit where a supply voltage is V.sub.DD, the gate-to-source voltage V.sub.gs will be limited to be no higher than V.sub.DD, and thus the drain current I.sub.d is limited to no higher than K(V.sub.DDV.sub.th).sup.2. Equation (1) is also applicable to a PMOS transistor, but a polarity of the gate-to-source voltage V.sub.gs needs to be reversed (i.e., gate-to-source voltage is replaced by source-to-gate voltage). In a circuit of a low supply voltage, it is difficult for a MOS transistor to output a large drain current due to inherently lacking a high overdrive voltage. In this present disclosure, the absence of a high overdrive voltage to output a large drain current in a low-supply voltage scenario is overcome by extending a duration of the overdrive voltage and thus the drain current. A duty ratio of a MOS transistor is a percentage of time that the MOS transistor is turned on to output a drain current. A total charge output by a MOS transistor is a time-integral of the drain current of said MOS transistor. If the drain current is, for example, reduced by 20% due to a lower supply voltage, but the duration of the drain current, or a duty ratio of the MOS transistor, is extended by 20%, the total charge output by the MOS transistor can remain the same. This way, a reduction in current is compensated by an increase in duty ratio, and the limitation of the low supply voltage can be overcome.

(14) A schematic diagram of a ring oscillator 200 in accordance with an embodiment of the present disclosure is depicted in FIG. 2. Ring oscillator 200 comprises a first stage 210, a second stage 220, a third stage 230, and a fourth stage 240 cascaded in a ring topology. Due to the ring topology, each stage (of stages 210, 220, 230, and 240) has a preceding stage and a succeeding stage; a preceding stage of the preceding stage is referred to as an alternate-preceding stage; and a succeeding stage of the succeeding stage is to as an alternate-succeeding stage. More specifically: stage 210 (220, 230, 240) is the preceding stage of stage 220 (230, 240, 210) and the alternate-preceding stage of stage 230 (240, 210, 220); on the other hand, stage 210 (220, 230, 240) is the succeeding stage of stage 240 (210, 220, 230) and the alternate-succeeding stage of stage 230 (240, 210, 220).

(15) Each stage comprises an NMOS transistor, a PMOS transistor, and a resistor. More specifically, stage 210 (220, 230, 240) comprises NMOS transistor MN1 (MN2, MN3, MN4), PMOS transistor MP1 (MP2, MP3, MP4), and resistor R1 (R2, R3, R4). NMOS transistor MN1 (MN2, MN3, MN4) receives a first (third, fifth, seventh) voltage V.sub.1 (V.sub.3, V.sub.5, V.sub.7) from a first (third, fifth, seventh) node N1 (N3, N5, N7) and outputs a second (fourth, sixth, eighth) voltage V.sub.2 (V.sub.4, V.sub.6, V.sub.8) to a second (fourth, sixth, eighth) node N2 (N4, N6, N8). PMOS transistor MP1 (MP2, MP3, MP4) receives the sixth (eighth, second, fourth) voltage V.sub.6 (V.sub.8, V.sub.2, V.sub.4) and outputs the third (fifth, seventh, first) voltage V.sub.3 (V.sub.5, V.sub.7, V.sub.1) to the third (fifth, seventh, first) node N3 (N5, N7, N1). Resistor R1 (R2, R3, R4) provides a coupling between the second (fourth, sixth, eighth) node N2 (N4, N6, N8) and the third (fifth, seventh, first) node N3 (N5, N7, N1) and fulfills a level-shifting function.

(16) In summary, each stage receives a first input that is output from the preceding stage and a second input that is output from the alternate-succeeding stage, and outputs a first output to the succeeding stage and a second output to the alternate-preceding stage; the NMOS transistor therein is configured to receive the first input and output the second output; the PMOS transistor therein is configured to receive the second input and output the first output; and the resistor therein is configured to provide a coupling and level-shifting between the first output and the second output. Here, for stage 210 (220, 230, 240): the NMOS transistor therein refers to NMOS transistor MN1 (MN2, MN3, MN4); the PMOS transistor therein refers to PMOS transistor MP1 (MP2, MP3, MP4); the resistor therein refers to resister R1 (R2, R3, R4); the preceding stage is stage 240 (210, 220, 230); the first input refers to V.sub.1 (V.sub.3, V.sub.5, V.sub.7); the alternate-succeeding stage is stage 230 (240, 210, 220); the second input refers to V.sub.6 (V.sub.8, V.sub.2, V.sub.4); the succeeding stage is stage 220 (230, 240, 210); the first output refers to V.sub.3 (V.sub.5, V.sub.7, V.sub.1); the alternate-preceding stage is stage 230 (240, 210, 220); the second output refers to V.sub.2 (V.sub.4, V.sub.6, V.sub.8); when the first input rises sufficiently high, the NMOS transistor therein is turned on and pulls down the second output directly and pulls down the first output indirectly via the resistor therein, but the first output remains higher than the second output due to the resistor therein; when the second input falls sufficiently low, the PMOS transistor therein is turned on and pulls up the first output directly and pulls up the second output indirectly via the resistor therein, but the first output remains higher than the second output due to the resistor therein. This way, the first output remains higher than the second output, and a level-shifting function is thus fulfilled.

(17) Due to the level-shifting of resistor R1 (R2, R3, R4), NMOS transistor MN2 (MN3, MN4, MN1) can have a high duty ratio since V.sub.3 (V.sub.5, V.sub.7, V.sub.1) can stay high to allow draining current from node N4 (N6, N8, N2) for a long duration. A total charge drained from node N4 (N6, N8, N2) can be high, and therefore a pull-down of V.sub.4 (V.sub.6, V.sub.8, V.sub.2) by NMOS transistor MN2 (MN3, MN4, MN1) can be strong even when the supply voltage V.sub.DD is low. Likewise, PMOS transistor MP3 (MP4, MP1, MP2) can have a high duty ratio due to that V.sub.2 (V.sub.4, V.sub.6, V.sub.8) can stay low to allow injecting current to node N7 (N1, N3, N5) for a long duration. A total charge injected to node N7 (N1, N3, N5) can be high, and a pull-up of V.sub.7 (V.sub.1, V.sub.3, V.sub.5) by PMOS transistor MP3 (MP4, MP1, MP2) can be strong even when the supply voltage V.sub.DD is low. Ring oscillator 200, therefore, can overcome a limitation of a low supply voltage by extending a duty ratio of a MOS transistor thanks to the level-shifting function.

(18) An oscillation cycle of ring oscillator 200 is described as follows. Consider a low-to-high transition event of V.sub.1; it prompts NMOS transistor MN1 to pull down V.sub.2 to ground; this prompts PMOS transistor MP3 to pull up V.sub.7 to V.sub.DD; this prompts NMOS transistor MN4 to pull down V.sub.8 to ground and also pulls down V.sub.1 to ground via resistor R4, resulting in a high-to-low transition event of V.sub.1; this prompts PMOS transistor MP2 to pull up V.sub.5 to V.sub.DD; this prompts NMOS transistor MN3 to pull down V.sub.6 to ground; and this prompts PMOS transistor MP1 to pull up V.sub.3 to V.sub.DD; this prompts MNOS transistor MN2 to pull down V.sub.4 to ground; this prompts PMOS transistor MP4 to pull up V.sub.1 to V.sub.DD, resulting in a next low-to-high transition event of V.sub.1. This way, a low-to-high transition event takes place in a cyclic, recurring manner, and an oscillation is thus established.

(19) Note that resistor R1 (R2, R3, R4) can also avoid a direct contention between NMOS transistor MN1 (MN2, MN3, MN4) and PMOS transistor MP1 (MP2, MP3, MP4), and therefore the same merit of the prior art ring oscillator taught by Lin in U.S. Pat. No. 9,252,753 is preserved.

(20) Note that, in a circuit comprising a plurality of PMOS transistors and a plurality of NMOS transistors, the function of the circuit remains the same if every PMOS transistor is replaced by an NMOS transistor, every NMOS transistor is replaced by a PMOS transistor, every power supply node is replaced by a ground node, and every ground node is replaced by a power supply node. This way, the circuit is said to be flipped, wherein the roles of PMOS transistor and NMOS transistor are swapped and the roles of power supply and ground are also swapped, but the function remains the same. Therefore, ring oscillator 200 can be flipped and becomes an alternative embodiment, which does not need to be explicitly shown, such an implementation would be obvious to persons of ordinary skill in the art.

(21) Ring oscillator 200 is a four-stage ring oscillator, but the teaching of the present disclosure can be applied to any number of stages that is higher than two, e.g. three-stage, four-stage, five-stage, six-stage, seven-stage, and so on.

(22) In ring oscillator 200, for each stage, the alternate-preceding stage happens to be the same as the alternate-succeeding stage. However, this is a coincidence and a special case that only occurs in a four-stage scenario. In general, the alternate-preceding stage is different from the alternate-succeeding stage, except for the special case of a four-stage scenario.

(23) By way of example but not limitation, in an embodiment, ring oscillator 200 is fabricated using a 28 nm CMOS (complementary metal oxide semiconductor) process; width and length of NMOS transistors MN1, MN2, MN3, and MN4 are 32 m and 45 nm, respectively; width and length of PMOS transistors MP1, MP2, MP3, and MP4 are 16 m and 30 nm, respectively; resistors R1, R2, R3, R4 are 75 Ohm; and V.sub.DD is 0.77V. A simulation result is shown in FIGS. 3A and 3B. Here, an oscillation frequency is approximately 14.25 GHz and a period is approximately 70.18 ps. As shown in FIG. 3A, V.sub.7, V.sub.5, V.sub.3, and V.sub.1 are of the same waveform but uniformly displaced in time to form a four-phase clock. As shown in FIG. 3B, V.sub.6, V.sub.4, V.sub.2, and V.sub.8 are of the same waveform but uniformly displaced in time to form a four-phase clock. It is clear that V.sub.7, V.sub.5, V.sub.3, and V.sub.1 stay high longer than low, resulting in a high duty ratio to allow the NMOS transistors they control to output more charge. On the other hand, V.sub.6, V.sub.4, V.sub.2, and V.sub.8 stay low longer than high, resulting in a high duty ratio to allow the PMOS transistors they control to output more charge.

(24) As illustrated by the flow diagram shown in FIG. 4, a method in accordance with an embodiment of the present disclosure comprises: (step 401) incorporating a plurality of stages, each comprising a MOS transistor of a first type, a MOS transistor of a second type, and a resistor; (step 402) cascading said plurality of stages in a ring topology so that each stage of said plurality of stages has a preceding stage, a succeeding stage, an alternate-preceding stage, and an alternate-succeeding stage; (step 403) using the MOS transistor of the first type to receive a first input that is output from the preceding stage and output a second output to the alternate-preceding stage; (step 404) using the MOS transistor of the second type to receive a second input that is output from the alternate-succeeding stage and output a first output to the succeeding stage; and (step 405) using the resistor to provide a coupling and level-shifting between the first output and the second output.

(25) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure.

(26) Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.