INSULATED CIRCUIT BOARD

Abstract

Provided is an insulated circuit board including a ceramic substrate, a circuit layer, and a metal layer that is bonded to the other surface of the ceramic substrate, the circuit layer and the metal layer are made of copper or a copper alloy, the circuit layer is formed of a plurality of punched sheets bonded to the ceramic substrate at an interval, the thickness of the circuit layer is 0.4 mm or more and 2.0 mm or less, when the bonding area of the circuit layer is represented by S1, and the bonding area of the metal layer is represented by S2, the area ratio S1/S2 is 0.5 or more and 0.8 or less, and, when the thickness of the circuit layer is represented by T1, and the thickness of the metal layer is represented by T2, the thickness ratio T1/T2 is 1.2 or more and 1.7 or less.

Claims

1. An insulated circuit board comprising: a ceramic substrate having a three-point bending strength, which is based on JIS 1601 2008, of 600 MPa or more; a circuit layer that is made of copper or a copper alloy, includes a plurality of small circuit layers that is bonded to one surface of the ceramic substrate at an interval so as to form a predetermined shape, and has a thickness T1 of 0.4 mm or more and 2.0 mm or less; and a metal layer that is made of copper or a copper alloy and is bonded to the other surface of the ceramic substrate, wherein, when a bonding area of the circuit layer to the ceramic substrate is represented by S1, and a bonding area of the metal layer to the ceramic substrate is represented by S2, an area ratio S1/S2 is 0.5 or more and 0.8 or less, and when a thickness of the metal layer is represented by T1, and a thickness of the metal layer is represented by T2, a thickness ratio T1/T2 is 1.2 or more and 1.7 or less.

2. The insulated circuit board according to claim 1, wherein the ceramic substrate is made of silicon nitride.

3. The insulated circuit board according to claim 1, wherein, in the circuit layer, each of the small circuit layers is made of a punched sheet.

4. The insulated circuit board according to claim 1, wherein, in the circuit layer, each of the small circuit layers is a polygonal flat sheet.

5. The insulated circuit board according to claim 4, wherein each of the small circuit layers has a rectangular shape.

6. The insulated circuit board according to claim 1, wherein, in the circuit layer, the interval between the plurality of small circuit layers is 0.5 mm or more and 2.0 mm or less.

7. The insulated circuit board according to claim 1, wherein, in the circuit layer, the plurality of small circuit layers has the same composition.

8. The insulated circuit board according to claim 1, wherein the circuit layer and the metal layer have the same composition.

9. The insulated circuit board according to claim 2, wherein, in the circuit layer, each of the small circuit layers is made of a punched sheet.

10. The insulated circuit board according to claim 2, wherein, in the circuit layer, each of the small circuit layers is a polygonal flat sheet.

11. The insulated circuit board according to claim 3, wherein, in the circuit layer, each of the small circuit layers is a polygonal flat sheet.

12. The insulated circuit board according to claim 2, wherein, in the circuit layer, the interval between the plurality of small circuit layers is 0.5 mm or more and 2.0 mm or less.

13. The insulated circuit board according to claim 3, wherein, in the circuit layer, the interval between the plurality of small circuit layers is 0.5 mm or more and 2.0 mm or less.

14. The insulated circuit board according to claim 4, wherein, in the circuit layer, the interval between the plurality of small circuit layers is 0.5 mm or more and 2.0 mm or less.

15. The insulated circuit board according to claim 5, wherein, in the circuit layer, the interval between the plurality of small circuit layers is 0.5 mm or more and 2.0 mm or less.

16. The insulated circuit board according to claim 2, wherein, in the circuit layer, the plurality of small circuit layers has the same composition.

17. The insulated circuit board according to claim 3, wherein, in the circuit layer, the plurality of small circuit layers has the same composition.

18. The insulated circuit board according to claim 4, wherein, in the circuit layer, the plurality of small circuit layers has the same composition.

19. The insulated circuit board according to claim 2, wherein the circuit layer and the metal layer have the same composition.

20. The insulated circuit board according to claim 3, wherein the circuit layer and the metal layer have the same composition.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0024] FIG. 1 is a cross-sectional view of a power module in which an insulated circuit board according to an embodiment of the present invention is used.

[0025] FIG. 2A is a plan view of the insulated circuit board in the embodiment as viewed from a circuit layer side.

[0026] FIG. 2B is a plan view of the insulated circuit board in the embodiment as viewed from a metal layer side.

[0027] FIG. 3A is a cross-sectional view for describing a method for manufacturing the insulated circuit board shown in FIG. 1.

[0028] FIG. 3B is a cross-sectional view for describing the method for manufacturing the insulated circuit board shown in FIG. 1.

[0029] FIG. 3C is a cross-sectional view for describing the method for manufacturing the insulated circuit board shown in FIG. 1.

DESCRIPTION OF EMBODIMENTS

[0030] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[Schematic Configuration of Insulated Circuit Board]

[0031] An insulated circuit board 1 that is manufactured by a method for manufacturing an insulated circuit board according to the present invention is a so-called power module board as shown in FIG. 1, and an element 30 is mounted on a surface of the insulated circuit board 1 as shown by a chain double-dashed line in FIG. 1 to configure a power module 100. The element 30 is an electronic component including a semiconductor, and a variety of semiconductor elements such as an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), and a freewheeling diode (FWD) semiconductor element are selected.

[0032] While not shown, the element 30 is provided with an upper electrode portion on the upper portion and a lower electrode portion on the lower portion. The lower electrode portion is bonded to the upper surface of a circuit layer 12 with solder 31 or the like, whereby the element 30 is mounted on the upper surface of the circuit layer 12. The upper electrode portion of the element 30 is connected to a circuit electrode portion or the like of the circuit layer 12 through a lead frame or the like bonded with solder or the like.

[Configuration of Insulated Circuit Board]

[0033] The insulated circuit board 1 includes a ceramic substrate 11, the circuit layer 12 that is bonded to one surface of the ceramic substrate 11 and includes a plurality of small circuit layers 121 and 122, and a metal layer 13 bonded to the other surface of the ceramic substrate 11.

[0034] The ceramic substrate 11 is an insulated substrate that prevents electrical connection between the circuit layer 12 and the metal layer 13, the sheet thickness T3 of the ceramic substrate 11 is 0.2 mm to 1.0 mm, and the three-point bending strength is 600 MPa or more. The ceramic substrate 11 is configured using, for example, a silicon nitride ceramic (Si.sub.3N.sub.4) or zirconia-reinforced alumina substrate. In this case, it is possible to increase the strength and the heat transfer coefficient of the ceramic substrate compared with those of a ceramic substrate made of aluminum nitride (AIN).

[0035] The ceramic substrate 11 of the present embodiment is made of silicon nitride ceramic and has a sheet thickness T3 set to 0.32 mm and a three-point bending strength set to 600 MPa or more and 1020 MPa or less.

[0036] In the example shown in FIG. 1 and FIGS. 2A and 2B, the circuit layer 12 includes two separated small circuit layers 121 and 122. The small circuit layers 121 and 122 each have a polygonal shape (a rectangular shape in the present embodiment) and are separately bonded to one surface of the ceramic substrate 11 at an interval (for example, 0.5 mm to 2.0 mm).

[0037] The circuit layer 12 (each of the small circuit layers 121 and 122) is formed of copper such as oxygen-free copper or a copper alloy such as a zirconium-added copper alloy, and the sheet thickness T1 of the circuit layer 12 is set to 0.4 mm or more and 2.0 mm or less. The sheet thickness T1 is larger than the sheet thickness T2 of the metal layer 13, and the thickness ratio T1/T2 is set to 1.2 or more and 1.7 or less. In the circuit layer 12 of the present embodiment, both the small circuit layers 121 and 122 have the same composition.

[0038] The circuit layer 12 of the present embodiment is made of oxygen-free copper and has a sheet thickness T1 set to 0.8 mm The interval between the small circuit layers 121 and 122 is set to 1.0 mm.

[0039] The metal layer 13 is made of high-purity copper such as oxygen-free copper or a copper alloy such as a zirconium-added copper alloy, and the sheet thickness T2 of the metal layer 13 is set to 0.3 mm or more and 1.6 mm or less. As described above, the sheet thickness T2 of the metal layer 13 is smaller than the sheet thickness T1 of the circuit layer 12, and the thickness ratio T1/T2 is set to 1.2 or more and 1.7 or less.

[0040] The metal layer 13 of the present embodiment is made of oxygen-free copper having the same composition as the oxygen-free copper of the circuit layer 12 and has a sheet thickness set to 0.6 mm.

[0041] In the insulated circuit board 1 configured as described above, when the bonding area of the circuit layer 12 is represented by S1 (mm.sup.2), and the bonding area of the metal layer 13 is represented by S2 (mm.sup.2), the area ratio S1/S2 is adjusted to a relationship in which the area ratio becomes 0.5 or more and 0.8 or less. The bonding areas S1 and S2 are values at 30 C.

[0042] In the present embodiment, since the circuit layer 12 includes the small circuit layers 121 and 122, the bonding area S1 of the circuit layer 12 is the sum of the bonding area S11 of the small circuit layer 121 and the bonding area S12 of the small circuit layer 122.

[Method of Manufacturing Insulated Circuit Board]

[0043] Next, a method for manufacturing the insulated circuit board 1 of the present embodiment will be described. The method for manufacturing the insulated circuit board 1 includes a metal sheet formation step of pressing sheet materials made of copper or a copper alloy to form one metal sheet for the metal layer 130 and a metal sheet for the circuit layer 120 and a bonding step of heating and bonding the metal sheet for the metal layer 130 and the metal sheet for the circuit layer 120 laminated on the ceramic substrate 11 through a brazing filler metal in a pressurized state. The metal sheet for the metal layer 130 is to serve as the metal layer 13, and the metal sheet for the circuit layer 120 has a predetermined shape (circuit pattern) and is to serve as the circuit layer 12. Hereinafter, the manufacturing method will be described in order of these steps.

(Metal Sheet Formation Step)

[0044] First, as shown in FIG. 3A, rolled sheets made of copper or a copper alloy (hereinafter, referred to as rolled copper materials) are punched by pressing to form the metal sheet for the metal layer 130 and the metal sheets for the circuit layer 120.

[0045] Specifically, the metal sheet for the metal layer 130 is formed into a rectangular sheet shape (for example, 40 mm50 mm) by pressing a rolled copper material having a thickness of 0.3 mm or more and 1.6 mm or less. The metal sheet for the circuit layer 120 is formed into a desired pattern shape (two rectangular punched sheets in the example shown in FIG. 2A) by pressing a rolled copper material having a thickness of 0.4 mm or more and 2.0 mm or less. That is, the metal sheet for the circuit layer 120 corresponds to a plurality of punched sheets of the present invention. The area ratio S1/S2 of the area S1 of the metal sheet for the circuit layer 120 formed as described above to the area S2 of the metal sheet for the metal layer 130 is set to 0.5 or more and 0.8 or less.

(Bonding Step)

[0046] Next, as shown in FIG. 3B, the metal sheet for the metal layer 130 and the metal sheet for the circuit layer 120 are bonded to the ceramic substrate 11. Specifically, the metal sheet for the metal layer 130 and the metal sheet for the circuit layer 120 are laminated on the front surface and the back surface of the ceramic substrate 11 with AgCuTi-based brazing filler metal foils 14 interposed therebetween. This laminate is sandwiched with carbon sheets and heated in a vacuum under a load applied in the laminating direction, thereby bonding the metal sheet for the metal layer 130 and the metal sheet for the circuit layer 120 to the ceramic substrate 11. Therefore, the insulated circuit board 1 in which the circuit layer 12 is bonded to the front surface of the ceramic substrate 11 shown in FIG. 3C through the bonding portion (brazing portion) and the metal layer 13 is bonded to the back surface through the bonding portion (brazing portion) is formed.

[0047] In this bonding step, the pressure applied in the laminating direction is preferably set to 0.1 MPa to 1.0 MPa, and the heating temperature is preferably set to 800 C. to 930 C. In addition, the AgCuTi-based brazing filler metal foil is preferably 5 m to 15 m in thickness. Furthermore, in addition to the AgCuTi-based brazing filler metal, a CuP-based brazing filler metal can also be used.

[0048] In the insulated circuit board 1 manufactured by the above-described manufacturing method, the thickness T1 of the circuit layer 12 is 0.4 mm or more and 2.0 mm or less, the area ratio S1/S2 of the bonding area S1 of the circuit layer 12 to the bonding area S2 of the metal layer 13 becomes 0.5 or more and 0.8 or less, and the thickness ratio T1/T2 of the thickness T1 of the circuit layer 12 to the thickness T2 of the metal layer 13 becomes 1.2 or more and 1.7 or less.

[0049] Regarding residual stresses that are generated on the surfaces of the ceramic substrate 11, on the bonding surface with the circuit layer 12 or the metal layer 13, a compressive stress is generated. However, since the pattern is formed on the circuit layer 12 side, as shown in FIG. 2A, in the portion between the respective small circuit layers 121 and 122 (the region Ar1 exposed due to the formation of the pattern), a compressive stress is generated on the back side, and a tensile stress is generated on the front side. Therefore, the ceramic substrate is likely to warp such that the circuit layer 12 side becomes convex. In this case, as the circuit layer 12 and the metal layer 13 become thicker, the ceramic substrate more significantly warps.

[0050] In contrast, in the present embodiment, even when a residual stress is generated between the respective small circuit layers 121 and 122 (the region Ar1) on the ceramic substrate 11, since the thickness of the second metal layer 13 is thinner than the thickness of the circuit layer 12, it is possible to maintain the balance between the circuit layer 12-side surface and the metal layer 13-side surface of the ceramic substrate 11. Therefore, even in a case where the circuit layer 12 is formed by the pressing method instead of the etching method, it is possible to suppress a high-temperature warpage change during soldering.

[0051] The other detailed configurations are not limited to those in the configuration of the embodiment, and a variety of modifications can be added without departing from the gist of the present invention.

[0052] For example, in the above-described embodiment, an example in which the insulated circuit board 1 is used as a power module board has been described, but the insulated circuit board 1 can also be used as a variety of kinds of insulated boards such as a substrate for an LED element.

Example

[0053] Next, the effects of the present invention will be described in detail using examples, but the present invention is not limited to the following examples.

[0054] As members configuring specimens of Examples 1 to 7 and Comparative Examples 1 and 2, ceramic substrates that had a sheet thickness of 0.32 mm and were made of silicon nitride ceramic were prepared, and circuit layers and metal layers that had a sheet thickness and a bonding area shown in Table 1 and were formed of oxygen-free copper were prepared. The interval between two small circuit layers that configured the circuit layer was set to 1.0 mm

[0055] In Table 1, the thickness of the circuit layer is indicated by T1 (mm), the thickness of the metal layer is indicated by T2 (mm), the bonding area of the circuit layer is indicated by S1 (mm.sup.2), and the bonding area of the metal layer is indicated by S2 (mm.sup.2).

[0056] These members were bonded together by the manufacturing method described in the above-described embodiment to produce insulated circuit boards, and the respective specimens of Examples 1 to 7 and Comparative Examples 1 and 2 were produced. In a series of heating tests designed to apply a temperature change such that a sample was heated from 30 C. to 285 C. and then cooled to 30 C., for each of the obtained specimens, the amount of warpage during heating to 285 C. (warpage during heating) and the amount of warpage (returning warpage) at 30 C. when the specimen had been heated to 285 C. and then cooled to 30 C. were respectively measured from the metal layer side. The amount of warpage was obtained by measuring the change of the ceramic substrate using a Moire-type three-dimensional shape measurement instrument, and the amount of change in the amount of warpage (difference between warpage during heating and returning warpage) was also obtained. The amount of warpage was expressed as negative in a case where the metal layer became concave and expressed as positive in a case where the metal layer became convex. The results are shown in Table 1.

TABLE-US-00001 TABLE 1 Warp- Re- age turning Amount at warp- of T1 T2 285 C. age change S1/S2 (mm) (mm) T1/T2 (m) (m) (m) Example 1 0.75 0.8 0.65 1.23 312 195 507 Example 2 0.75 0.8 0.6 1.33 268 184 452 Example 3 0.75 0.8 0.5 1.6 141 266 407 Example 4 0.75 1.5 1 1.5 162 273 435 Example 5 0.75 2 1.2 1.7 293 342 49 Example 6 0.8 0.8 0.5 1.6 155 299 454 Example 7 0.65 0.8 0.5 1.6 132 232 364 Comparative 0.75 0.8 0.7 1.14 650 400 1050 Example 1 Comparative 0.75 0.8 0.4 2 523 320 843 Example 2

[0057] As is clear from Table 1, it was possible to confirm that, in Examples 1 to 7 in which the area ratios S1/S2 of the bonding area S1 of the circuit layer to the bonding area S2 of the metal layer were 0.5 or more and 0.8 or less, the thickness ratios T1/T2 were 1.2 or more and 1.7 or less, the amounts of warpage were small at a high temperature during soldering or the like, and the amounts of change were also as small as 600 m or less in the obtained insulated circuit boards.

INDUSTRIAL APPLICABILITY

[0058] It is possible to suppress a warpage change at a high temperature during soldering of an insulated circuit board.

REFERENCE SIGNS LIST

[0059] 1 Insulated circuit board

[0060] 11 Ceramic substrate

[0061] 12 Circuit layer

[0062] 13 Metal layer

[0063] 14 Brazing filler metal foil

[0064] 30 Element

[0065] 31 Solder

[0066] 100 Power module

[0067] 120 Metal sheet for circuit layer (punched sheet)

[0068] 130 Metal sheet for metal layer

[0069] 121 Small circuit layer

[0070] 122 Small circuit layer

[0071] S1 Bonding area

[0072] S2 Bonding area

[0073] S11 Bonding area

[0074] S12 Bonding area

[0075] T1 Thickness of circuit layer

[0076] T2 Thickness of metal layer

[0077] T3 Thickness of ceramic substrate

[0078] Ar1 Region