CASCADED MODULAR MULTILEVEL CONVERTER FOR MEDIUM-VOLTAGE POWER ELECTRONICS SYSTEMS

Abstract

A cascaded modular multilevel converter for medium-voltage power electronics systems is disclosed. The converter can be used in applications such as an auxiliary power supply for medium-voltage (MV) power electronics system, or a unidirectional SST which powers a home (where very light load conditions are experienced when the home is unoccupied or during the night). Unlike the traditional solutions which use a grid-frequency, bulky, and heavy power transformers, the disclosed converter can operate at higher switching frequencies, weigh less, and provide a higher power density than other approaches. Additionally, the disclosed converter features an internal capacitor voltage balancing and can achieve power factor correction (PFC) using predictive control.

Claims

1. A cascaded modular multilevel converter for medium-voltage power electronics systems, comprising: a plurality of modules, wherein each module has a bus capacitor, a diode and a switch so that the bus capacitors between modules may be connected in series or in parallel depending on the state of the switches in the modules.

2. The power electronic converter according to claim 1, wherein an input voltage of the power electronic converter corresponds to the number of modules in the plurality.

3. The power electronic converter according to claim 1, wherein the converter has a first number (N) of modules, and wherein the converter has a second number (N+1) of modes of operation based on the state of the switch in each of the N modules.

4. The power electronic converter according to claim 3, wherein a composed voltage of the converter is number (m) (where 0mN) times a bus capacitor voltage when Nm of the N modules have closed (ON) switches and m of the N modules have an open (OFF) switch.

5. The power electronic converter of claim 1, further comprising a dc/dc power converter wherein the dc/dc power converted is connected to an output of the power electronic converter to provide galvanic isolation of a regulated output voltage.

6. The power electronic converter of claim 1, wherein the power electronic converter has an input voltage and an output voltage.

7. The power electronic converter of claim 6, wherein the input voltage is 2.4 kV RMS and the output voltage is 24 V dc.

8. The power electronic converter of claim 7, wherein the power electronic converter has a power rating of 100 Watts with 10kV of isolation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1A schematically illustrates a conventional MMSPC topology with 3 modules and a plurality of MOSFET switches.

[0010] FIG. 1B schematically illustrates the MMSPC topology of FIG. 1A simplified with diodes substituting some of the MOSFET switches, which is made possible due to unidirectional operation of the converter.

[0011] FIG. 1C schematically illustrates the MMSPC topology of FIG. 1B simplified further by shorting the devices in a permanently ON state and removing devices in a permanently OFF state.

[0012] FIG. 1D schematically illustrates the MMSPC topology of FIG. 1C rearranged for clarity, wherein FIGS. 1A-1D illustrate the simplification progress from a conventional MMSPC (FIG. 1A) to the power electronic converter of the present disclosure (FIG. 1D).

[0013] FIG. 2 schematically illustrates an implementation of the disclosed power electronic converter in an auxiliary power supply.

[0014] FIG. 3 schematically illustrates the power electronic converter according to the present disclosure.

[0015] FIGS. 4A-4H schematically illustrate the operating modes of the power electronic converter of FIG. 3, wherein FIG. 4A is Mode 0: bypass connection, FIGS. 4B-4D are Mode 1: combination of series/parallel/bypass connections on modules, FIGS. 4E-4G are Mode 2: combination of series/parallel/bypass connections on modules, and FIG. 4H is Mode 3: series connection of all modules.

DETAILED DESCRIPTION

[0016] The present disclosure embraces a power electronic converter which is derived from MMSPC. The MMSPC's topology is a generalization of a conventional modular multilevel converter (MMC) topology, and allows not only series but also parallel connections among modules. One advantage of the MMSPC over MMC is the modules' voltages are balanced without sensing. Another advantage of the MMSPC is a reduction in the current rating necessary for each switch in the MMSPC. Each switch in the MMSPC requires half the current rating required for a switch in a conventional MMC.

[0017] Additionally, the MMSPC features an internal capacitor voltage balancing and requires only one dc-link voltage sensor to perform the required control. Even at light load operation (when the input current is relatively small), a PFC may be used to achieve a unity power factor (PF) and a low total harmonic distortion (THD) of the input current. The MMSPC may be used easily with a predictive PFC control algorithm. The power electronic converter disclosed herein retains all the advantages of the MMSPC. The disclosed power electronic converter has an advantage of significantly reduced number of power semiconductor devices, compared to the MMSPC.

[0018] Although a MMSPC is capable of bidirectional operation, some applications, such as a power supply, require only unidirectional power flow (i.e., from the HV ac input to the dc output). While other unidirectional applications may exist, the power supply application is considered for convenience in what follows.

[0019] As shown in FIGS. 1A and 1B, unidirectional power flow implies that only bypass connection, parallel connections, and series connection with negative polarities are used. This allows for the substitution of diodes for some of the MOSFETs, as shown in FIGS. 1A and 1B. Further, it can be noticed that, in operation, some of the devices would always stay in the ON state, while some of the devices would always remain in the OFF state. Those devices that would stay in the ON state (i.e., devices marked yellow and/or the word on in FIG. 1B) can be replaced with a short circuit, whereas those that would always remain OFF (i.e., devices marked green and/or the word off in FIG. 1B) can be completely removed from the circuit. Additionally, some MOSFETs (i.e., marked red and/or the letters dio in FIG. 1B) can be replaced by diodes because they need to conduct only when their body diodes would naturally conduct (e.g., in the absence of the gate signal). This replacement, as shown in FIG. 1C, further simplifies the topology. The topology can be rearranged for clarity as shown in FIG. 1D.

[0020] An auxiliary power supply based on the disclosed power electronic converter is shown in FIG. 2. In addition to the disclosed power electronic converter, a dc/dc power converter is connected to the output of the disclosed power electronic converter to provide the galvanic isolation of the regulated output voltage, as shown in FIG. 2. The disclosed power electronic converter has similar topology to known switched capacitor (SC) converters, but differs in the way the series/parallel connections are achieved and in the modulation strategy. The topology of the disclosed power electronic converter is fully scalable and can adapt to higher MV input voltage by simply increasing the number of series connected modules.

DISCLOSED POWER ELECTRONIC CONVERTER OPERATING PRINCIPLE

[0021] FIG. 3 schematically illustrates the power electronic converter of the present disclosure. The disclosed power electronic converter has four operating modes. The operating modes are schematically illustrated in FIGS. 4A-4H. As shown in FIGS. 4A-4H, the disclosed power electronic converter can produce 0V, 1Vbus, 2Vbus, or 3Vbus at the right-hand side of the input inductor (L.sub.in) by connecting the dc bus capacitors in series or in parallel.

[0022] The Table I lists balancing effect according to the switching states of the four different operating modes of the disclosed power electronic converter. The parallel connection of modules (dc bus capacitors) can be used to improve the dc-link voltages balancing and only one dc-link voltage sensor is required (at the C3 in FIG. 3). No other balancing control is necessary.

TABLE-US-00001 TABLE I BALANCING EFFECT ACCORDING TO SWITCHING STATE Switching Balancing Composed Mode state effect voltage Connection 0 (1, 1, 1) 0 V 3B 1-a (0, 1, 1) V.sub.bus, 2, V.sub.bus, 3 1S + 2B 1-b (1, 0, 1) V.sub.bus, 1, V.sub.bus, 2 1 V.sub.bus 2P + 1B 1-c (1, 1, 0) V.sub.bus, 1, V.sub.bus, 2, V.sub.bus, 3 3P 2-a (0, 0, 1) 2 V.sub.bus 2S + 1B 2-b (1, 0, 0) V.sub.bus, 1, V.sub.bus, 2 2P + 1S 2-c (0, 1, 0) V.sub.bus, 2, V.sub.bus, 3 1S + 2P 3 (0, 0, 0) 3 V.sub.bus 3S (B: bypass, S: series connection, P: parallel connection)

[0023] The equations that describe the input inductor's current slope in each of the 4 modes illustrated in FIGS. 4A-4H are presented in Table II. Due to the interleaved PWM scheme applied in this case, there are three distinct regions of the input voltage and three intervals of duty cycle, d, in which only certain operating modes can be applied, as shown in Table II.

TABLE-US-00002 TABLE II OPERATING REGIONS AND CORRESPONDING MODES OF THE PROPOSED CONVERTER TOPOLOGY Range Duty Mode Current Ripple slope Region 1 |v.sub.in| < V.sub.bus [00001]$\frac{2}{3}d<1$ Mode 0, 1 [00002]$\mathrm{up}.Math.\text{:}.Math..Math.\frac{.Math.v_{\mathrm{in}}.Math.}{L}$ [00003]$d.Math.\mathrm{own}.Math.\text{:}.Math..Math.\frac{.Math.v_{\mathrm{in}}.Math.-v_{\mathrm{bus}}}{L}$ Region 2 V.sub.bus < |v.sub.in| < 2V.sub.bus [00004]$\frac{1}{3}d<\frac{2}{3}$ Mode 1, 2 [00005]$\mathrm{up}.Math.\text{:}.Math..Math.\frac{.Math.v_{\mathrm{in}}.Math.-v_{\mathrm{bus}}}{L}$ [00006]$d.Math.\mathrm{own}.Math.\text{:}.Math..Math.\frac{.Math.v_{\mathrm{in}}.Math.-2.Math.v_{\mathrm{bus}}}{L}$ Region 3 2V.sub.bus < |v.sub.in| < 3V.sub.bus [00007]$0d<\frac{1}{3}$ Mode 2, 3 [00008]$\mathrm{up}.Math.\text{:}.Math..Math.\frac{.Math.v_{\mathrm{in}}.Math.-2.Math.v_{\mathrm{bus}}}{L}$ [00009]$d.Math.\mathrm{own}.Math.\text{:}.Math..Math.\frac{.Math.v_{\mathrm{in}}.Math.-3.Math.v_{\mathrm{bus}}}{L}$

[0024] Region 1: In this region, the equivalent circuit is changing between Mode 0 and Mode 1 (see FIGS. 4A and 4B-4D). This means that the converter has all bypass connections or all parallel connections. In Mode 0, due to the all bypass connections, the inductor sees a positive voltage of |V.sub.in|, resulting in increasing inductor current. On the other hand, in mode 1, the inductor sees the negative voltage of |V.sub.in|V.sub.bus (because |V.sub.in| is lower than V.sub.bus). In this mode, the inductor current decreases. Even though Mode 1 can have switching states other than (1,1,0) (i.e., as shown in FIG. 4D), all these states would produce the same inductor current ripple and can be described by the following two equations:

[00010]$\begin{array}{cc}.Math..Math.i_{L.Math.\_.Math.\mathrm{up}}=\frac{.Math.v_{\mathrm{in}}.Math.}{{\mathrm{Lf}}_s}.Math.\left(d-\frac{2}{3}\right)& \left(1\right)\\ .Math..Math.i_{L.Math.\_.Math.\mathrm{down}}=\frac{v_{\mathrm{bus}}-.Math.v_{\mathrm{in}}.Math.}{{\mathrm{Lf}}_s}.Math.\left(1-d\right)& \left(2\right)\end{array}$

where d is the duty cycle and f.sub.s is the switching frequency.

[0025] Region 2: In this region, the modules' connections are changing between Mode 1 and Mode 2 (see FIGS. 4B-4D and 4E-4G). In Mode 2, the inductor sees a negative voltage of |V.sub.in|2V.sub.bus, resulting in decreasing of the inductor current. In this region, the inductor current ripple can be described by the following two equations:

[00011]$\begin{array}{cc}.Math..Math.i_{L.Math.\_.Math.\mathrm{up}}=\frac{.Math.v_{\mathrm{in}}.Math.-v_{\mathrm{bus}}}{{\mathrm{Lf}}_s}.Math.\left(d-\frac{1}{3}\right)& \left(3\right)\\ .Math..Math.i_{L.Math.\_.Math.\mathrm{down}}=\frac{2.Math.v_{\mathrm{bus}}-.Math.v_{\mathrm{in}}.Math.}{{\mathrm{Lf}}_s}.Math.\left(\frac{2}{3}-d\right)& \left(4\right)\end{array}$

[0026] Region 3: In this region, the modules' connections are changing between Mode 2 and Mode 3 (see FIGS. 4E-4G and 4H). The analysis of Mode 2 is same as Region 2. In Mode 3, the inductor sees a negative voltage of |V.sub.in|3V.sub.bus. In this region, the inductor current ripple can be described by the following two equations:

[00012]$\begin{array}{cc}.Math..Math.i_{L.Math.\_.Math.\mathrm{up}}=\frac{.Math.v_{\mathrm{in}}.Math.-2.Math.v_{\mathrm{bus}}}{{\mathrm{Lf}}_s}.Math.d& \left(5\right)\\ .Math..Math.i_{L.Math.\_.Math.\mathrm{down}}=\frac{3.Math.v_{\mathrm{bus}}-.Math.v_{\mathrm{in}}.Math.}{{\mathrm{Lf}}_s}.Math.\left(\frac{1}{3}-d\right)& \left(6\right)\end{array}$

[0027] In the specification and/or figures, typical embodiments have been disclosed. Those skilled in the art will also appreciate that various adaptations and modifications of the preferred and alternative embodiments described above can be configured without departing from the scope and spirit of the disclosure.