POWER ARCHITECTURE FOR SERVER AND IT EQUIPMENT RACK

Abstract

A dual-input power supply has two power paths that connect a server to electrical Each power path has a first stage that comprises a power-factor correction circuit. The power paths share a common second stage that comprises a dc/dc converter. The first stages of the power paths collectively defining a pair of first stages that is disposed either within a package that is off the motherboard or without a package and on the motherboard. Similarly, the second stage is disposed either within a package that is off the motherboard or without a package and on the motherboard.

Claims

1. An apparatus comprising a power supply for providing power to a load comprising a server that has a motherboard having load circuitry thereon, said power supply being a dual-input power supply comprising first and second power paths that are connected to electrical power, wherein each of said first and second power paths connects to said load, wherein each of said power paths comprises a first stage that comprises a power-factor correction circuit, wherein said power paths share a common second stage that comprises a dc/dc converter, said first stages of said power paths collectively defining a pair of first stages that is disposed either within a package that is off said motherboard or without a package and on said motherboard, and wherein said second stage is disposed either within a package that off said motherboard or without a package and on said motherboard.

2. The apparatus of claim 1, wherein said power supply comprises a first package and a second package, wherein said pair of first stages is disposed within said first package, wherein said second stage is disposed within said second package, wherein said first package is insertable between said electrical power and said second package, and wherein said second package is insertable between said load and said first package, whereby said pair of first stages is removable from said power supply without removing said second stage, and whereby said second stage is removable from said power supply without removing said pair of first stages.

3. The apparatus of claim 1, wherein said power supply comprises a package that is insertable between said electrical power and said motherboard, wherein said pair of first stages is disposed within said package, and wherein said second stage is disposed on said motherboard along with said load circuitry.

4. The apparatus of claim 1, wherein said pair of first stages and said second stage are both disposed on said motherboard along with said load circuitry.

5. The apparatus of claim 1, wherein said power supply comprises zero fans.

6. The apparatus of claim 1, wherein said power supply comprises a fan.

7. The apparatus of claim 1, wherein said electrical power comprises a common ac power source that connects to both said first and second power paths.

8. The apparatus of claim 1, wherein said electrical power comprises first and second ac power sources, wherein said first power path connects to said first ac power source, and wherein said second power path connects to said second ac power source.

9. The apparatus of claim 1, wherein said electrical power comprises dc power and wherein, when said power supply is connected to said dc power, said first stage is bypassed.

10. The apparatus of claim 1, wherein said first stage comprises capacitors and transformers, that collectively sustain a voltage equal to that provided by a source of said electrical power, wherein each of said input capacitors sustains a fraction of said voltage, wherein each of said capacitors is connected across a primary winding of a corresponding one of said transformers, wherein said primary windings are cascaded, and wherein secondary windings of said transformers are tied together such that said second stage receives a voltage that is the sum of that across each of said capacitors.

11. The apparatus of claim 1, further comprising first and second heat sinks, wherein said first heat sink is disposed on said motherboard so as to be in thermal communication with said pair of first stages and wherein said second heat sink is disposed on said motherboard so as to be in thermal communication with said second stage.

12. The apparatus of claim 1, further comprising first and second heat shields disposed on said motherboard to prevent a user from inadvertently coming into contact with said pair of first stages and said second stage, respectively, wherein said first heat shield is disposed to cover said pair of first stages and said second heat shield is disposed to cover said second stage.

13. The apparatus of claim 1, further comprising first and second electromagnetic-interference shields disposed on said motherboard disposed to prevent electromagnetic interference from said pair of first stages and from said second stage from interfering with circuitry on said motherboard, wherein said first electromagnetic-interference shield is disposed to electromagnetically isolate said pair of first stages and wherein said second electromagnetic-interference shield is disposed to electromagnetically isolate said second stage.

14. The apparatus of claim 1, wherein said electrical power comprise first and second power sources that operate independently of each other, wherein said second power path maintains a connection between said second power source and said server while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said server while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational, and wherein said first stages are isolated from each other.

15. The apparatus of claim 1, wherein said first and second power paths share a common transformer.

16. The apparatus of claim 1, wherein said first and second power paths share a common inductor.

17. The apparatus of claim 1, wherein said first and second power paths share a common hold-up capacitor.

18. The apparatus of claim 1, wherein said apparatus is configured for providing continuity of power to said server, wherein said electrical power comprises first and second power sources that operate independently of each other, wherein said second power path maintains a connection between said second power source and said server while said second power source has sustained a fault that prevents said second power source from providing power, wherein said first power path maintains a connection between said first power source and said server while said first power source has sustained a fault that prevents said first power source from providing power, wherein said power supply retains the same configuration regardless of how many of said power sources are operational, and wherein said first stages of said first and second power paths are non-isolated from each other.

19. The apparatus of claim 1, wherein said server is a stand-alone server.

20. The apparatus of claim 1, wherein said server is a server in a data center.

21. The apparatus of claim 1, wherein said first stages of said first and second power paths each comprise a primary winding and wherein said primary windings are magnetically coupled to a secondary winding via a transformer.

22. The apparatus of claim 1, wherein said electrical power comprises power sources that work independently of each other, wherein each of said first stages of said first and second power paths comprises a transistor and a primary winding, wherein said transistor connects a corresponding one of said power sources to said primary winding, and wherein said power supply further comprises a controller that controls both of said transistors.

23. The apparatus of claim 1, wherein each of said first stages comprises a winding and a capacitor that is parallel to said winding and wherein said first stages are configured to cause said capacitors to cooperate to form a single hold-up capacitor that is shared by both said first and second power paths.

24. The apparatus of claim 1, wherein said electrical power comprises power sources that work independently of each other and wherein said power supply is configured to draw power only from whichever one of said first and second power sources offers a higher voltage.

25. The apparatus of claim 1, further comprising first and second shields disposed to surround said pair of first stages and said second stage, respectively, wherein said first and second shields have multiple apertures to promote air circulation.

26. The apparatus of claim 1, further comprising first and second heat shields disposed to surround said pair of first stages and said second stage, respectively and first and second grounded electromagnetic interference shields disposed to suppress electromagnetic interference resulting from operation of said pair of first stages and said second stage, wherein said electromagnetic interference shields and said heat shields both comprise apertures, and wherein said apertures on said electromagnetic interference shields are smaller than said apertures on said heat shields.

27. The apparatus of claim 1, wherein said pair of first stages is hot-swappable and said second stage is non-hot-swappable.

28. The apparatus of claim 1, wherein said power supply is non-hot-swappable.

29. The apparatus of claim 1, wherein said pair of first stages and said second stage are hot swappable independently of each other.

30. The apparatus of claim 1, wherein circuitry on said motherboard has an average operating temperature that is higher than that of said load.

31. The apparatus of claim 1, wherein circuitry on said motherboard has an average operating temperature that is equal to the operating temperature of the load circuitry and wherein said pair of first stages and said second stage are separately packaged.

32. The apparatus of claim 1, wherein said electrical power comprises first and second power sources and said power supply is configured to switch between said first and second power sources without the use of a mechanical transfer switch.

33. The apparatus of claim 1, wherein said motherboard comprises, in addition to said load circuitry, at least some circuitry from said power supply.

34. A method of providing continuous dc power to a server at a data center, said method comprising using a first power path, maintaining a connection between said server and a first power source, using a second power path, maintaining a connection between said server and a second power source, wherein said second power source operates independently of said first power source, and upon occurrence of an inability of said first power source to provide power, maintaining said connection to said first power source, wherein each of said power paths comprises a first stage that comprises a power-factor correction circuit, wherein said power paths share a common second stage that comprises a dc/dc converter, said first stages of said power paths collectively defining a pair of first stages that is disposed either within a package that is off a motherboard of said server or without a package and on said motherboard, and wherein said second stage is disposed either within a package that off said motherboard or without a package and on said motherboard.

Description

DESCRIPTION OF DRAWINGS

[0072] FIG. 1 shows the architecture of a power supply with power paths connected to independent ac sources for providing power to one or more loads at a data center;

[0073] FIG. 2 shows the architecture of a power supply similar to that shown in FIG. 1 but with the first stages of the two power paths in a first package and the shared second stage of the power paths on a second package;

[0074] FIG. 3 shows the architecture of a power supply similar to that shown in FIG. 1 but with the first stages of the two power paths being within the same package and the shared second stage of the power paths being on a motherboard at the load.

[0075] FIG. 4 shows the architecture of a power supply similar to that shown in FIG. 1 but with both power paths being on a motherboard at the load;

[0076] FIGS. 5-7 show power supplies in which the two isolated power paths, each of which comprises an isolated power-factor correction circuit, share a common dc/dc converter, a hold-up capacitor, and switches that are controlled by either a single controller or by two separate controllers;

[0077] FIG. 8 shows two non-isolated power paths, each of which comprises a power-factor correction circuit, that share a dc/dc transformer's magnetic core, the remainder of the dc/dc converter, and a hold-up capacitor;

[0078] FIG. 9 shows details of a configuration of capacitors for a power-factor correction circuit;

[0079] FIGS. 10-11 shows circuitry similar to that shown in FIG. 8 but with different topologies;

[0080] FIG. 12 shows function blocks for one of two ac/dc power supplies that are within one package identifying certain function blocks that can be shared between them;

[0081] FIGS. 13-15 show embodiments in which power-factor correction circuits share a common transformer;

[0082] FIGS. 16-18 show embodiments in which power-factor correction circuits share a common inductor core, a dc/dc converter, including the magnetic core of its transformer, and a hold-up capacitance that is formed by a pair of capacitors that, as a result of the circuit topology, effectively function as a single capacitor;

[0083] FIG. 19 is similar to FIG. 18 but with separate controllers for the input transistors;

[0084] FIG. 20 shows a stand-alone server with first and second power paths connected to a common ac source;

[0085] FIG. 21 shows an exemplary architecture for a dual-path power supply that supplies power to a stand-alone server;

[0086] FIG. 22 shows an architecture similar to that shown in FIG. 21 but with the second stage being on the motherboard of the stand-alone server;

[0087] FIG. 23 shows an architecture similar to that shown in FIG. 22 but with the first and second stages both being on the motherboard of the stand-alone server;

[0088] FIG. 24 shows an isometric view of a motherboard with a power supply mounted thereon; and

[0089] FIG. 25 shows the power supply of FIG. 24 with shields disposed around the pair of first stages and the second stage.

DETAILED DESCRIPTION

[0090] FIG. 1 shows a dual-input power supply 10 that provides a first power path 12 and a second power path 14. The first power path 12 receives ac power from a first ac source 16. The second power path 14 receives ac power from a second ac source 18. Both the first power path 12 and the second power path 14 ultimately deliver power to a load 20 in a data center 22. Examples of a load 20 include a server, including a stand-alone server, a router, a switcher, and combinations thereof.

[0091] The power supply 10 includes a first converter 24 along the first power path 12 and a second converter 26 along the second power path 14. Each of the first and second converters 24, 26 is an ac/dc power converter.

[0092] The first converter 24 includes a first stage 28 and a second stage 30.

[0093] The first stage 28, which is often referred to as a “power-factor correction stage, converts ac received from the first ac source 16 into dc, which it then provides to the second stage 30. The second stage 30 transforms the dc that it receives from the first stage 28 into a dc voltage having the value required by the load 20. In the embodiments described herein, the second stage 30 comprises a dc/dc converter.

[0094] The second converter 26 includes first and second stages like the first converter 24. Accordingly, only the first and second stages 28, 30 of the first converter 24 are illustrated in FIG. 1. The first and second power paths 12, 14 share at least the same second stage 30.

[0095] In the embodiment shown in FIG. 1, the first and second stages 28, 30 are inside a first package 32.

[0096] In an alternative embodiment, shown in FIG. 2, the first stage 28 of the first power path 12 is within the first package 32 and the first stage of the second power path 14 is also within the first package 32. The shared second stage 30 of the first and second power paths 12, 14 is within a second package 34. This configuration is advantageous because the expected lifetime of the second stage 30 is much greater than that of the first stage 28.

[0097] In another embodiment, shown in FIG. 3, the first stage 28 of the first power path 12 is within the first package 32 and the first stage 28 of the second power path 14 is also within the first package 32. The shared second stage 30 of the first and second power paths 12, 14 is on a motherboard 35 that also holds circuitry 37 of the load 20. This offers the advantages of the architecture shown in FIG. 2 but with the additional advantage of avoiding loss due to connectors between the second package 34 and the load 20.

[0098] In another embodiment, shown in FIG. 4, the first stage 28 of the first power path 12, and the shared second stage 30 of the first and second power paths 12, 14 are all on a motherboard 35 that also holds circuitry 37 of the load 20. This offers the advantages of the architecture shown in FIG. 3 with the additional advantage of avoiding loss due to connectors between the first package 32 and the second package 34.

[0099] FIG. 5 shows a power supply 10 having first and second inputs 36, 38 for connection to the first and second ac sources 16, 18, respectively. The power supply 10 further includes an output 40 for connection to the load 20 (not shown). The first and second converters 24, 26 each have a first stage 28. The two first stages 28 are isolated from each other. As a result, it is not possible for a short circuit to develop between the first and second ac sources 16, 18.

[0100] The first and second converters 24, 26 share a second stage 30 and a hold-up capacitor C1. In some embodiments, a single controller connects to the gate terminals through an isolated driver of first and second transistors Q1, Q2. In other embodiments, each of the first and second transistors Q1, Q2 has its own gate controller. In either case, current flow through corresponding first and second transformers T1, T2 is controlled.

[0101] In the illustrated embodiment, and in all other embodiments described herein, the hold-up capacitor is an electrolytic capacitor.

[0102] Throughout this specification, reference will be made to operation of the circuitry in response to failure of one of the first and second ac sources 16, 18. In each case, because of the symmetry of the circuits, operation will proceed in an analogous manner upon failure of the other of the first and second ac sources 16, 18.

[0103] In FIG. 5, the first stage 28 comprises a power-factor correction circuit having a flyback topology. However, alternative topologies are possible. For example, FIG. 6 shows a power supply 10 similar to that shown in FIG. 5 but with the first stage 28 having a fly-forward topology instead of a flyback topology. FIG. 7 shows a power supply 10 similar to that shown in FIG. 5 but with its first stage 28 having a forward topology instead of a flyback topology.

[0104] When both the first and second ac sources 16, 18 are operational, the power supply 10 sees both voltages. In effect, each ac source 16, 18 offers the power supply 10 some power. The power supply 10 cannot, however, accept both offers. To do so would result in too much power at the load 20. Thus, the power supply 10 must have a way to accept one offer and reject the other. For ease of discussion, it is assumed that power is being drawn from the first ac source 16.

[0105] If the second ac source 18 were to fail, the power supply 10 would simply continue to draw from the first ac source 16 just as it has all along.

[0106] If, on the other hand, the first ac source 16 were to fail, then the first ac source 16 would no longer offer the higher of the two voltages. Thus, the power supply 10 would begin drawing current from the second power supply 22. This happens automatically, simply as a result of the circuit's topology. Accordingly, in principle it would not be necessary to have transistors Q1, Q2.

[0107] The first and second converters 24, 26 shown in FIGS. 5-7 share only a second stage 30 and a hold-up capacitor C1. They continue to have separate first and second transformers T1, T2. These transformers T1, T2 are physically large and consume significant area in the actual circuit.

[0108] The embodiments shown in FIGS. 8-10 overcome this disadvantage by providing a way to, in effect, share the first and second transformers T1, T2. Instead of each power path 12, 14 having its own transformer T1, T2, each power path 12, 14 has a primary winding 44, 46 that couples to a common transformer T1. This shared transformer T1 couples both of the first stages 30 to the shared second stage 30. Since the transformers T1, T2 are physically quite large, sharing a transformer T1 as shown in FIGS. 5-7 offers a significant savings in space.

[0109] A byproduct of sharing the transformer T1 is that the first stages 30 of the first and second converters 24, 26 are no longer isolated from each other. As a result, it is no longer possible to automatically rely on small voltage differences at the first and second ac sources 16, 18 as a basis for choosing which of the first and second ac sources 16, 18 current will be drawn from for an extended period. Accordingly, this embodiment requires a slightly different approach to control.

[0110] The embodiment shown in FIG. 8 features a first transistor Q1 that controls current in a first primary winding 44 and a second transistor Q2 that controls current through a second primary winding 46. A single gate controller 41 controls both the first and second transistors Q1, Q2. As a result, the first and second transistors Q1, Q2 receive control signals concurrently. This is an important feature because it enables the first and second transistors Q1, Q2 to change state concurrently. As used herein, “concurrently” means an interval that is short enough so that the effect of a time difference is undetectable at the output 40. Since the first and second transistors Q1, Q2 work concurrently, the voltages on the hold-up capacitors C1, C2 are same, regardless of the input sources' conditions. As a result, the hold-up capacitors C1 and C2 work together and function effectively as a single large hold-up capacitance, regardless of the input sources' respective conditions.

[0111] Within the first stage 28, an element that is particularly likely to fail is the input electrolytic capacitor C1, which can be seen in FIG. 8 as being connected in parallel to the primary winding 44 and as also sustaining a maximum voltage that is equal to that of the first ac source 16.

[0112] To promote reliability, it is useful to replace the input electrolytic capacitor C1 with plural input capacitors C1-C7, each of which is connected to a primary winding of corresponding transformer T1-T7 with the primary windings cascaded and with the secondary windings of the transformers T1-T7 tied together.

[0113] Each capacitor C1-C7 sustains a voltage that is a fraction of the maximum voltage of the first ac source 16, the fraction being the reciprocal of the number of such capacitors C1-C7. As a result, the capacitors C1-C7 need not be rated to sustain a particularly high voltage.

[0114] An advantage of electrolytic capacitors is that the capacitor plates are highly variegated and thus offer considerable surface area for storage of charge within a small volume. This makes them particularly useful for power supplies, in which a space is at a premium and considerable amounts of charge must be stored. However, electrolytic capacitors are notoriously short-lived in part because the insulation between the plates dries out over time.

[0115] The configuration shown in FIG. 9 permits the notoriously unreliable electrolytic capacitors C1, C2 shown in FIG. 8 to be replaced with more reliable ceramic capacitors. This results in a more reliable and long-lived first stage 28.

[0116] An additional advantage of the first stage 28 shown in FIG. 9 is that individual transformers T1-T7 are much smaller than the transformer T1 shown in FIG. 8. This is useful because machines that pick and place components onto a printed-circuit board are better suited for manipulating smaller components.

[0117] FIGS. 10 and 11 shows a configuration similar to that shown in FIG. 8 but with the circuitry between the transformer T1 and the second stage 30 having a flyback topology and a forward topology, respectively, instead of the fly-forward topology shown in FIG. 8.

[0118] In all embodiments shown in FIGS. 8, 10, and 11, the respective states of the first and second input transistors Q1, Q2 will depend on the availability of the first and second ac sources 16, 18. If both the first and second ac sources 16, 18 are available, the first and second transistors Q1, Q2 will be in opposite states, with one being conductive and the other being non-conductive will be in a conducting state while the other will be in a non-conductive state.

[0119] FIG. 12 shows various components that are associated with but not part of a power path 12. A number of these components are susceptible to being shared between first and second power paths 12, 14. By sharing one or more of these components, it is possible to reduce part count of the overall power supply 10 as well as to increase its power density.

[0120] In some embodiments, the power supply 10 comprises internal components that are not along the power path itself. These include various controllers, such as the gate controller 41 and a PWM controller 54, input monitoring circuitry 56, output monitoring circuitry 58, surge-protection circuitry 60, a fan power supply 62 for providing a dc voltage, usually twelve volts, to power a fan motor, a bias power supply 64 for providing a constant dc voltage, usually five volts, for use by any other digital circuitry that may be used within the data center, feedback circuitry 66 that connects to the load 20, a thermal sensor 68 for monitoring the fan's operating temperature and providing an input for adjusting the fan motor's duty cycle, and overload protection circuitry 70 connected to the output 40.

[0121] In some embodiments, the first and second power paths 12, 14 share the housekeeping circuitry 52 that provides power to one or more of the foregoing components. Embodiments include those in which the housekeeping circuitry 52 is split between primary and secondary sides of a transformer that couples the first and second stages 28, 30.

[0122] In the embodiments of FIGS. 13-15, the first and second power paths 12, 14 share a common transformer T1 and a common second stage 30. Depending on the topology of diodes D1, D2 between the transformer T1 and the second stage 30, the first stage 28 has a forward topology, as shown in FIG. 13, a fly-forward topology, as shown in FIG. 14, or a flyback topology, as shown in FIG. 15.

[0123] In the embodiments shown in FIGS. 13-15, the respective states of the first and second input transistors Q1, Q2 will depend on the availability of the first and second ac sources 16, 18. If both the first and second ac sources 16, 18 are available, the first and second transistors Q1, Q2 will be in opposite states, with one being conductive and the other being non-conductive will be in a conducting state while the other will be in a non-conductive state.

[0124] FIG. 16 shows a first ac source 16 that is coupled to a first power path 12 and a second ac source 18 that is coupled to a second power path 14. Each of the first and second power paths 12, 14 has a corresponding first stage 28 to which a corresponding one of the first and second ac sources 16, 18 is coupled. An inductor L1 couples the first stages 28 of the first and second power paths 12, 14 to each other. As a result, the first stages 28 are not isolated from each other.

[0125] The first power path's first stage 28 has a first power-path primary winding 44 and a corresponding first-power-path output capacitor C1. The first power-path output capacitor C1 is connected parallel to the first-power-path primary winding 44.

[0126] The first power path's first stage 28 also has a first power-path input transistor Q1 and a first-power-path output transistor Q3. The first power-path input transistor Q1 connects to the negative side of the first-power-path primary winding 44 by way of the first-power-path output transistor Q3 and to the positive side of the first-power-path primary winding 44 by way of a first power-path diode D1 that is biased to permit current from the inductor L1 to the first-power-path primary winding 46.

[0127] The second power path's first stage 28 has a second power-path primary winding 46 and a corresponding second-power-path output capacitor C2. The second power-path output capacitor C2 is connected parallel to the second-power-path primary winding 46.

[0128] The second power path's first stage 28 also has a second power-path input transistor Q2 and a second-power-path output transistor Q4. The second power-path input transistor Q2 connects to the negative terminal of the second-power-path primary winding 46 by way of the second-power-path output transistor Q4 and to the positive terminal of the second-power-path primary winding 46 by way of a second-power-path diode D2 that is biased to permit current from the inductor L1 to the second-power-path primary winding 46.

[0129] A first controller 41 controls the gate of the first power-path input transistor Q1 and the gate of the second-power-path input transistor Q2. The respective states of the first-power-path input transistor Q1 and the second-power-path input transistor Q2 depend on the availability of the first and second ac sources 16, 18. If both the first and second ac sources 16, 18 are available, the first-power-path input transistor Q1 and the second-power-path input transistor Q2 will be in opposite states in which one is in a conducting state and the other is in a non-conducting state. Since the first controller 41 controls the gates of both transistors Q1, Q2, it is possible to reliably cause both transistors Q1, Q2 to transition between conductive and non-conductive states at substantially the same time.

[0130] A second controller 50 controls the gate of the first power-path output transistor Q3 and the gate of the second-power-path output transistor Q4. This permits concurrent control of the first power-path output transistor Q3 and of the second-power-path output transistor Q4.

[0131] In the embodiments of FIGS. 16-19, two first stages 28 of the first and second power paths 12, 14 share a common inductor core L1, and a transformer T1. While it may not be immediately apparent, the novel topology of the first and second power paths 12, 14, and in particular, the concurrent operation of the output transistors Q3, Q4, causes the first power-path output capacitor C1 and the second-power-path output capacitor C2 to work together to form what is effectively a single hold-up capacitor that is shared by both of the two first stages 28. This shared hold-up capacitor is formed by the combination of the first power-path output capacitor C1 and the second-power-path output capacitor C2.

[0132] The illustrated topology forms a shared hold-up capacitor by clamping the voltages across the first power-path output capacitor C1 and the second-power-path output capacitor C2 to each other. This causes the first and second power paths 12, 14 to, in effect, share what is electrically the equivalent of a single hold-up capacitor that is formed by the first power path's output capacitor C1 and the second power path's output capacitor C2. This virtual hold-up capacitor holds enough charge to support current during the brief interval required to transition from the state in which both of the first and second ac sources 16, 18 are available and the state in which power is available from only one of the first and second ac sources 16, 18.

[0133] Because the output capacitors C1, C2 effectively form a single capacitor, the first stages 28 of the first and second power paths 12, 14 effectively share a common hold-up capacitor. As a result, the output capacitors C1, C2 can be made half as large as they would have had to be had they not been configured to cooperate as a single hold-up capacitor.

[0134] FIG. 18 also shows downstream circuitry 72 that extends between the secondary winding 48 of the transformer T1 and the power supply's output 40. In FIG. 18, the downstream circuitry 72 is configured with a forward topology. FIG. 19 shows an embodiment identical to that if FIG. 18 but with the downstream circuitry 72 having been configured with a fly-forward topology. FIG. 20 shows an embodiment identical to that if FIG. 18 but with the downstream circuitry 72 instead having been configured with a fly-flyback topology.

[0135] FIG. 19 shows an embodiment similar to that shown in FIG. 18 but with the first controller 41 controlling only the second power-path input transistor Q2. A third controller 74 controls the first-power-path input transistor Q1.

[0136] In the embodiment shown in FIG. 19, the states of the first-power-path input transistor Q1 and the second power-path input transistor Q2 depend on the availability of the first and second ac sources 16, 18. If only one the first ac source 16 is available, then only the first-power-path input transistor Q1 will be in a conducting state. If only the second ac source 18 is available, then only the second power-path input transistor Q2 will be in a conducting state. If both the first and second ac sources 16, 18 are available, the first-power-path input transistor Q1 and the second power-path input transistor Q2 will be in opposite states with one being in a conducting state and the other being in a non-conducting state. The choice of which one is in a conducting state and which one is in a non-conducting state is arbitrary.

[0137] The architectural principles set forth in connection with FIGS. 1-4 are applicable to a dual-input power supply 10 in which both inputs are connected to the same ac power source 16. As an example, FIG. 20 shows a stand-alone server 76 with two power supplies operating in tandem, each of which connects to the same ac power source 16. The two power supplies continue to define first and second power paths 12, 14, each of which comprises first and second stages 28, 30 as already described above. The main distinction is that the first and second power paths 12, 14 connect to the same ac source 16.

[0138] Because the lifetime of a conventional power supply is less than that of the stand-alone server 76 to which it supplies power, it is expected that at some point, the first power path 12 will fail. In such cases, the second power path 14 can carry the burden of supplying power by itself, but only for a limited period. Failure of the first power path 12 thus triggers an alert to a human operator, who then hot-swaps the failed first power path 12 with a new first power path 12.

[0139] Within a power supply 10, the expected lifetimes of the various components are not identical. In fact, the second stage 30, which comprises the dc/dc converter, has a much longer expected lifetime than the first stage 28, which comprises the power-factor correction circuit.

[0140] Given the differential in expected lifetimes, it is useful to provide the stand-alone server 76 with an architecture along the lines of that shown in FIG. 21, in which the first stage 28 is within its own first package 32 and the second stage 30 is within its own second package 34. This permits the first package 32 to be hot-swapped independently of the second package 34.

[0141] Because the expected lifetime of the second package 34 is comparable to that of the stand-alone server 76, it is useful to modify the architecture shown in FIG. 21 to place the second stage 30 directly on the motherboard 35 of the stand-alone server 76, as shown in FIG. 22. In this case, only the first stage 28 is in its own package 32 since it is only the first stage 28 that may need to be replaced.

[0142] In a passively-cooled power supply 10, the expected lifetime of the first stage 28 approaches that of the stand-alone server 76 to which it supplies power.

[0143] As used herein, a passively-cooled power supply 10 is one that relies, in normal operation, primarily on conduction of heat from power-handling units rather than from a fan. Such a power supply 10 can include a fan for use in emergencies, with the fan being controlled by a controller that receives a temperature signal from a heat sensor. However, in such a power supply 10, years can go by without the fan ever having to be turned on.

[0144] In such cases, where the expected lifetime of the first stage 28 is sufficiently long, an architecture similar to that shown in FIG. 23 is useful. In this architecture, the first stage 28 and second stage 30 are both on the motherboard 35 of the stand-alone server 76.

[0145] An isometric view of a typical motherboard 35 with a power supply 10 mounted thereon can be seen in FIG. 24. Since the power supply 10 generates considerable heat during operation, it is useful to provide a first heat sink 78 in thermal communication with the switches 80 and transformers 82 of the first stage 28 and a second heat sink 84 in thermal communication with the second stage 30.

[0146] An embodiment as shown in FIGS. 23 and 24 is particularly useful because the power supply 10 no longer needs to be designed as a hot-swappable module. Placement of the first and second stages 28, 30 on the motherboard 35 thus reduces space required to accommodate the circuitry and also reduces costs.

[0147] A motherboard 35 normally contains circuitry 37 that does not operate at high temperatures. As a result, those who handle motherboards 35 do so with the expectation that the circuitry 37 is relatively safe to handle.

[0148] The inclusion of the power supply 10 on the motherboard 35 as shown in FIG. 23 changes this. Circuitry associated with a power supply 10 operates at elevated temperatures and at high voltages, thereby raising the average operating temperature of circuitry on the motherboard 35. Moreover, a power supply's rapid switching and high current levels combine to cause considerable electromagnetic interference. This can interfere with nearby circuitry 37 on the motherboard 35. As a result, it is useful to include additional components to provide some protection against both of these hazards.

[0149] FIG. 25 shows the motherboard 35 shown in FIG. 24 but with the first stage 28 and second stage 30 having been shielded by corresponding first and second shields 86, 88. In the illustrated embodiment, the first shield 86 is a grounded EMI shield that protects the load circuitry 37 against interference and also protects service personnel from shock and from inadvertently touching the components of the first stage 28. The second shield 86 is a heat shield that protects service personnel from inadvertently touching the components of the second stage 30.

[0150] In the foregoing embodiments, the power supply 10 has been shown to receive power from one or more ac sources 16, 18. However, in some embodiments, the power supply 10 receives dc power from one or more dc sources. Such dc sources are typically maintained at a high voltage, such as two hundred to four hundred volts. In such embodiments, the dc power essentially passes through the first stage 28 and maintains a voltage at a hold-up capacitor that provides a voltage for the second stage 30, which comprises the dc/dc converter.

[0151] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the appended claims. Other embodiments are within the scope of the following claims.