Abstract
Methods and devices for speeding up the onset of a target current through an output leg of a current mirror are presented. Upon activation of the current mirror, a pre-charge current is sourced to a node of the current mirror that is common to the output leg and an input leg of the current mirror. Sourcing of the pre-charge current is based on sensing, by a first transistor, of a voltage at the common node. Pre-charging of the common node continues up to a cutoff voltage sensed at the common node. Sourcing of the pre-charge current is provided by a second transistor coupled to the common node. Based on the voltage sensed at the common node, the first transistor controls the sourcing of the pre-charge current by the second transistor. Such control is based on a portion of a current from a current source that flows through the first transistor.
Claims
1. A circuital arrangement, comprising: a main current mirror comprising an input leg and an output leg, the input leg coupled to the output leg through a first common node of the main current mirror; and a pre-charging circuit coupled to the first common node, the pre-charging circuit comprising: a first transistor coupled to the first common node, the first transistor configured to sense a voltage at the first common node; and a second transistor coupled to the first common node, the second transistor configured to source a pre-charge current to the first common node based on a voltage sensed at the first common node by the first transistor.
2. The circuital arrangement of claim 1, wherein: operation of the main current mirror comprises an active state and an inactive state, and the second transistor is configured to source the pre-charge current only during a portion of a transition phase between the inactive state and the active state.
3. The circuital arrangement of claim 2, wherein: the active state is defined by steady state voltage at the first common node for a flow of a target current through the output leg, and during the transition phase, the pre-charge current charges the first common node to a pre-charge voltage that is near and below the steady state voltage.
4. The circuital arrangement of claim 3, wherein: the first transistor comprises a gate coupled to the first common node, and the second transistor comprises a source coupled to the first common node.
5. The circuital arrangement of claim 4, wherein: the first transistor is configured as a common-source transistor, and the second transistor is configured as a common-drain transistor.
6. The circuital arrangement of claim 5, wherein: a drain of the first transistor is coupled to a gate of the second transistor.
7. The circuital arrangement of claim 6, wherein: the pre-charging circuit further comprises a current source coupled to the drain of the first transistor and to the gate of the second transistor.
8. The circuital arrangement of claim 7, wherein: the pre-charging circuit further comprises a series connected resistor coupled between the current source and the drain of the first transistor.
9. The circuital arrangement of claim 8, wherein: during the transition phase, a current that flows from the current source through the drain of the first transistor causes a voltage drop across the series connected resistor that turns ON the second transistor.
10. The circuital arrangement of claim 8, wherein: when the first common node is at a voltage that is equal to, or larger than, the pre-charge voltage, a current that flows from the current source through the drain of the first transistor causes a voltage drop across the series connected resistor that turns OFF the second transistor.
11. The circuital arrangement of claim 7, wherein: a size of the first transistor is such that when the first common node is at a voltage that is equal to, or larger than, the pre-charge voltage, a totality of a current from the current source flows through the first transistor.
12. The circuital arrangement of claim 11, wherein: the size of the first transistor and sizes of transistors of the main current mirror are ratiometrically related.
13. The circuital arrangement of claim 11, wherein: the current from the current source and a current that flows through the input leg of the main current mirror are mirrored from a same reference current.
14. The circuital arrangement of claim 1, wherein: the first transistor and the second transistor are coupled to the first common node through a resistor.
15. The circuital arrangement of claim 1, wherein: the first transistor and the second transistor are coupled to the first common node through a series connected resistor coupled to a shunted capacitor.
16. The circuital arrangement of claim 1, further comprising: a switching arrangement coupled to the first common node, the switching arrangement configured to short the first common node during an inactive state of the main current mirror.
17. The circuital arrangement of claim 1, wherein: the input leg comprises a diode-connected common-source transistor comprising a gate that is coupled to the first common node, the output leg comprises a common-source transistor comprising a gate that is coupled to the first common node, and the common-source transistor of the input leg and the common-source transistor of the output leg are ratiometrically related.
18. The circuital arrangement of claim 17, wherein: the output leg further comprises one or more cascode transistors in series connection with the common-source transistor of the output leg, the input leg further comprises one or more diode-connected transistors in series connection with the common-source transistor of the input leg, and gates of the one or more cascode transistors of the output leg are coupled to respective gates of the one or more diode-connected transistors of the input leg at respective one or more common nodes of the main current mirror.
19. The circuital arrangement of claim 17, wherein: the pre-charging circuit further comprises one or more transistors, each transistor of the one or more transistors coupled to a respective node of the one or more common nodes, and the each transistor is configured to source a pre-charge current to the respective node based on the voltage sensed at the first common node by the first transistor.
20. The circuital arrangement of claim 1, wherein: the output leg is a conduction path of a radio frequency (RF) amplifier that is configured to amplify an RF signal coupled to the first common node.
21. The circuital arrangement of claim 1, wherein: the pre-charging circuit further comprises a current source, and the first transistor is configured to drain a current from the current source with a current magnitude that increases based on an increase of the volage sensed at the first common node by the first transistor.
22. The circuital arrangement of claim 21, wherein: during an inactive state of the main current mirror, a voltage at the first common node is about zero volts and the first transistor is turned OFF, during a transition from the inactive state to an active state, the pre-charge current gradually charges the first common node which causes the first transistor to gradually turn ON with a gradual increase of the current magnitude drained by the first transistor, and when the first common node is charged to a cutoff voltage, the current magnitude drained by the first transistor causes the second transistor to turn OFF.
23. The circuital arrangement of claim 1, wherein: the first transistor, the second transistor, and transistors of the main current mirror comprise metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).
24. The circuital arrangement of claim 23, wherein: said transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).
25. An electronic module comprising the circuital arrangement of claim 1.
26. A method, comprising: using the electronic module of claim 25 in one or more electronic systems comprising: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a radio, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.
27. A method for reducing a transition phase between an inactive state and an active state of a current mirror, the method comprising: sensing, via a first transistor, a voltage at a common node to an input leg and an output leg of the current mirror; based on the sensing, controlling a second transistor to source a pre-charge current to the common node; based on the controlling, speeding up charging of the common node up to a cutoff voltage that is near and below a steady state voltage at the common node; and charging the common node to the steady state voltage via a current through the input leg of the current mirror, thereby causing onset of a target current through the output leg for operation of the current mirror according to the active state.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
[0013] FIG. 1A shows a prior art configuration of an N-type current mirror.
[0014] FIG. 1B shows an extension of the prior art configuration of FIG. 1A for a case of a cascoded configuration.
[0015] FIG. 1C shows a switching arrangement for activation and deactivation of the current mirror of FIG. 1A.
[0016] FIG. 1D shows a prior art configuration of a P-type current mirror that can be used to provide a reference current to the N-type current mirror of FIG. 1A.
[0017] FIG. 2 shows a block diagram of a pre-charging circuit according to an embodiment of the present disclosure used to speed up operation of an N-type current mirror.
[0018] FIG. 3A shows an embodiment according to the present disclosure of the pre-charging circuit of FIG. 2.
[0019] FIG. 3B shows another embodiment according to the present disclosure of the pre-charging circuit of FIG. 2.
[0020] FIG. 3C shows an embodiment according to the present disclosure of the pre-charging circuit of FIG. 2 comprising a resistor to generate a current.
[0021] FIG. 3D shows an embodiment according to the present disclosure of the pre-charging circuit of FIG. 2 comprising a current mirror to generate a current.
[0022] FIG. 3E shows an embodiment according to the present disclosure of the pre-charging circuit of FIG. 2 comprising a switching arrangement for activation and deactivation of the pre-charging circuit.
[0023] FIG. 4 shows an embodiment according to the present disclosure of a pre-charging circuit used to speed up operation of the cascoded configuration of FIG. 1B.
[0024] FIG. 5 shows a block diagram of a pre-charging circuit according to an embodiment of the present disclosure used to speed up operation of an N-type current mirror while controlling a timing of a pre-charge current burst.
[0025] FIG. 6 is a process chart showing various steps of a method according to the present disclosure for reducing a transition phase between an inactive state and an active state of a current mirror.
[0026] Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
[0027] FIG. 2 shows a block diagram of a pre-charging circuit (220) according to an embodiment of the present disclosure used to speed up operation of the prior art current mirror (M.sub.N10, M′.sub.N10, I.sub.REF) described above with reference to FIG. 1C. The pre-charging circuit (220) is an active circuit that includes active devices, such as, for example, transistors M.sub.N20 and M.sub.N21. As shown in FIG. 2, the pre-charging circuit (220) may operate within a same voltage domain as the current mirror (M.sub.N10, M′.sub.N10, I.sub.REF), the voltage domain defined by the supply voltage, V.sub.DD, and the reference ground. The pre-charging circuit (220) is coupled to the node N.sub.10 of the current mirror (M.sub.N10, M′.sub.N10, I.sub.REF) and therefore to the gates of the transistors M.sub.N10 and M′.sub.N10. In case the current mirror includes a cascode configuration such as one described with reference to FIG. 1B described above, the pre-charging circuit (220) may further be coupled to nodes (N.sub.11, . . . , etc.) that connect respective gates of the main (M.sub.N10, M.sub.N11, . . . , etc.) and replica (M′.sub.N10, M′.sub.N11, . . . , etc.) circuits.
[0028] According to an embodiment of the present disclosure, coupling of the pre-charging circuit (220) of FIG. 2 to the node, N.sub.10, of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF) allows a transistor (M.sub.N20) of a sensing circuit (220a) of the pre-charging circuit (220) to sense a level of a voltage at the coupled node, N.sub.10. According to an embodiment of the present disclosure, the sensing circuit (220) controls operation of a current sourcing circuit (220b) based on the level of the voltage sensed at the coupled node, N.sub.10. According to an embodiment of the present disclosure, the current sourcing circuit (220b) includes a transistor (M.sub.N21) that is coupled to the node, N.sub.10. Under control of the sensing circuit (220), the transistor (M.sub.N21) may charge the node N.sub.10 via a pre-charge current, I.sub.PC10, or a burst of a pre-charge current, I.sub.PC10.
[0029] According to an embodiment of the present disclosure, when activated, the pre-charging circuit (220) may be used to pre-charge the node N.sub.10 to a pre-charge voltage that is near, but lower than, a steady state voltage at the node N.sub.10 during normal operation of the current mirror (M.sub.N10, M′.sub.N10, I.sub.REF). Once the pre-charge voltage is reached, the pre-charging circuit (220) may stop provision (e.g., sourcing) of the pre-charge current, I.sub.PC10, to the node N.sub.10, with a reduced effect on operation of the current mirror (M.sub.N10, M′.sub.N10, I.sub.REF). Accordingly, the pre-charge voltage may be considered as a cutoff voltage of the pre-charging circuit (220). Once the pre-charge current I.sub.PC10 stops flowing, the node N.sub.10 continues to charge up to the steady state voltage solely based on the reference current I.sub.REF. Accordingly, reduction in the charging time of the node N.sub.10 is obtained by provision of the pre-charge current, I.sub.PC10, provided as a burst of current, which in combination with the reference current, I.sub.REF, speed up charging of the node N.sub.10 from zero volts (instant right after activation) to the pre-charge voltage, and therefore (substantially) reduce a time during which the node N.sub.10 is (slowly) charged solely via the reference current, I.sub.REF. In case of coupling to a plurality of nodes (e.g., N.sub.10, N.sub.11, . . . , etc. of FIG. 1B), the sensing circuit (220a) may control a plurality of current sourcing circuits (e.g., 220b) each including a transistor (e.g., M.sub.N21) coupled to a respective node of the plurality of nodes for provision of a respective pre-charge current. Such control of the plurality of current sources may be based to a voltage sensed at a single node (e.g., node N.sub.10) by the sensing circuit (220a).
[0030] According to an embodiment of the present disclosure, the (a level of the) pre-charge voltage may be adjustable. Adjusting of the pre-charge voltage may be provided via a resistor, a size of a transistor, a ratio of sizes of two transistors, or any combination thereof. According to an exemplary embodiment of the present disclosure, the ratio of the sizes of the two transistors may be with respect to a transistor of the pre-charging circuit (e.g., M.sub.N20 of FIG. 2) and a transistor of the current mirror (e.g., M.sub.N10, M′.sub.N10 of FIG. 2, or M.sub.P10 of FIG. 1D). According to a further embodiment of the present disclosure, the pre-charge voltage may be selected based on a desired magnitude of the current (I.sub.OUT) through the output leg (e.g., M.sub.N10 of FIG. 2) during a transition state/phase from a deactivated state to an activated (steady state) state of the current mirror (M.sub.N10, M′.sub.N10, I.sub.REF). Various relationships between sizes of devices, currents through the devices and biasing voltages to the devices for establishing operation of the pre-charging circuit (220) for a given/desired pre-charge voltage may be obtained via circuit simulation software and/or experimental testing according to well-known in the art systems and procedures, description of which is beyond the scope of the present disclosure.
[0031] A sequence of events for pre-charging the node N.sub.10 via the pre-charging circuit (220) of FIG. 2 may include: upon activation of the current mirror (M.sub.N10, M′.sub.N10, I.sub.REF) via, for example, the control signal, /Ena, (optionally) activating the pre-charging circuit (220); sensing a voltage level at the node N.sub.10 via the sensing circuit (220a); controlling the current sourcing circuit (220b) to start a burst of pre-charge current, I.sub.PC10, into the node N.sub.10; further controlling the current sourcing circuit (220b) to maintain sourcing of the pre-charge current, I.sub.PC10, so long the sensed voltage at the node N.sub.10 is smaller than the pre-charge voltage; and to control the current sourcing circuit (220b) to stop the burst of the pre-charge current, I.sub.PC10, when the sensed voltage at the node N.sub.10 is equal to, or larger than, the pre-charge voltage. It should be noted that activation of the pre-charge circuit (220) may be optional as in some exemplary configurations, presence of a current required for activation of the pre-charge circuit (220) may be enslaved to the activation of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF) itself, and therefore activation of the pre-charge circuit (220) may inherently be provided via activation of the current mirror. Furthermore, it should be noted that when inactive, the pre-charging circuit (220) may not consume any current/power.
[0032] FIG. 3A shows an exemplary embodiment according to the present disclosure of a pre-charging circuit (220A) which can be used as the pre-charging circuit (220) described above with reference to FIG. 2, including the transistor M.sub.N20 used for sensing of the voltage level at the node N.sub.10, and the transistor M.sub.N21 used to source the pre-charge current, I.sub.PC10, to the node N.sub.10. As can be seen in FIG. 3A, the transistor M.sub.N20 comprises a gate that is coupled (connected) to the node N.sub.10; a source that is coupled to the reference ground; and a drain that is coupled, through a node, N.sub.21, to a current source, I.sub.20, and to a gate of the transistor M.sub.N21. A source of the transistor M.sub.N21 is coupled to the node N.sub.10, and a drain of the transistor M.sub.N21 is coupled to the supply voltage V.sub.DD through a resistor R.sub.21.
[0033] An optional DC charging element (340) may be coupled to the node N.sub.21 as shown in FIG. 3A. The optional element (340) may be used to control/set a DC voltage at the gate of the transistor M.sub.N21 via a flow of a portion of the current from the current source I.sub.20 through the node N.sub.21. In the exemplary implementation shown in FIG. 3A, the optional element (340) may be a capacitor C.sub.21 that can charge the node N.sub.21. In another exemplary implementation shown in FIG. 3B, the optional element (340) may be one or more series-connected diodes (e.g., diode-connected N-type transistors M.sub.N25, M.sub.N26) that can charge the node N.sub.21 up to a voltage determined by the diodes thereby allowing some type of the overvoltage protection of the transistor M.sub.N21 (as well as the transistor M.sub.N20).
[0034] With continued reference to FIG. 3A, a person skilled in the art would recognize that the transistor M.sub.N20 is arranged as a common-source configuration so that based on a level of the voltage at node N.sub.10, a current may flow from the (series-connected) current source, I.sub.20, through the transistor M.sub.N20. When fully ON, a maximum current though the transistor M.sub.N20 may be limited by the size of the transistor and the current sourced by the current source I.sub.20. On the other hand, a person skilled in the art would recognize that the transistor M.sub.N21 is arranged as a source follower (common-drain configuration), so that based on a voltage difference between the gate and source (i.e., gate-to-source voltage) of the transistor M.sub.N21, a current, I.sub.PC10, may flow from the supply voltage V.sub.DD to the node N.sub.10 through the resistor R.sub.21 and the transistor M.sub.N21.
[0035] As shown in FIG. 3A, the current source I.sub.20 is controllable via a control signal Ctr.sub.20 configured to activate and deactivate sourcing of a current through the current source I.sub.20. Such control of the current source I.sub.20 may be synchronized to the active and inactive states of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2 controllable via control signal/Ena). For example, when the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2) is inactive, the current source I.sub.20 may be controlled not to source/output any current (i.e., current source is inactive), and when the current mirror is active, the current source I.sub.20 may be controlled to source/output a current (i.e., current source is active).
[0036] During the inactive state of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2 with/Ena at a high level), the node N.sub.10 shown in FIG. 3A is shorted to the reference ground and therefore is at about zero volts. Furthermore, during the inactive state of the current mirror, the current source I.sub.20 is also inactive. It follows that during the inactive state, no current flows through either of the transistor M.sub.N20 or the node N.sub.21. Accordingly, the gate-to-source voltage of the transistor M.sub.N21 is also at about zero volts and therefore no current (i.e., I.sub.PC10=0) is sourced into the node N.sub.10 through the transistor M.sub.N21.
[0037] During the active state of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2 with/Ena at a low level), the node N.sub.10 shown in FIG. 3A is not shorted to the reference ground and therefore can charge, at least through the reference current, I.sub.REF. At an instant immediately after switching states from the inactive to the active state, the node N.sub.10 is still close to the zero volts and therefore no current flows through the transistor M.sub.N20 as the transistor M.sub.N20 is turned OFF. However, since the current source I.sub.20 is activated (active, active state, sources current), a current starts to flow from the current source I.sub.20 to charge the node N.sub.21 at a rate that is much faster than the rate of charge of the node N.sub.10. In turn, the node N.sub.21 charges at a level that allows tuning ON of the transistor M.sub.N21 and therefore allows flowing of the pre-charge current I.sub.PC10 into the node N.sub.10 which in turn speeds up the charging of said node. As the node N.sub.10 charges, it gradually turns ON the transistor M.sub.N20 which therefore diverts a portion of the current from the current source 120 to flow through the transistor M.sub.N20. Depending on the configuration of the current source I.sub.20 as well as a size of the transistor M.sub.N20, the gradual turning ON of the transistor M.sub.N20 can result in: a) the totality of the current sourced by the current source I.sub.20 to flow through the transistor M.sub.N20, or b) a magnitude of the current through the transistor M.sub.N20 to lower the voltage at the node N.sub.21, both of which result in a discharge of the node N.sub.21, which in combination with the charging of the node N.sub.10, can turn OFF the transistor M.sub.N21, and therefore stop flow of the pre-charge current I.sub.PC10 through the transistor M.sub.N21.
[0038] With continued reference to FIG. 3A, the pre-charge voltage at node N.sub.10 at which the flow of the pre-charge current I.sub.PC10 through the transistor M.sub.N21 stops may be adjusted to a voltage level that is near, but lower than, a steady state voltage at the node N.sub.10 during normal operation of the current mirror (M.sub.N10, M′.sub.N10, I.sub.REF). This allows the node N.sub.10 to charge up to its operating (steady state) voltage (e.g., corresponding to flow of the target output current I.sub.OUT) solely through the reference current I.sub.REF. Accordingly, the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2) reaches its normal (steady state) active state of operation through a transition phase that includes: a) a fast pre-charge phase of the node N.sub.10 via a combination of the reference current I.sub.REF and the pre-charge current I.sub.PC10 from an initial voltage (close to zero volts) to the pre-charge voltage, and b) a slow final charge phase of the node N.sub.10 via the reference current I.sub.REF from the pre-charge voltage to the steady state voltage that coincides with the flow of the (target) output current I.sub.OUT through the output leg of the current mirror. Adjustment of the pre-charge voltage may be provided via designed characteristics of the current source I.sub.20 and the transistor M.sub.N20 as later described with reference to the exemplary embodiments of FIG. 3C and FIG. 3D.
[0039] FIG. 3C shows an embodiment according to the present disclosure of a pre-charging circuit (220C) which can be used as the pre-charging circuit (220) described above with reference to FIG. 2. In particular, the pre-charging circuit (220C) represents a specific implementation of the pre-charging circuit (220A) described above with reference to FIG. 3A wherein the current source I.sub.20 is implemented via a resistor R.sub.22 in series connection with a P-type transistor switch M.sub.SP22. Accordingly, operation of the pre-charging circuit (220A) as described above with reference to FIG. 3A equally applies to the pre-charging circuit (220C) of FIG. 3C.
[0040] With continued reference to FIG. 3C, activation of the current source I.sub.20 of the pre-charging circuit (220C) may be synchronized with activation of the current mirror circuit (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2) via the control signal/Ena. When the control signal/Ena is low (i.e., current mirror activated), the transistor switch M.sub.SP22 is ON and therefore a current may flow from the supply voltage V.sub.DD through the transistor switch M.sub.SP22 and resistor R.sub.22. Accordingly, during the fast pre-charge phase of the node N.sub.10, such current from the current source I.sub.20 first charges the node N.sub.21 to turn ON the transistor M.sub.N21. As the transistor M.sub.N20 gradually turns ON (conducts current), more current flows through the transistor M.sub.N20 causing the node N.sub.21 to gradually discharge down to a voltage level where the gate-to-source voltage of the transistor M.sub.N21 causes the transistor to turn OFF thereby stopping the flow of the pre-charge current I.sub.PC10 through the node N.sub.10. In other words, the voltage at the node N.sub.21 decreases due to the increased voltage drop across the resistor R.sub.22 as the current through the transistor M.sub.N20 increases. As described above with reference to, for example, FIG. 3A, the turning OFF of the transistor M.sub.N21 coincides with the node N.sub.10 being pre-charged to the pre-charge voltage level, also referred herein as the cutoff voltage.
[0041] According to an embodiment of the present disclosure, adjusting of the pre-charge voltage for the configuration shown in FIG. 3C may be provided via a size of the resistor R.sub.22 that determines a relationship between a current that flows through the transistor switch M.sub.SP22 and a voltage at the node N.sub.21, and a size of the transistor M.sub.N20 that determines a current through the transistor M.sub.N20 as a function of the voltage at the node N.sub.10. Accordingly, for a given target pre-charge voltage (i.e., node N.sub.10) that determines a gate voltage to the transistor M.sub.N20, the size of the transistor M.sub.N20 is such as to draw a current through the resistor R.sub.22 that causes the node N.sub.21 to discharge to a level for which the gate-to-source voltage (i.e., difference in voltages at nodes N.sub.21 and N.sub.10) is such as to turn OFF the transistor M.sub.N21.
[0042] With continued reference to FIG. 3C, it would be clear to a person skilled in the art that (in the active state/mode of operation) once the transistor M.sub.N21 is turned OFF, a residual current still flows through the transistor M.sub.N20. According to an exemplary embodiment of the present disclosure, the size of the resistor R.sub.22 may be further based on a maximum allowable (residual) current through the resistor R.sub.22 during the active state. As the size (i.e., resistance) of the resistor R.sub.22 determines the voltage at the node N.sub.21, for a given current flow through the transistor M.sub.N20, a larger size of such resistor can provide a same voltage for a smaller current. Furthermore, and as described above with reference to FIG. 3A and FIG. 3B, presence of the optional charging element (340) in the configuration shown in FIG. 3C may not be necessary.
[0043] FIG. 3D shows an embodiment according to the present disclosure of a pre-charging circuit (220D) which can be used as the pre-charging circuit (220) described above with reference to FIG. 2. In particular, the pre-charging circuit (220D) represents a specific implementation of the pre-charging circuit (220A) described above with reference to FIG. 3A wherein the current source 120 is implemented via a P-type current mirror leg (e.g. M.sub.P22) that mirrors a current (e.g., I′.sub.REF of FIG. 1D) that is used to generate the reference current I.sub.REF of the current mirror (e.g. M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2). Operation of the pre-charging circuit (220A) as described above with reference to FIG. 3A equally applies to the pre-charging circuit (220D) of FIG. 3D.
[0044] With continued reference to FIG. 3D, and further reference to FIG. 1D, a P-type transistor M.sub.P22 with a gate coupled to the node P.sub.10 (of FIG. 1D) is used to provide a current leg that mirrors the current I′.sub.REF of FIG. 1D. In other words, the current source I.sub.20 of FIG. 3D is generated via a current mirror (M.sub.P22, M′.sub.P10, I′.sub.REF) in a same way as the reference current I.sub.REF is generated via the current mirror (M.sub.P10, M′.sub.P10, I′.sub.REF) described above with reference to FIG. 1D. Accordingly, activation and deactivation of the current source 120 of FIG. 3D is enslaved to the activation and deactivation of the current mirror (M.sub.P10, M′.sub.P10, I′.sub.REF) (e.g., via the control signal Ena of FIG. 1D, Ena being the complement of/Ena of FIG. 2).
[0045] With further reference to FIG. 3D, when the control signal Ena is high (i.e., and/Ena is low, current mirror activated), the transistor M.sub.P22 is ON and therefore a (constant) current flows from the supply voltage V.sub.DD through the transistor M.sub.P22 to charge the charging element (340). Accordingly, during the fast pre-charge phase of the node N.sub.10, such current from the current source I.sub.20 (i.e., transistor M.sub.P22) first charges the node N.sub.21 to turn ON the transistor M.sub.N21. As the pre-charge current I.sub.PC10 charges the node N.sub.10, the transistor M.sub.N20 gradually turns ON (conducts current) and current flows through the transistor M.sub.N20. By selecting a size of the transistor M.sub.N20 such as to fully drain all of the current sourced by the transistor M.sub.P22 when the voltage at node N.sub.10 reaches the pre-charge voltage, once the pre-charge voltage is reached, no current will be available to drive the transistor M.sub.N21 and therefore the transistor M.sub.N21 immediately turns OFF (e.g., irrespective of the gate-to-source voltage) thereby stopping the flow of the pre-charge current I.sub.PC10 through the node N.sub.10.
[0046] A person skilled in the art will appreciate advantages provided by the configuration shown in FIG. 3D wherein ratios of sizes of transistors only is used to provide operation of the pre-charging circuit (220D) based on currents that accordingly track over process and temperature variations. In turn this eliminates/reduces variation in the pre-charge voltage that (effectively) causes the pre-charge current I.sub.PC10 to stop, thereby providing a more stable and consistent operation of the pre-charging circuit. Furthermore, it allows to target a pre-charge voltage that is closer to the steady state voltage without concerns of overshooting (to a level that is above the steady state voltage). Furthermore, by ratiometrically relating the various currents in play, a target cutoff for sourcing of the pre-charge current I.sub.PC10 to the node N.sub.10 may be made with respect to a magnitude of the output current I.sub.OUT of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2).
[0047] FIG. 3E shows an embodiment according to the present disclosure of a pre-charging circuit (220E) which can be used as the pre-charging circuit (220) described above with reference to FIG. 2. In particular, the pre-charging circuit (220E) represents any of the specific implementations described above with reference to FIGS. 3A-3D with an added switching arrangement (e.g., M.sub.N27) that can be used to further activate and deactivate operation of the pre-charging circuit. In particular, a (N-type) transistor switch M.sub.N27 coupled to the node N.sub.21 may be used short the node N.sub.21 during the inactive state (e.g., Ena is high) of the pre-charging circuit (220E).
[0048] FIG. 4 shows an embodiment according to the present disclosure of a pre-charging circuit (220F) which can be used as the pre-charging circuit (220) described above with reference to FIG. 2 for a case wherein the output leg of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2) includes the cascoded configuration (100B) described above with reference to FIG. 1B. In particular, the pre-charging circuit (220F) may be used to speed up operation of the cascoded configuration of FIG. 1B by pre-charging not only the node N.sub.10, but also nodes (e.g., N.sub.11, . . . , etc.) of gates of the cascode transistors (e.g., M.sub.N11, . . . , etc.) of the output leg (e.g., 110 of FIG. 1B). Pre-charging of the nodes (e.g., N.sub.11, . . . , etc.) provided via respective pre-charge currents (e.g., I.sub.PC11, . . . , etc.) generated via respective source follower circuits (e.g., M.sub.N22 and R.sub.22 for node N.sub.11) as shown in FIG. 4.
[0049] With continued reference to FIG. 4, during the inactive state of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2 with/Ena at a high level), no current flows through the current source I.sub.20 and therefore the nodes (N.sub.21, N.sub.22, . . . , etc.) shown in FIG. 3A are at about zero volts. On the other hand, during the active state of the current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2 with/Ena at a high level), a current flows through the current source I.sub.20 which initially charges node N.sub.21 through the diode-connected (N-type) transistor M.sub.N45, and therefore charges the node N.sub.22 (e.g., one forward diode voltage drop above node N.sub.21). In turn, charging of the nodes N.sub.21 and N.sub.22 cause the transistors M.sub.N21 and M.sub.N22 to turn ON and therefore to source pre-charge currents I.sub.PC10 and I.sub.PC11 to respective nodes N.sub.10 and N.sub.11 (it is noted that nodes N.sub.10 and N.sub.11 can be considered as common nodes to the input and output legs of the current mirror shown in FIG. 1B). Similar to the description above with reference to FIG. 2, pre-charging of the nodes N.sub.10 and N.sub.11, continues until the cutoff voltage (i.e., pre-charge voltage) is sensed at the gate of the transistor M.sub.N20 via node N.sub.10. Once the cutoff voltage is reached, the transistors M.sub.N21 and M.sub.N22 to turn OFF and therefore sourcing of pre-charge currents I.sub.PC10 and I.sub.Pcii to respective nodes N.sub.10 and N.sub.11 stop. A person skilled in the art would clearly understand that principle of operation of the pre-charge circuit (220F) may be readily understood by the above detailed description of FIG. 2 and FIGS. 3A-3F.
[0050] FIG. 5 shows a block diagram of a pre-charging circuit (220) according to an embodiment of the present disclosure used to speed up operation of an N-type current mirror (M.sub.N10, M′.sub.N10, I.sub.REF) while controlling a timing of a pre-charge current (e.g., I.sub.PC10) burst. A person skilled in the art would recognize that the configuration shown in FIG. 5 is similar to one described above with reference to FIG. 2 with added (series-connected) resistor R.sub.45 and optional (shunted) capacitor C.sub.45 that in combination may be used to control timing of a burst of the pre-charge current I.sub.PC10 provided to the node N.sub.10.
[0051] With continued reference to FIG. 5, the resistor R.sub.45 can be used to limit/control any overshoot of a voltage at the node N.sub.10 when the pre-charge circuit (220) is (initially) activated by controlling the rate of the pre-charge current (e.g., initial burst of the current I.sub.PC10), with smaller values of R.sub.45 yielding in a higher/faster rate. In other words, R.sub.45 may be used to dynamically control the onset of the pre-charge current I.sub.PC10. According to an embodiment of the present disclosure, the resistor R.sub.45 may be used to control timing of the pre-charge burst (e.g., pre-charge rate) of the current I.sub.PC10 to the node N.sub.10, while the ratio of the transistors of the pre-charge circuit (e.g., M.sub.N20, M.sub.N21 as described above) may be used to determine the (cutoff) voltage level at the node N.sub.10 up to which the pre-charge burst continues. It should be noted that even in presence of an initial overshoot at the node N.sub.10 that may be caused by the onset of the pre-charge current I.sub.PC10, the final voltage value at the node N.sub.10 (i.e., steady state voltage) is determined by charging of the node N.sub.10 solely/exclusively/only by the current I.sub.REF (and not the pre-charge current I.sub.PC10). In some embodiments the optional shunting capacitor C.sub.45 may be used to provide added (voltage) stability during operation of the pre-charge circuit (220).
[0052] FIG. 6 is a process chart (600) showing various steps of a method according to the present disclosure for reducing a transition phase between an inactive state and an active state of a current mirror. As shown in FIG. 6 such steps comprise: sensing, via a first transistor, a voltage at a common node to an input leg and an output leg of the current mirror, per step (610); based on the sensing, controlling a second transistor to source a pre-charge current to the common node, per step (620); based on the controlling, speeding up charging of the common node up to a cutoff voltage that is near and below a steady state voltage at the common node, per step (630); and charging the common node to the steady state voltage via a current through the input leg of the current mirror, thereby causing onset of a target current through the output leg for operation of the current mirror according to the active state, per step (640).
[0053] It should be noted that while the above description is mainly provided with respect to pre-charging of an exemplary N-type current mirror (e.g., M.sub.N10, M′.sub.N10, I.sub.REF of FIG. 2 and FIG. 5), teachings according to the present disclosure may equally apply to a P-type current mirror provided minor circuit modifications that are well within the ability of a person skilled in the art.
[0054] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
[0055] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.
[0056] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
[0057] Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
[0058] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.
[0059] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.
[0060] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
