ANALOG-TO-DIGITAL CONVERTER, LOW-DROPOUT REGULATOR AND COMPARISON CONTROL CIRCUIT THEREOF

Abstract

A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

Claims

1. A comparison control circuit, comprising: a comparator, having a first input terminal, a second input terminal and a first output terminal, the comparator receives a first input signal at the first input terminal and receives a second input signal at the second input terminal, the comparator is configured to compare the first input signal and the second input signal and to output a comparison signal at the first output terminal, wherein the comparison signal is a first high voltage potential or a first low voltage potential; a Schmitt trigger, having a third input terminal and a second output terminal, the Schmitt trigger is configured to output a trigger signal at the second output terminal according to the comparison signal received at the third input terminal and a voltage potential range, wherein the trigger signal is a second high voltage potential or a second low voltage potential, and the voltage potential range is in a range from the first low voltage potential to the first high voltage potential; a capacitor set, configured to adjust the second input signal when being controlled; and a logic circuit, configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

2. The comparison control circuit according to claim 1, wherein the comparator is a comparator with single-ended input.

3. The comparison control circuit according to claim 1, wherein the first high voltage potential is 1 volt (V), and the first low voltage is 0 volt (V).

4. The comparison control circuit according to claim 1, wherein the second high voltage potential is 1 volt (V), and the second low voltage is 0 volt (V).

5. The comparison control circuit according to claim 1, wherein the capacitor set comprises a plurality of capacitors from C.sub.1 to C.sub.N, and wherein each of the plurality of capacitors has a first terminal and a second terminal.

6. The comparison control circuit according to claim 5, wherein the first terminal of each of the plurality of capacitors is electrically connected to the second input terminal, and the second terminal of each of the plurality of capacitors is electrically connected to a reference voltage source or a ground selectively when being controlled.

7. An analog low-dropout regulator, comprising: an error amplifier, having a positive input terminal, a negative input terminal and a third output terminal, the error amplifier is configured to output a control voltage at the third output terminal according to a feedback voltage received at the positive input terminal and a stable reference voltage potential received at the negative input terminal; a pass transistor, having a gate terminal, a drain terminal and a source terminal, the pass transistor is configured to output an output voltage at the drain terminal according to the control voltage received at the gate terminal; a voltage divider circuit, configured to divide the output voltage and the feedback voltage, such that a value of the feedback voltage is the same as the stable reference voltage potential, thereby a value of the output voltage is the same as the stable reference voltage potential; and a comparison control circuit, comprising: a comparator, having a first input terminal, a second input terminal and a first output terminal, the comparator receives a first input signal at the first input terminal and receives a second input signal at the second input terminal, the comparator is configured to compare the first input signal and the second input signal and to output a comparison signal at the first output terminal, wherein the comparison signal is a first high voltage potential or a first low voltage potential; a Schmitt trigger, having a third input terminal and a second output terminal, the Schmitt trigger is configured to output a trigger signal at the second output terminal according to the comparison signal received at the third input terminal and a voltage potential range, wherein the trigger signal is a second high voltage potential or a second low voltage potential, and the voltage potential range is in a range from the first low voltage potential to the first high voltage potential; a capacitor set, configured to adjust the second input signal when being controlled; and a logic circuit, configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal; wherein the second input terminal is electrically connected to the drain terminal.

8. The analog low-dropout regulator according to claim 7, wherein the voltage divider circuit comprises a first voltage dividing resistor and a second voltage dividing resistor, and wherein a resistance of the first voltage dividing resistor is much smaller than a resistance of the second voltage dividing resistor.

9. The analog low-dropout regulator according to claim 7, wherein the comparator is a comparator with single-ended input.

10. The analog low-dropout regulator according to claim 7, wherein the first high voltage potential is 1 volt (V), and the first low voltage is 0 volt (V).

11. The analog low-dropout regulator according to claim 7, wherein the second high voltage potential is 1 volt (V), and the second low voltage is 0 volt (V).

12. The analog low-dropout regulator according to claim 7, wherein the capacitor set comprises a plurality of capacitors from C.sub.1 to C.sub.N, and wherein each of the plurality of capacitors has a first terminal and a second terminal.

13. The analog low-dropout regulator according to claim 12, wherein the first terminal of each of the plurality of capacitors is electrically connected to the second input terminal, and the second terminal of each of the plurality of capacitors is electrically connected to a reference voltage source or a ground selectively when being controlled.

14. An analog-to-digital converter, comprising: a comparator, having a first input terminal, a second input terminal and a first output terminal, the comparator is configured to compare the first input terminal and the second input terminal and to output a comparison signal at the first output terminal, wherein the comparison signal is a first high voltage potential or a first low voltage potential; a Schmitt trigger, having a third input terminal and a second output terminal, the Schmitt trigger is configured to output a trigger signal at the second output terminal according to the third input terminal and a voltage potential range, wherein the trigger signal is a second high voltage potential or a second low voltage potential, and the voltage potential range is in a range from the first low voltage potential to the first high voltage potential; a capacitor set, comprising a plurality of switched capacitor groups, each of the plurality of switched capacitor groups comprises a capacitor and a switch in series, the plurality of switched capacitor groups are connected in parallel with each other, when the switches are controlled, the switches electrically connect the capacitors to a reference voltage source or a ground selectively, a parallel point of the capacitors is electrically connected to the second input terminal; and a logic circuit, configured to control the switches of the capacitor set according to the trigger signal.

15. The analog-to-digital converter according to claim 14, wherein a capacitance of capacitor C.sub.i is twice a capacitance of capacitor C.sub.i+1, a capacitance of capacitor C.sub.N−1 is equal to a capacitance of capacitor C.sub.N, and wherein i=1˜N−2.

16. The analog-to-digital converter according to claim 14, wherein the capacitor set is a capacitive digital-to-analog converter.

17. The analog-to-digital converter according to claim 14, wherein the logic circuit is a successive approximation register (SAR).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The disclosure will become more fully understood from the detailed description given herein below for illustration only, and thus not limitative of the disclosure, wherein:

[0018] FIG. 1 illustrates a functional block diagram of a comparison control circuit according to an embodiment of the present application;

[0019] FIG. 2A illustrates a waveform diagram of the voltage of an external input signal received by a comparator of the comparison control circuit according to an embodiment of the present application;

[0020] FIG. 2B illustrates a waveform diagram of the voltage of a clock of the comparator of the comparison control circuit according to an embodiment of the present application;

[0021] FIG. 2C illustrates a waveform diagram of the voltage of a comparison signal output by the comparator of the comparison control circuit according to an embodiment of the present application;

[0022] FIG. 3 illustrates a schematic circuit diagram of an analog-to-digital converter according to an embodiment of the present application;

[0023] FIG. 4 illustrates a flow diagram of the operation of the analog-to-digital converter according to an embodiment of the present application;

[0024] FIG. 5 illustrates a schematic circuit diagram of an analog low-dropout regulator according to an embodiment of the present application; and

[0025] FIG. 6 illustrates a flow diagram of the operation of the analog low-dropout regulator according to an embodiment of the present application.

DETAILED DESCRIPTION

[0026] Some embodiments of the present application are illustrated in the drawings. For the sake of clear illustration, many practical details will be illustrated together in the following description, but this is not to limit the scope of claims of the present application.

[0027] Please refer to FIG. 1. FIG. 1 illustrates a functional block diagram of a comparison control circuit 100 according to an embodiment of the present application. The comparison control circuit 100 includes a comparator 110, a Schmitt trigger 120, a logic circuit 130 and a capacitor set 140. The comparator 110 has a first input terminal 111, a second input terminal 112 and a first output terminal 113. The Schmitt trigger 120 has a third input terminal 121 and a second output terminal 122. As shown in FIG. 1, the third input terminal 121 of the Schmitt trigger 120 is electrically connected to the first output terminal 113 of the comparator 110, the logic circuit 130 is electrically connected to the second output terminal 122 of the Schmitt trigger 120, and the capacitor set 140 is electrically connected to the second input terminal 112 and the logic circuit 130.

[0028] In some embodiments, the comparator 110 is a comparator with single-ended input, wherein the comparator 110 receives a first input signal V.sub.in1 at the first input terminal 111 and receives a second input signal V.sub.in2 at the second input terminal 112. The comparator 110 is configured to compare the first input signal V.sub.in1 and the second input signal V.sub.in2 and to output a comparison signal at the first output terminal 113, wherein the comparison signal is a first high voltage potential or a first low voltage potential. Please refer to FIG. 2A, FIG. 2B and FIG. 2C. FIG. 2A illustrates a waveform diagram of the voltage of an external input signal received by the comparator 110 of the comparison control circuit 100 according to an embodiment of the present application. FIG. 2B illustrates a waveform diagram of the voltage of a clock of the comparator 110 of the comparison control circuit 100 according to an embodiment of the present application, wherein the clock of the comparator 110 is configured to trigger the comparator 110 to output the comparison signal. FIG. 2C illustrates a waveform diagram of the voltage of the comparison signal output by the comparator 110 of the comparison control circuit 100 according to an embodiment of the present application, wherein a waveform in a solid line represents the waveform of the comparison signal, and a waveform in a three-dotted chain line represents the waveform led by noise. In the waveform diagrams of the FIG. 2A, FIG. 2B and FIG. 2C, the horizontal axis represents time in nanoseconds (ns). The vertical axis represents the magnitude of voltage, and the unit is volts (V). In this embodiment, the first high voltage potential is 1 volt, and the first low voltage potential is 0 volt. The first input signal V.sub.in1 is the external input signal, and the second input signal V.sub.in2 is a comparison voltage potential V.sub.com, wherein the value of the comparison voltage potential V.sub.com is 0.5 volts. When the value of the first input signal V.sub.in1 (as illustrated in a dotted line L1 shown in FIG. 2A) received at the first input terminal 111 of the comparator 110 is greater than or equal to the second input signal V.sub.in2, the clock of the comparator 110 will trigger the comparator 110 at the falling edge (as illustrated in a dotted line L1 shown in FIG. 2B), such that the comparator 110 outputs the first high voltage potential (as illustrated in a box R1 formed by a single-dotted chain shown in FIG. 2C) at the first output terminal 113. When the value of the first input signal V.sub.in1 (as illustrated in a dotted line L2 shown in FIG. 2A) received at the first input terminal 11I of the comparator 110 is less than the second input signal V.sub.in2, the clock of the comparator 110 will trigger the comparator 110 at the rising edge (as illustrated in a dotted line L2 shown in FIG. 2B), such that the comparator 110 outputs the first low voltage potential (as illustrated in a box R2 formed by a single-dotted chain shown in FIG. 2C) at the first output terminal 113.

[0029] The Schmitt trigger 120 is configured to output a trigger signal at the second output terminal 122 according to the comparison signal received at the third input terminal 121 and a voltage potential range, wherein the trigger signal is a second high voltage potential or a second low voltage potential. In some embodiments, the user can define the voltage potential range of the Schmitt trigger 120. In this embodiment, the voltage potential range of the Schmitt trigger 120 is in a range from the first low voltage potential to the first high voltage potential. When the value of the comparison signal received by the Schmitt trigger 120 is greater than or equal to the upper limit of the voltage potential range, the Schmitt trigger 120 outputs the second high voltage potential at the second output terminal 122. When the value of the comparison signal received by the Schmitt trigger 120 is within the voltage potential range (i.e., the value of the comparison signal is greater than or equal to the lower limit of the voltage potential range, and the value of the comparison signal is less than the upper limit of the voltage potential range), the Schmitt trigger 120 does not perform any action. When the value of the comparison signal received by the Schmitt trigger 120 is less than the lower limit of the voltage potential range, the Schmitt trigger 120 outputs the second low voltage potential at the second output terminal 122. In some embodiments, the second high voltage potential is 1 volt, and the second low voltage potential is 0 volt. Since the Schmitt trigger 120 has better noise immunity to analog signals, the noise generated by the power source or the noise of the comparison signal output by the comparator 110 can be effective against by disposing the Schmitt trigger 120 in the comparison control circuit 100, thereby avoiding problems during the operating process of the comparison control circuit 100.

[0030] The capacitor set 140 is configured to adjust the second input signal V.sub.in2 when being controlled by the logic circuit 130. In some embodiments, the capacitor set 140 includes N capacitors C.sub.1-C.sub.N and N switches S.sub.1-S.sub.N, wherein each of the capacitors C.sub.1-C.sub.N has a first terminal and a second terminal. The first terminal of each of the capacitors C.sub.1-C.sub.N is electrically connected to the second input terminal 112 of the comparator 110. The second terminal of each of the capacitors C.sub.1-C.sub.N can be selectively electrically connected to a reference voltage source V.sub.ref or ground through the corresponding switch when being controlled. When a second terminal of a capacitor is electrically connected to the reference voltage source V.sub.ref, the capacitor will be charged. When a second terminal of a capacitor is electrically connected to the ground, the capacitor will be discharged.

[0031] The logic circuit 130 is configured to control the capacitor set 140 according to the trigger signal to correspondingly adjust the comparison voltage potential V.sub.com. In other words, the logic circuit 130 will control the corresponding switch(es) in the capacitor set 140 according to the value of the trigger signal. Then, the corresponding capacitor(s) will be electrically connected to the reference voltage source V.sub.ref or ground for charging or discharging. Finally, the capacitor set 140 will calculate an adjusted comparison voltage potential according to the capacitance of each capacitor and output the adjusted comparison voltage potential to the second input terminal 112 of the comparator 110.

[0032] In some embodiments, the structure of the comparison control circuit 100 can be applied in an analog-to-digital converter 200. Please refer to FIG. 3. FIG. 3 illustrates a schematic circuit diagram of the analog-to-digital converter 200 according to an embodiment of the present application. The analog-to-digital converter 200 includes a comparator 210, a Schmitt trigger 220, a logic circuit 230 and a capacitor set 240. As shown in FIG. 3, a third input terminal 221 of the Schmitt trigger 220 is electrically connected to a first output terminal 213 of the comparator 210, the logic circuit 230 is electrically connected to a second output terminal 222 of the Schmitt trigger 220, and the capacitor set 240 is electrically connected to a second input terminal 212 of the comparator 210 and the logic circuit 230. In this embodiment, the signal received at the first input terminal 211 of the comparator 210 is an analog input signal V.sub.ain, the signal received at the second input terminal 212 of the comparator 210 is a comparison voltage potential V.sub.com, and the signal received at the third input terminal 221 of the Schmitt trigger 220 is a comparison signal.

[0033] The analog-to-digital converter 200 is configured to convert the analog input signal V.sub.ain into a digital output signal with N bits. In some embodiments, the analog-to-digital converter 200 starts the conversion from the most significant bit (MSB) of the digital output signal and sequentially converts the remaining bits until the least significant bit (LSB) is converted, which complete a complete analog-to-digital conversion. In some embodiments, the analog-to-digital converter 200 outputs a digital output signal V.sub.dout through the logic circuit 230, wherein the logic circuit 230 is a successive approximation register (SAR).

[0034] The capacitor set 240 of the analog-to-digital converter 200 includes a plurality of switched capacitor groups. Each of the switched capacitor groups includes a capacitor and a switch in series, and each of the switched capacitor groups is in parallel with each other, wherein a parallel point of each switched capacitor group is electrically connected to the second input terminal 212 of the comparator 210. Each switch of the capacitor set 240 is electrically connected to a reference voltage source V.sub.ref or ground selectively when being controlled, wherein the reference voltage source V.sub.ref is a fixed voltage value. In some embodiments, the capacitance of the capacitor C.sub.i is twice the capacitance of the capacitor C.sub.i+1, and the capacitance of the capacitor C.sub.N−1 is equal to the capacitance of the capacitor C.sub.N, wherein i=1˜N−2. In some embodiments, the capacitor set 240 is a capacitive digital-to-analog converter, wherein the capacitive digital-to-analog converter converts a digital signal into an analog signal by using capacitors to store charges. For example, in this embodiment, the capacitor set 240 includes four capacitors C.sub.1-C.sub.4 and four switches S1-S4. If a digital signal received by the capacitor set 240 is (1100), the capacitors C.sub.1 and C.sub.2 are electrically connected to the reference voltage source V.sub.ref, and the capacitors C.sub.1 and C.sub.2 are electrically connected to the ground. It is assumed that the value of the reference voltage source V.sub.ref is 1 volt and the capacitance of the capacitor C.sub.4 is C. Since the total capacitance of the capacitors in parallel is equal to the sum of the capacitance of the capacitors, and the impedance of a capacitor is inversely proportional to its capacitance, the comparison voltage potential V.sub.com output by the capacitor set 240 to the comparator 210 is 0.75 volts. The formula is as follows:

[00001]$V_{\mathrm{com}}=\frac{4C+2C}{4C+2C+C+C}\times V_{\mathrm{ref}}=\frac{3}{4}{V}_{\mathrm{ref}}$

[0035] Please refer to FIG. 4. FIG. 4 illustrates a flow diagram of the operation of the analog-to-digital converter 200 according to an embodiment of the present application. As shown in FIG. 4, when the analog input signal V.sub.ain is input to the analog-to-digital converter 200, the analog-to-digital converter 200 samples (Sample-and-Hold, S&H) the analog input signal V.sub.ain, and inputs the analog input signal V.sub.ain to comparator 210. The purpose of sampling is to make the analog-to-digital converter 200 to maintain the consistency of the analog input signal V.sub.ain during the operating process, so as to avoid errors in the digital output signal V.sub.dout. In step S20, the comparator 210 compares the analog input signal V.sub.ain of the first input terminal 211 and the comparison voltage potential V.sub.com of the second input terminal 212 and outputs, at the first output terminal 213, a comparison signal to the Schmitt trigger 220 of the analog-to-digital converter 200. In step S30, the Schmitt trigger 220 outputs, at the second output terminal 222, a trigger signal to the logic circuit 230 of the analog-to-digital converter 200 according to the comparison signal and a voltage potential range.

[0036] In step S40, the logic circuit 230 stores the trigger signal in order as the corresponding bits in the analog input signal V.sub.ain (from the most significant bit to the least significant bit). Then, the logic circuit 230 control the corresponding switch in the capacitor set 240 of the analog-to-digital converter 200 according to the trigger signal, such that the corresponding capacitor is electrically connected to the reference voltage source V.sub.ref or ground. For example, if the current conversion sequence is the second bit, it represents that the logic circuit 230 will store the trigger signal as the second valid bit of the analog input signal V.sub.ain. If the value of the trigger signal is 1, the logic circuit 230 will control the switch S.sub.2 of the capacitor set 240, such that the capacitor C.sub.2 of the capacitor set 240 is electrically connected to the reference voltage source V.sub.ref for charging.

[0037] In step S50, the capacitor set 240 calculates an adjusted comparison voltage potential V.sub.com according to the capacitance of each capacitor and outputs the adjusted comparison voltage potential V.sub.com to the comparator 210. In step S60, the analog-to-digital converter 200 repeats steps S20-S50 to perform the next round of bit conversion until all the bits in the analog input signal V.sub.ain are converted, then proceeds to step S70. Since the magnitude of capacitance of each capacitor in the capacitor set 240 is different, the value of the comparison voltage potential V.sub.com output by the capacitor set 240 in each round of bit conversion is also different. With the proceeding of each round of bit conversion, the value of the comparison voltage potential V.sub.com received by the comparator 210 will gradually approach the value of the analog input signal V.sub.ain. When the value of the comparison voltage potential V.sub.com received by the comparator 210 is equal to the value of the analog input signal V.sub.ain, it represents that the analog-to-digital converter 200 has completely converted the analog input signal V.sub.ain into all bits of the digital output signal V.sub.dout. Therefore, in step S70, the analog-to-digital converter 200 will output a digital output signal V.sub.dout through the logic circuit 230 and end the analog-to-digital conversion this time.

[0038] In another embodiment, the comparison control circuit 100 can also be applied in an analog low-dropout regulator 300. Please refer to FIG. 5. FIG. 5 illustrates a schematic circuit diagram of the analog low-dropout regulator 300 according to an embodiment of the present application. The analog low-dropout regulator 300 includes an error amplifier 310, a pass transistor 320, a voltage divider circuit 330 and a comparison control circuit 340. The error amplifier 310 has a positive input terminal 312, a negative input terminal 311 and a third output terminal 313. The pass transistor 320 has a gate terminal 321, a drain terminal 322 and a source terminal. The comparison control circuit 340 includes a comparator 341, a Schmitt trigger 342, a logic circuit 343 and a capacitor set 344. As shown in FIG. 5, the gate terminal 321 of the pass transistor 320 is electrically connected to the third output terminal 313 of the error amplifier 310, the voltage divider circuit 330 is electrically connected to the drain terminal 322 of the pass transistor 320 and the positive input terminal 312 of the error amplifier 310, and a second input terminal 341b of the comparator 341 is electrically connected to the drain terminal 322 of the pass transistor 320. In this embodiment, the signal received at a first input terminal 341a of the comparator 341 is the comparison voltage potential V.sub.com, and the signal received at the second input terminal 341b of the comparator 341 is an output voltage V.sub.out.

[0039] The error amplifier 310 is configured to output a control voltage at the third output terminal 313 according to a feedback voltage V.sub.fb received at the positive input terminal 312 and a stable reference voltage potential V.sub.sref received at the negative input terminal 311, wherein the control voltage is configured to control the voltage of the gate terminal 321 of the pass transistor 320. When the feedback voltage V.sub.fb is greater than the stable reference voltage potential V.sub.sref, the error amplifier 310 will adjust the voltage of the gate terminal 321 of the pass transistor 320, so that the value of a current flowing through the pass transistor 320 decreases to reduce the output voltage V.sub.out. When the feedback voltage Vie is less than the stable reference voltage potential V.sub.sref, the error amplifier 310 will adjust the voltage of the gate terminal 321 of the pass transistor 320, so that the value of the current increases to increase the output voltage V.sub.out.

[0040] The pass transistor 320 is configured to output the output voltage V.sub.out at the drain terminal 322 according to the control voltage received at the gate terminal 321. In some embodiments, the pass transistor 320 receives an input voltage V.sub.in at the source terminal 323. When the gate terminal 321 of the pass transistor 320 receives the control voltage from the error amplifier 310, the pass transistor 320 outputs the output voltage V.sub.out at the drain terminal 322, wherein the value of the input voltage V.sub.in is greater than the value of the output voltage V.sub.out. In some embodiments, the pass transistor 320 is a PMOS (p-channel metal oxide semiconductor).

[0041] The voltage divider circuit 330 is configured to divide the output voltage V.sub.out and the feedback voltage V.sub.fb, such that the value of the feedback voltage V.sub.fb is the same as the value of the stable reference voltage potential V.sub.sref, further such that the value of the output voltage V.sub.out is the same as the value of the stable reference voltage potential V.sub.sref, wherein the stable reference voltage potential V.sub.sref is a fixed voltage not affected by temperature or signal noise. In some embodiments, the voltage divider circuit 330 includes a first voltage dividing resistor R.sub.fb1 and a second voltage dividing resistor R.sub.fb2, wherein the resistance of the first voltage dividing resistor R.sub.fb1 is much smaller than the resistance of the second voltage dividing resistor R.sub.fb2. It is assumed that the error amplifier 310 is an ideal amplifier, the value of the output voltage V.sub.out is the same as the value of the stable reference voltage potential V.sub.sref can be calculated, and the formula is as follows:

[00002]$V_{\mathrm{out}}=I\times \left(R_{\mathrm{fb}1}+R_{\mathrm{fb}2}\right)=V_{\mathrm{fb}}\times \left(1+\frac{R_{\mathrm{fb}1}}{R_{\mathrm{fb}2}}\right)=V_{\mathrm{sref}},\mathrm{wherein}$$I=\frac{V_{\mathrm{fb}}}{R_{\mathrm{fb}2}},V_{\mathrm{fb}}=V_{\mathrm{sref}},R_{\mathrm{fb}1}\ll R_{\mathrm{fb}2}$

[0042] In some embodiments, the comparison control circuit 340 is configured to stabilize the output voltage V.sub.out. When the pass transistor 320 outputs an output voltage V.sub.out at the drain terminal 322, the output voltage V.sub.out becomes more stable by being adjusted through the comparison control circuit 340. In some embodiments, the output voltage V.sub.out is input to the comparison control circuit 340 through the second input terminal 341b of the comparator 341, and the output voltage V.sub.out is compared with comparison voltage potential V.sub.com received at the first input terminal 341a of the comparator 341. When the value of the output voltage V.sub.out is greater than the comparison voltage potential V.sub.com, the comparison control circuit 340 control the capacitor set 344 through the logic circuit 343 to reduce the value of the output voltage V.sub.out to the comparison voltage potential V.sub.com. When the value of the output voltage V.sub.out is less than the comparison voltage potential V.sub.com, the comparison control circuit 340 control the capacitor set 344 through the logic circuit 343 to increase the value of the output voltage V.sub.out to the comparison voltage potential V.sub.com. In some embodiments, the comparison voltage potential V.sub.com received at the first input terminal 341a of the comparator 341 is equal to the stable reference voltage potential V.sub.sref.

[0043] In some embodiments, the user can define the number of capacitors in the capacitor set 344 and the capacitance of each capacitor according to the value of the output voltage V.sub.out. If the more number of capacitors in the capacitor set 344, it represents that the voltage value output by the capacitor set 344 will have more variations; and if the less number of capacitors in the capacitor set 344, it represents that the voltage value output by the capacitor set 344 will have fewer variations. If the more capacitance of a capacitor, it represents that the voltage range output by the capacitor set 344 will be larger; if the less capacitance of a capacitor, it represents that the voltage range output by the capacitor set 344 will be smaller. For example, if the value of the output voltage V.sub.out is small (e.g., the value of the output voltage V.sub.out is 1 volt), the user can set a smaller number of capacitors with smaller capacitance in the capacitor set 344 to save cost.

[0044] Please refer to FIG. 6. FIG. 6 illustrates a flow diagram of the operation of the analog low-dropout regulator 300 according to an embodiment of the present application. As shown in FIG. 6, in step S80, the analog low-dropout regulator 300 inputs an input voltage V.sub.in to the source terminal 323 of the pass transistor 320. In step S90, the analog low-dropout regulator 300 respectively inputs a stable reference voltage potential V.sub.sref and a feedback voltage V.sub.fb to the negative input terminal 311 and the positive input terminal 312. At this time, the error amplifier 310 outputs a control voltage to the gate terminal 321 of the pass transistor 320 according to the stable reference voltage potential V.sub.sref and the feedback voltage V.sub.fb. In step S100, the gate terminal 321 of the pass transistor 320 receives the control voltage, such that the pass transistor 320 enters a conductive state and outputs an output voltage V.sub.out at the drain terminal 322. At this time, if the value of the output voltage V.sub.out is not equal to the stable reference voltage potential V.sub.sref, the analog low-dropout regulator 300 adjusts the output voltage V.sub.out through the voltage divider circuit 330 and the error amplifier 310, such that the value of the output voltage V.sub.out is equal to the stable reference voltage potential V.sub.sref.

[0045] In step S110, when the value of the output voltage V.sub.out is equal to the stable reference voltage potential V.sub.sref, the comparator 341 of the comparison control circuit 340 receives the output voltage V.sub.out through the second input terminal 341b and outputs, according to the output voltage V.sub.out and the comparison voltage potential V.sub.com received at the first input terminal 341a, a comparison signal at the first output terminal 341c to the third input terminal 342a of the Schmitt trigger 340. In step S120, the Schmitt trigger 342 outputs, according to the comparison signal and a voltage potential range, a trigger signal to the logic circuit 343 of the comparison control circuit 340 at the second output terminal 342b. In step S130, the logic circuit 343 controls the corresponding switch in the capacitor set 344 of the comparison control circuit 340 according to the trigger signal, such that the corresponding capacitor in the capacitor set 344 is charged or discharged. Finally, in step S140, the capacitor set 344 calculates an adjusted output voltage V.sub.out according to the capacitance of each capacitor and outputs it.

[0046] To sum up, according to some embodiments of the comparison control circuit 100, even if the input signal or power signal in various types of circuits is mixed with noise, these circuits can immune the noise through the comparison control circuit 100, thereby avoiding operation failure or to output wrong results. For example, applying the structure of the comparison control circuit 100 in the analog-to-digital converter 200 can make the analog-to-digital converter 200 outputting a more accurate digital output signal V.sub.dout. The analog low-dropout regulator 300 can adjust the output voltage V.sub.out through the comparison control circuit 340, such that the output voltage V.sub.out becomes more stable.

[0047] Although the present application has been disclosed by the embodiments as aforementioned, it is not intended to limit the creation of the present application. Those skilled in the art may make some modifications and changes without departing from the spirit and scope of the present application, but such modifications and changes are still within the scope of the present application.