Abstract
An electronic arrangement (100) and a method of manufacturing an electronic arrangement are provided. The electronic arrangement comprises an array of electronic components (110) arranged along a first axis, A, and a carrier (120) arranged to support the array of electronic components, wherein the carrier comprises, a first metal layer (130), a second metal layer (140), and an at least partially insulating layer (150) arranged between the first and second metal layers. The electronic arrangement further comprises a partition portion (160) arranged between two adjacently arranged electronic components for partitioning the electronic arrangement, wherein the second metal layer comprises a void (180) intersected by the second axis, wherein the void has a width (190) which extends parallel to the first axis, such that, at the second axis, the second metal layer is undercut with respect to the first metal layer, in a direction parallel to the first axis.
Claims
1. An electronic arrangement, comprising an array of electronic components arranged on a layer of a layer stack and along a first axis, A, and the layer stack being formed as a carrier arranged to support the array of electronic components, wherein the carrier comprises, in a direction perpendicular to the first axis and perpendicular to the layer stack, a first metal layer and a second metal layer, wherein an at least partially insulating layer is arranged between the first and second metal layers, and at least one partition portion arranged between two adjacently arranged electronic components for partitioning the electronic arrangement along a second axis, B, of the at least one partition portion, wherein the second axis extends perpendicular to the first axis, wherein the second metal layer, at the at least one partition portion, comprises at least one void intersected by the second axis, wherein the at least one void has a width which extends parallel to the first axis, such that, at the second axis, the second metal layer is undercut with respect to the first metal layer, in a direction parallel to the first axis.
2. The electronic arrangement of claim 1, wherein the width of the at least one void is in the range of 0.7-1.1 times the distance (L) between adjacently arranged electronic components.
3. The electronic arrangement of claim 1, wherein the width of the at least one void is negatively correlated to the thickness of the at least partially insulating layer.
4. The electronic arrangement of claim 1, wherein the sum of the thickness of the at least partially insulating layer and half the width of the at least one void is 0.1-3 mm, preferably 0.5-1.2 mm, and most preferred 0.5-0.7 mm.
5. The electronic arrangement of claim 1, wherein the at least one void has a rectangular shape.
6. The electronic arrangement of claim 1, wherein the second metal layer comprises aluminum, Al.
7. The electronic arrangement of claim 1, wherein the thickness of the second metal layer is 0.1-1.6 mm, preferably 0.2-0.5 mm, and most preferred 0.24-0.36 mm.
8. The electronic arrangement of claim 1, wherein at least one of the at least partially insulating layer and the first metal layer comprises an indentation at the at least one partition portion.
9. The electronic arrangement of claim 1, wherein at least one of the electronic components comprises at least one light-emitting diode, LED.
10. An electronic board, comprising a plurality of electronic arrangements according to claim 1, wherein the electronic arrangements are arranged side-by-side in a first plane such that partition portions of adjacently arranged electronic arrangements are arranged along the second axis in the first plane for partitioning the electronic board along the second axis.
11. A method of manufacturing an electronic arrangement, comprising the steps of: forming a layer stack by arranging a first metal layer on an at least partially insulating layer, wherein the first metal layer and the at least partially insulating layer extend along a first axis, providing a second metal layer extending along the first axis and forming at least one void in the second metal layer having a width which extends parallel to the first axis, arranging a plurality of electronic components in an array on the first metal layer along the first axis, and forming at least one partition portion between two adjacently arranged electronic components for partitioning the electronic arrangement along a second axis, B, of the at least one partition portion perpendicular to the first axis by arranging the second metal layer under the at least partially insulating layer such that the at least one void is intersected by the second axis and such that, at the second axis, the second metal layer is undercut with respect to the first metal layer, in a direction parallel to the first axis.
12. The method of claim 11, wherein the at least one void has a rectangular shape.
13. The method of claim 11, wherein the second metal layer comprises aluminum, Al.
14. The method of claim 11, wherein the thickness of the second metal layer is 0.1-1.6 mm, preferably 0.2-0.5 mm, and most preferred 0.24-0.36 mm.
15. The method of claim 11, further comprising forming at least one indentation at the second axis in at least one of the at least partially insulating layer and the first metal layer at the at least one partition portion.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] This and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing embodiment(s) of the invention.
[0035] FIGS. 1a-b are schematic, cross-sectional views of a metal-core PCB (MCPCB) according to the prior art;
[0036] FIGS. 2a-b are schematic, cross-sectional views of an electronic arrangement according to an exemplifying embodiment of the present invention;
[0037] FIG. 3 is a schematic, cross-sectional view of an electronic arrangement according to an exemplifying embodiment of the present invention;
[0038] FIGS. 4a-b are schematic top and bottom views, respectively, of an electronic arrangement according to an exemplifying embodiment of the present invention;
[0039] FIGS. 5a-b are schematic top and bottom views, respectively, of an electronic board according to an exemplifying embodiment of the present invention; and
[0040] FIG. 6 is a schematic illustration of a method of manufacturing an electronic arrangement according to an exemplifying embodiment of the present invention.
DETAILED DESCRIPTION
[0041] FIG. 1a is a schematic, cross-sectional view of a metal-core PCB (MCPCB) 10 according to the prior art. The MCPCB 10 comprises a plurality of electronic components 11, which are exemplified as a first LED element 11a and a second LED element 11b. The electronic elements 11 are arranged along a horizontally extending first axis A. The MCPCB 10 further comprises a first metal layer 13 and a second metal layer 14, and a layer 15 which is arranged between the first metal layer 13 and the second metal layer 14.
[0042] The MCPCB 10 may be cut along a second axis B extending perpendicular to the first axis A. The partitioning or cutting of the MCPCB 10 is schematically indicated by the pair of scissors 20, which eventually separates the first LED element 11a and the second LED element 11b of the MCPCB 10. After cutting, the resulting right (or left) hand portion of the MCPCB 10 in FIG. 1a is schematically shown in FIG. 1b. However, the distance CD (which furthermore may be denoted as the creepage distance CD) between the first metal layer 13 and the second metal layer 14 along the layer 15 may hereby be relatively small. More specifically, this creepage distance CD between the conductive first and second metal layers 13, 14 may be in the order of the thickness of the layer 15, such as e.g. 0.1 mm. This is generally a too small creepage distance, and may lead to leakage currents between the conductive first and second metal layers 13, 14.
[0043] FIG. 2a is a schematic, cross-sectional view of an electronic arrangement 100 according to an exemplifying embodiment of the present invention. The electronic arrangement 100 comprises an array of electronic components 110 arranged along a first axis, A, which extends horizontally. The electronic components 110, which are exemplified as two electronic components 110a, 110b which are spaced apart along the first axis A, may for example comprise one or more LEDs.
[0044] The electronic arrangement 100 comprises a carrier 120 which is arranged to support the array of electronic components 110. The carrier 120 comprises, in a direction perpendicular to the first axis A, a first metal layer 130 and a second metal layer 140. The first metal layer 130 may, for example, comprise or be made of copper (Cu). The thickness of the first metal layer 130 may, for example, be 35-70 m. The second metal layer 140 may, for example, comprise or be made of aluminum (Al). The thickness of the second metal layer 140 may, for example, be 0.1-1.6 mm, such as 0.2-0.5 mm, such as 0.24-0.36 mm, or approximately 0.3 mm. The carrier 120 further comprises an at least partially insulating layer 150 which is arranged between the first metal layer 130 and the second metal layer 140. The thickness of the at least partially insulating layer 150 may, for example, be 75-150 m.
[0045] The electronic arrangement 100 further comprises at least one partition portion 160. The partition portion 160 is arranged between the two adjacently arranged electronic components 110a, 110b for partitioning (cutting) the electronic arrangement 100 along a second axis B of the at least one partition portion 160, wherein the second axis B extends perpendicular to the first axis A. The intended partitioning (cutting) along the second axis B is schematically indicated by a pair of scissors 20.
[0046] At the partition portion 160 of the electronic arrangement 100, the second metal layer 140 comprises at least one void 180 which is intersected by the second axis B. The at least one void 180 has a width 190 which extends parallel to the first axis A, such that, at the second axis B, the second metal layer 140 is undercut with respect to the first metal layer 130, in a direction parallel to the first axis A. This configuration of the electronic arrangement 100 leads to a relatively large creeping distance between the first metal layer 130 and the second metal layer 140 after cutting the electronic arrangement 100 at the partition portion 160 and along the second axis B as indicated in FIG. 2. The width 190 of the at least one void 180 may be dependent on the distance L between adjacently arranged electronic components 110a, 110b. For example, the width 190 of the at least one void 180 may be not less than L, or be in the range of 0.9-1.1 times the distance L between (two) adjacently arranged electronic components 110a, 110b on either side of the partition portion 160.
[0047] After partitioning or cutting the electronic arrangement 100 at the partition portion 160 and along the second axis B, the resulting right (or left) hand portion of FIG. 2a is schematically shown in FIG. 2b. The L-shaped distance CD (which furthermore may be denoted as the creepage distance CD) between the first metal layer 130 and the second metal layer 140 along the at least layer 15 may hereby be sufficiently large for minimizing or completely avoiding leakage currents between the conductive first metal layer 130 and the second metal layer 140. More specifically, as the second metal layer 140 is undercut with respect to the first metal layer 130, in a direction parallel to the first axis A and at the second axis B, the L-shaped creepage distance CD between the conductive first and second metal layers 130, 140 may be in the order of the sum of the thickness of the at least partially insulating layer 150 and half the width of the at least one void 180. In combination herewith, the width of the at least one void 180 may be dependent on the thickness of the at least partially insulating layer 150. For example, in case the at least partially insulating layer 150 is relatively thin, the width of the one or more voids 180 may be relatively large. Hence, as a consequence, the second metal layer 140 may be undercut to a relatively large degree with respect to the first metal layer 130 in order to create a sufficiently large creepage distance CD. In contrast, in case the at least partially insulating layer 150 is relatively thick, the width of the one or more voids 180 may be relatively small. In other words, the second metal layer 140 may be undercut to a relatively small degree with respect to the first metal layer 130, as the at least partially insulating layer 150 by virtue of its thickness may contribute to a large extent to the creepage distance CD of the electronic arrangement 100. The creepage distance CD may be 0.1-3 mm, such as 0.5-1.2 mm, such as 0.5-0.7 mm. The thickness of the second metal layer may be 0.1-1.6 mm, such as 0.2-0.5 mm, such as 0.24-0.36 mm. In particular, if Al is provided as the second metal layer, the thickness of the second metal layer of Al may be approximately 0.3 mm.
[0048] FIG. 3 is a schematic, cross-sectional view of an electronic arrangement 100 according to an exemplifying embodiment of the present invention. The electronic arrangement 100 as shown has many features in common with the electronic arrangement 100 of FIG. 2a, and it is hereby referred to the caption of FIG. 2a for an increased understanding of the partitioning operation of the electronic arrangement 100. In FIG. 3, the at least partially insulating layer 150 and the first metal layer 130 comprise a respective indentation 310, 320 at the partition portion 160 for facilitating a partitioning (cutting) of the electronic arrangement 100 at the partition portion 160. It should be noted that the electronic arrangement 100 may alternatively comprise only one indentation at the partition portion 160, i.e. the indentation 310 of the insulating layer 150 or the indentation 320 of the first metal layer 130. It should be noted that features of the indentations 310, 320 such as the shape, the arrangement, etc., of the indentations may differ from that disclosed which are schematically indicated.
[0049] FIG. 4a is a schematic top view of an electronic arrangement 100 according to an exemplifying embodiment of the present invention. In this embodiment, the electronic arrangement 100 consists of six sub-sections 100a-f arranged in series along the axis A, wherein each of the six sub-sections 100a-f comprises six electronic components 110a-f. It will be appreciated that the number of sub-sections and the number of electronic components of the electronic arrangement 100 are arbitrary, and that the electronic arrangement 100 as depicted is merely shown as an example. The electronic arrangement 100 may be partitioned (cut) at one or more of the partition portions 160a-e which are arranged between two adjacently arranged electronic components of two adjacently arranged sub-sections of the electronic arrangement 100. The partitioning or cutting at the partition portions 160a-e along the axis B is schematically indicated by the pair of scissors 20a-e. It will be appreciated that the configuration of the electronic arrangement 100 at the partition portions 160a-e are the same or similar to that described in FIGS. 2a-b, and it is hereby referred to those figures for an increased understanding. Hence, the electronic arrangement 100 may be partitioned or cut at one or more of the partition portions 160a-e such that the second metal layer is undercut with respect to the first metal layer, resulting in a sufficiently large creepage distance between the first and second metal layers as described previously.
[0050] It should be noted that the electronic arrangement 100 in FIG. 4a may comprise connectors (not shown) at the partition portions 160a-e. In this way, the electronic arrangement 100 may be partitioned or cut such that one or more of the resulting sub-sections 100a-f may constitute an electronic arrangement. For example, an electronic arrangement 100 of a first length (e.g. about 0.61 m, which substantially corresponds to 2 foot) may be partitioned into two (sub) electronic arrangements of half the first length (i.e. about 0.30 m, which substantially corresponds to 1 foot).
[0051] FIG. 4b is a schematic bottom view of an electronic arrangement 100 according to the exemplifying embodiment of the present invention shown in FIG. 4a. Here, the electronic arrangement 100 shows the respective void 180a-e at the respective partition portion 160a-e, at which the electronic arrangement 100 may be partitioned or cut.
[0052] FIG. 5a is a schematic top view of an electronic board 400 according to an exemplifying embodiment of the present invention. The electronic board 400 comprises a plurality of electronic arrangements 100.sub.1-6 according to any one of the preceding embodiments. The electronic arrangements 100.sub.1-6 are arranged adjacently side-by-side in a first plane such that partition portions 160.sub.1-6 of adjacently arranged electronic arrangements are arranged along second axis B in the first plane for partitioning the electronic board 400 along the second axis B. Hence, the electronic board 400 extends in two dimensions in a first plane and may be partitioned (cut) into smaller portions or segments along the second axis B. The partitioning or cutting at the partition portions 160.sub.1-6 along the axis B is schematically indicated by the pair of scissors 20.
[0053] FIG. 5b is a schematic bottom view of an electronic board 400 according to the exemplifying embodiment of the electronic board 400 of FIG. 5a. Here, the electronic board 400 shows the respective void 180.sub.1-6 of the respective partition portion 160.sub.1-6 at which the electronic board 400 may be partitioned or cut along axis B.
[0054] FIG. 6 is a schematic illustration of a method 500 of manufacturing an electronic arrangement according to an exemplifying embodiment of the present invention. The method 500 comprises the step of arranging 510 a first metal layer on an at least partially insulating layer, wherein the first metal layer and the at least partially insulating layer extend along a first axis. The step of arranging 510 the first metal layer may, as an example, comprise a lamination of a (dielectric) foil and a Cu foil. The method further comprises the step of providing 520 a second metal layer extending along the first axis and forming at least one void in the second metal layer having a width which extends parallel to the first axis. The step of providing 520 the second metal layer may, as an example, comprise a stamping of an Al substrate. As a further example, the method may comprise laminating the (dielectric) foil and the Cu foil onto the Al substrate, patterning the Cu-layer, adding a solder mask and pattering the solder mask. The method further comprises the step of arranging 530 a plurality of electronic components in an array on the carrier along the first axis. The step of arranging 530 the plurality of electronic components may, as an example, comprise applying a solder paste and arrange the electronic components on the carrier by a pick-and-place method. The method further comprises the step of forming 540 at least one partition portion between two adjacently arranged electronic components for partitioning the electronic arrangement along a second axis, B, of the at least one partition portion perpendicular to the first axis by arranging the second metal layer under the at least partially insulating layer such that the at least one void is intersected by the second axis and such that, at the second axis, the second metal layer is undercut with respect to the first metal layer, in a direction parallel to the first axis. It should be noted that the steps of the above-mentioned method 500 may be performed in the order as described, or alternatively, be performed in a different order.
[0055] The person skilled in the art realizes that the present invention by no means is limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, the first metal layer, the second metal layer, the at least partially insulating layer, the partition portion(s), the void(s), etc., may have different dimensions and/or sizes than those depicted and/or described. For example, one or more of the layers may be thicker or thinner than exemplified in the figures.
