PRINTED CIRCUIT BOARDS WITH NON-FUNCTIONAL FEATURES

Abstract

A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

Claims

1. A printed circuit board (PCB) comprising: a stack of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board; one or more holes each of which passes through one or more of the layers; and one or more conductive vias each of which is formed in a corresponding one of the one or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers; wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs), each NFF physically contacting a corresponding via that is one of the one or more vias, wherein an interface between each NFF and the corresponding via does not completely laterally surround the corresponding via. wherein at least one of the vias physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the via.

2. The PCB of claim 1, wherein each NFF is integral with its corresponding via.

3. The PCB of claim 1, wherein in top view, at least one NFF forms a ring sector, and the interface between the NFF and the corresponding via is an arc of an inner circle of the ring sector.

4. The PCB of claim 1, wherein for at least one said NFF, the hole containing the corresponding via passes through the PCB, and the corresponding via passes through a length of the hole but not the entire hole, the hole's diameter being enlarged in the hole's portion beyond the via.

5. The PCB of claim 1, wherein the one or more conductive vias comprise a pair of differential vias, and the stack of layers comprises a first plurality of layers each of which comprises two NFFs each of which physically contacts a corresponding one of the differential vias.

6. The PCB of claim 5, wherein for each differential via of the pair, for the corresponding NFFs physically contacting the via in the first plurality of layers, for any two layers that are consecutive in the first plurality of layers, the corresponding NFFs are at different angular positions relative to the via.

7. The PCB of claim 6, wherein each differential via of the pair physically contacts only one NFF in each of the first plurality of layers.

8. The PCB of claim 7, wherein for any two consecutive layers in the first plurality of layers, the corresponding two NFFs in one of the consecutive layers are rotated around their respective vias by a predefined angle relative to the corresponding two NFFs in the other one of the consecutive layers.

9. The PCB of claim 8, wherein in at least one layer of the first plurality of layers, each of the corresponding two NFFs that physically contacts one of the vias of the pair faces away from the other via of the pair.

10. The PCB of claim 5, wherein all the NFF physically contacting the differential vias are in the first plurality of layers.

11. A printed circuit board (PCB) comprising: a stack of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board; one or more holes each of which passes through one or more of the layers; and one or more conductive vias each of which is formed in a corresponding one of the one or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers; wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs), each NFF physically contacting a corresponding via that is one of the one or more vias, but not completely laterally surrounding the corresponding via; wherein at least one of the vias physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the via.

12. The PCB of claim 11, wherein in top view, at least one NFF protrudes from the corresponding via as a strip running along the corresponding via's circumference and having a uniform width.

13. The PCB of claim 11, wherein the one or more conductive vias comprise a pair of differential vias, and the stack of layers comprises a first plurality of layers each of which comprises two NFFs each of which physically contacts a corresponding one of the differential vias.

14. The PCB of claim 13, wherein for each differential via of the pair, for the corresponding NFFs physically contacting the via in the first plurality of layers, for any two layers that are consecutive in the first plurality of layers, the corresponding NFFs are at different angular positions relative to the via.

15. The PCB of claim 14, wherein each differential via of the pair physically contacts only one NFF in each of the first plurality of layers.

16. The PCB of claim 15, wherein for any two consecutive layers in the first plurality of layers, the corresponding two NFFs in one of the consecutive layers are rotated around their respective vias by a predefined angle relative to the corresponding two NFFs in the other one of the consecutive layers.

17. The PCB of claim 16, wherein in at least one layer of the first plurality of layers, each of the corresponding two NFFs that physically contacts one of the vias of the pair faces away from the other via of the pair.

18. The PCB of claim 13, wherein all the NFF physically contacting the differential vias are in the first plurality of layers.

19. A method for manufacturing a printed circuit board (PCB), the method comprising: forming a plurality of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board, wherein each of one or more of the layers comprises one or more conductive features each of which comprises one or more non-functional features (NFFs); then attaching the layers to each other to form a stack of the layers; then forming one or more holes through one or more of the layers, wherein each of one or more of the holes has a boundary shared with at least one NFF that does not completely laterally surround the hole; then forming one or more conductive vias comprising a portion of the circuitry and passing through one or more of the layers, each via being formed in a corresponding one of the one or more holes, wherein the boundary of each NFF physically contacts a via formed in the hole sharing the boundary with the NFF; wherein at least one of the vias physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the via.

20. The method of claim 19, wherein the one or more conductive vias comprise a pair of differential vias, and the stack of layers comprises a first plurality of layers each of which comprises two NFFs each of which physically contacts a corresponding one of the differential vias.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 is a perspective view of components interconnected by a PCB according to prior art.

[0016] FIG. 2 is a perspective view of a prior art PCB in the process of manufacture.

[0017] FIG. 3 is a perspective view of a prior art PCB.

[0018] FIGS. 4, 5, 6 are exploded views of prior art PCBs.

[0019] FIG. 7A is an exploded view of a PCB according to some embodiments of the present invention.

[0020] FIG. 7B shows a horizontal cross section of a PCB according to some embodiments of the present invention.

[0021] FIGS. 8 and 9 are top views of PCBs according to some embodiments of the present invention.

[0022] FIG. 10 shows loss versus frequency plots for simulated PCB embodiments of the present invention and prior art.

[0023] FIGS. 11 and 12 are exploded views of PCBs according to some embodiments of the present invention.

[0024] FIG. 13 shows a horizontal cross section of a PCB according to some embodiments of the present invention.

DETAILED DESCRIPTION

[0025] This section describes some embodiments of the present disclosure. The invention is not limited to such embodiments except as defined by the appended claims.

[0026] This disclosure uses the following terminology. The terms insulator, insulating, etc. refer to electrical insulation unless stated otherwise. Likewise, the terms conductor, conductive, etc. refer to electrical conductivity unless stated otherwise. The terms capacitor, capacitance, etc. refer to electrical capacitance unless stated otherwise.

[0027] FIG. 7A illustrates an embodiment of the present disclosure, similar to FIG. 6, but with slivers 710 instead of non-functional pads 310n. FIG. 7B shows a horizontal cross-sectional across a sliver 710. Each sliver 710 can be shaped as a sector of a non-functional pad 310n of FIG. 6, but other shapes can be also used. In the example of FIGS. 7A, 7B, each hole 238 is round in top view. Via 134 is a circular (cylindrical) liner on the hole's sidewalls. Sliver 710 is a sector of a ring surrounding the hole 238. The sliver thickness can be, for example, as large as the thickness of non-functional via 310n of FIG. 6. In some embodiments, the diameter of hole 238 is 12 mil; the outer diameter of sliver 710 is 14 mil; and the angle spanned by sliver 710 is 20 to 150, e.g. 70. The backdrilled hole 510 is unfilled, and has a diameter of 50 mil. In other embodiments, the backdrilled hole 510 is partially or completely filled with epoxy, or is absent. Other shapes and dimensions are possible. Further, different slivers 710 may have different shapes or dimensions at the same via 134 and/or at different vias in the same PCB.

[0028] Due to its smaller area, sliver 710 adds less parasitic capacitance than a non-functional pad of the same diameter.

[0029] In FIGS. 7A and 7B, every two consecutive slivers 710 down the via 134 are positioned on opposite sides of the via, and they have identical shapes and dimensions, in order to provide greater rotational uniformity of thermal stresses. The slivers are rotationally symmetric in top view relative to each other; the rotation axis is the center axis of hole 238, and the rotation angle is 180 between the slivers. In some embodiments, other rotation angles are used, e.g. 60 in FIG. 8, which shows the top view of three slivers at three respective different planes 216.

[0030] The invention is not limited to rotation angles or symmetry. The slivers can be provided at different vias as needed to achieve desired capacitances or other electrical characteristics and improve mechanical integrity of the structure. Some vias may have no slivers. Non-functional pads 310n may or may not be used in the same PCB in addition to slivers 710.

[0031] Each sliver 710 is positioned in a respective layer 210 corresponding to a ground plane, or a power voltage plane, or some other reference voltage plane. Slivers 710 can also be part of a signal plane. In some embodiments, a sliver is provided as an isolated feature of a signal plane, at a via not physically contacting any part of the signal plane other than the sliver.

[0032] FIG. 9 is a top view of a differential via pair, carrying a differential signal. The sliver 710 at each via faces away from the other via to minimize the capacitive coupling between the slivers and prevent a dip in the differential impedance and hence to increase the differential signal speed and integrity. The slivers 710 may or may not be part of the same plane 216.

[0033] FIG. 10 shows two graphs of simulated insertion loss versus frequency for respective two differential via structures. The top curve is obtained for the structure as in FIG. 4, without either non-functional pads or slivers. The bottom curve is obtained for a structure as in FIGS. 7A, 7B. In both cases, the distance between the via centers was 1 mm; each via's hole 238 diameter was 12 mils; the outer diameter of each pad 310, and of each sliver 710, was 14 mils; and the stub 510 diameter was 50 mils. Each sliver 710 spanned the angle of 70. Clearly, the insertion loss is almost the same in the two structures.

[0034] FIGS. 11 and 12 illustrate two differential via structures with slivers 710. Contact pads 1010 are to be soldered to respective contact pads of surface mount components 120 (not shown in FIGS. 11 and 12). In other embodiments, at least some contact pads of components 120 are soldered directly to top pads 310, e.g. as in Via in Pad Plated Over (VIPPO) structures.

[0035] In FIGS. 11 and 12, each of a number of planes 216 is provided with two slivers 710 at the respective two vias. The planes are ground or power voltage planes in some embodiments, though other types of planes can be used. In FIG. 11, in each plane having slivers, the slivers are on the opposite sides of each other, and the sliver at each via is on the opposite side of the other via, to minimize the capacitive coupling between the slivers and reduce differential impedance dip. In FIG. 12, the sliver positions change from plane to plane down the via: in one plane the slivers are as in FIG. 11; and in every subsequent plane having slivers, the slivers are rotated around their respective vias by some angle (the same angle for both slivers). The thermal stress reduction can be more uniform than in FIG. 11. Other sliver positions are also possible.

[0036] The slivers can be provided at buried vias and at blind vias.

[0037] The slivers can be manufactured by conventional methods. For example, each substrate 220 can be provided with a conductive layer (copper or another material) patterned to provide traces 130 or a ground or power voltage plane, and also to provide slivers 710 in some or all of the planes. The patterning can be additive or subtractive as known in the art. Then the substrates can be attached to each other to form a stack as described above in connection with FIG. 3, and the stack can be pierced with holes 238. The holes can be lined or filled with conductor 134.

[0038] Some embodiments of the present disclosure are defined by the following clauses.

[0039] Clause 1 defines a printed circuit board (PCB) comprising:

[0040] a stack of layers (e.g. 210) each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board (the circuitry may include a signal plane 216S, a ground plane, a power voltage plane, a reference voltage plane);

[0041] one or more holes (e.g. 238) each of which passes through one or more of the layers; and

[0042] one or more conductive vias (e.g. 134) each of which is formed in a corresponding one of the one or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers;

[0043] wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs, e.g. 710), each NFF physically contacting a corresponding via that is one of the one or more vias, wherein an interface between each NFF and the corresponding via does not completely laterally surround the corresponding via.

[0044] 2. The PCB of clause 1, wherein each NFF is integral with its corresponding via. (For example, a sliver 710 can be continuous with the via 134, e.g. a continuous monocrystalline copper structure.)

[0045] 3. The PCB of clause 1 or 2, wherein each NFF comprises over 50 mass % of metal (e.g. copper), and the corresponding via comprises over 50 mass % of the same metal.

[0046] 4. The PCB of any preceding clause, wherein for each NFF, the corresponding via physically contacts, in the corresponding layer, only the NFF and the insulator.

[0047] 5. The PCB of any preceding clause, wherein in top view, at least one NFF forms a ring sector, and the interface between the NFF and the corresponding via is an arc of an inner circle of the ring sector. (See FIG. 7B for example. If the via is circular, the sliver 710 may or may not be concentric with the via.)

[0048] 6. The PCB of clause 5, wherein the ring sector spans an angle of at most 150. (The ring sector angle is shown as A in FIG. 13, which is otherwise an enlarged copy of FIG. 7B.)

[0049] 7. The PCB of any preceding clause, wherein in top view, for at least one NFF, the corresponding interface has a length of at most 150/360 of a length of the corresponding via's circumference at the corresponding layer. (For example, if the angle A in FIG. 13 is 150, then the via-sliver interface is 150/360 of the via's circumference.)

[0050] 8. The PCB of clause 7, wherein the corresponding via physically contacts, in addition to the NFF, only the insulator in the corresponding layer. (For example, if the corresponding layer is a ground plane, and the via does not physically contact the ground plane, the via may contact only the sliver and the insulator of the corresponding layer.)

[0051] 9. The PCB of any preceding clause, wherein for at least one said NFF, the hole containing the corresponding via passes through the PCB, and the corresponding via passes through a length of the hole but not the entire hole, the hole's diameter being enlarged in the hole's portion beyond the via. (For example, the backdrilled hole 510 may have a larger diameter than the rest of the hole.)

[0052] 10. The PCB of any preceding clause, wherein for at least one said NFF, the corresponding via is one of a pair of differential vias.

[0053] 11. The PCB of clause 10, wherein each via in the pair physically contacts at least one NFF.

[0054] 12. The PCB of clause 10 or 11, wherein at least one NFF physically contacting one of the vias of the pair faces away from the other via of the pair.

[0055] 13. The PCB of clause 10, 11, or 12, wherein each via of the pair physically contacts one or more NFFs facing away from the other via of the pair.

[0056] 14. The PCB of clause 10, 11, 12, or 13, wherein at least one of the vias of the pair physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the corresponding via.

[0057] 15. The PCB of clause 14, wherein the other one of the vias of the pair physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the corresponding via.

[0058] 16. A printed circuit board (PCB) comprising:

[0059] a stack of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board;

[0060] one or more holes each of which passes through one or more of the layers; and

[0061] one or more conductive vias each of which is formed in a corresponding one of the one or more holes, each via comprising a portion of the circuitry and passing through one or more of the layers;

[0062] wherein each of one or more of the layers comprises one or more conductive non-functional features (NFFs), each NFF physically contacting a corresponding via that is one of the one or more vias, but not completely laterally surrounding the corresponding via.

[0063] 17. The PCB of any preceding clause, wherein in top view, at least one NFF protrudes from the corresponding via as a strip running along the corresponding via's circumference and having a uniform width. (For example, in FIG. 7B, the sliver is a ring sector whose width is the difference between the outer and inner ring diameters.)

[0064] 18. The PCB of any preceding clause, wherein in top view, at least one NFF is a strip running along the corresponding hole's boundary and having a uniform width. (For example, in FIG. 7B, the sliver runs along the via's circumference, which in turn abuts the hole's boundary.)

[0065] 19. The PCB of any preceding clause, wherein for at least one NFF, the corresponding via is one of a pair of differential vias.

[0066] 20. A method for manufacturing a printed circuit board (PCB), the method comprising:

[0067] forming a plurality of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board, wherein each of one or more of the layers comprises one or more conductive features each of which comprises one or more non-functional features (NFFs); then

[0068] attaching the layers to each other to form a stack of the layers; then

[0069] forming one or more holes through one or more of the layers, wherein each of one or more of the holes has a boundary shared with at least one NFF that does not completely laterally surround the hole; then

[0070] forming one or more conductive vias comprising a portion of the circuitry and passing through one or more of the layers, each via being formed in a corresponding one of the one or more holes, wherein the boundary of each NFF physically contacts a via formed in the hole sharing the boundary with the NFF.

[0071] Although illustrative embodiments have been shown and described, a wide range of modification, change and substitution is contemplated in the foregoing disclosure and in some instances, some features of the embodiments may be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the embodiments disclosed herein.