HIGH-SPEED LINEAR CHARGE PUMP CIRCUITS FOR CLOCK DATA RECOVERY

Abstract

The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.

Claims

1. A communication system comprising: a variable gain amplifier (VGA) configured to generate an amplified data signal based on a received data signal; a first sampler configured to generate a first data signal based on the amplified data signal; a second sampler configured to generate a second data signal based on the amplified data signal; a phase detector configured to generate an early signal and a late signal using at the first data signal and the second data signal; and a charge pump circuit comprising a bias section and a switch section, the bias section being configured to generate a first bias signal and a second bias signal, the switch section being configured for generating a charge current, the switch section comprises a first switch coupled to the early signal and a first resistor directly coupled to the first switch, the switch section further comprising a second switch coupled to the late signal and a second resistor directly coupled to the second switch.

2. The communication system of claim 1 wherein the charge pump circuit further comprises a digital-to-analog converter (DAC) for providing a control current to the bias section, wherein the bias section is configured to control magnitudes of the first and second bias signal according to the control current.

3. The communication system of claim 1 wherein the charge pump circuit further comprises a loop-filter resistor and a first capacitor, the loop-filter resistor being coupled to the first resistor.

4. The communication system of claim 1 wherein the first switch comprises a PMOS transistor, a gate of the PMOS transistor is coupled to the early signal.

5. The communication system of claim 4 wherein a drain of the PMOS transistor is coupled to the first resistor.

6. The communication system of claim 1 further comprising a voltage controlled oscillator coupled to the charge pump circuit.

7. The communication system of claim 1 wherein the switch section further comprises a third switch having a first terminal coupled to an inverse early signal and having a second terminal directly coupled to the first resistor.

8. The communication system of claim 1 wherein the bias section comprises an operational amplifier coupled to a voltage source.

9. The communication system of claim 1 wherein the first sampler comprises a data sampler, and the second sampler comprises an edge sampler.

10. The communication system of claim 1 further comprising a clock data recovery circuit, the clock data recovery circuit comprising the phase detector and the charge pump circuit.

11. A clock data recovery (CDR) circuit comprising: a phase detector configured to generate an early signal and a late signal using at least a first sample signal and a second sample signal; a voltage controlled oscillator configured got generate a clock signal based on a control voltage; and a charge pump circuit configured to generate the control voltage using at least the early signal and the late signal, the charge pump circuit comprising: a bias section configured to generate a first bias signal and a second bias signal; a loop filter; and a switch section configured for generating a charge current, the switch section comprises a first switch coupled to the early signal and a first resistor directly coupled to the first switch, the switch section further comprising a second switch coupled to the late signal and a second resistor directly coupled to the second switch.

12. The CDR circuit of claim 11 comprising a data sampler for generating the first sample signal and an edge sampler for generating the second sample signal.

13. The CDR circuit of claim 12 wherein the data sampler and the edge sampler are coupled to the voltage control oscillator.

14. The CDR circuit of claim 11 wherein the first sample signal comprises in-phase data and the second sample signal comprises quadrature signal.

15. The CDR circuit of claim 11 wherein the switch section further comprises a third switch coupled to an inverse early signal.

16. The charge pump circuit of claim 11 further comprising a capacitance coupled to a drain terminal of the first switch.

17. A serializer/deserializer system comprising: a communication interface for receiving data signal; a variable gain amplifier (VGA) configured to generate an amplified data signal based on the data signal; a first sampler configured to generate an in-phase signal based on the amplified data signal; a second sampler configured to generate a quadrature signal based on the amplified data signal; a phase detector configured to generate an early signal and a late signal using at the in-phase signal and the quadrature signal; a charge pump circuit configured to generate a control voltage and comprising a bias section and a switch section, the switch section comprises a first switch coupled to the early signal and a first resistor directly coupled to the first switch, the switch section further comprising a second switch coupled to the late signal and a second resistor directly coupled to the second switch; and a voltage controlled oscillator configured to generate a clock signal based on the control voltage.

18. The serializer/deserializer system of claim 17 wherein the first sampler and the second sampler are coupled to the voltage controlled oscillator.

19. The serializer/deserializer system of claim 17 further comprising a loop filter coupled to the charge pump circuit.

20. The serializer/deserializer system of claim 17 further comprising a loop filter coupled to the bias section, the bias section being configured to generate bias signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following diagrams are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many other variations, modifications, and alternatives. It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this process and scope of the appended claims.

[0015] FIG. 1 is a simplified diagram illustrating a clock data recovery circuit 100.

[0016] FIG. 2 is a diagram illustrating a conventional charge pump circuit with current control.

[0017] FIG. 3 is a diagram illustrating another conventional charge pump circuit.

[0018] FIG. 4 is a graph illustrating performance of conventional charge pump implantations as illustrated in FIG. 3.

[0019] FIG. 5A is a simplified diagram illustrating an exemplary charge pump circuit according to embodiments of the present invention.

[0020] FIG. 5B is a timing diagram illustrating operation of an exemplary charge pump circuit according to embodiments of the present invention.

[0021] FIG. 6 is a graph illustrating charge pump current according to embodiments of the present invention.

[0022] FIG. 7 is a graph illustrating performance of a charge pump according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.

[0024] As mentioned above, clock data recovery (CDR) circuits have a wide range applications. For example, CDR is widely used in data transfer and data communication. In a CDR implementation, a charge pumps takes the output of a phase detector and converts into a current signal. FIG. 1 is a simplified diagram illustrating a clock data recovery circuit 100. For example, charge pump circuits according to embodiments of the present invention can be deployed in the CDR circuit 100. The CDR circuit 100 receives data from a variable gain amplifier (VGA). The CDR circuit 100 samples the received data with its data sampler 101 and edge sampler 102. Data sampler 101 generates I-data (in-phase) and edge sampler 102 generates Q-data (quadrature). Phase detector 103 performs phase detection (e.g., using a Bang-Bang phase-detector) using the I-data and q-data respectively received from data sampler 101 and the edge sampler 102. Based on the phase detection, phase detector 103 generates an early signal and a late signal, which are transmitted to charge pump 104. Together, the data sampler and the edge sampler approximate the phase of the clock with respect to the data. For example, the data sampler and the edge sampler can be implemented using sense-amplifier based regeneration flip-flops. For example, data sampler 101, edge sampler 102, and phase detector 103 are considered the first stage of the CDR circuit 100, while the charge pump is considered the second stage of the CDR circuit. Charge pump 104 is configured to generate control voltage for the voltage-controlled oscillator (VCO) 106. VCO 106 generates a clock signal based on the control voltage. For example, charge pump 104 may be implemented according to embodiments of the present invention. The charge pump (CP) 104 uses the early/late signal from the phase detector (PD) to generate and inject a controlled amount of charge onto the loop filter (LPF), and the filtered signal is used to drive the VCO to the correct frequency and phase. The clock output from the VCO 106 is provided to the data sampler and the edge sampler for phase correction. The VCO 106 generates clock signals for both data sampler 101 (I-clock signal) and edge sampler 102 (Q-clock signal).

[0025] Based on the early/late signals from Phase detector, charge pump 104 injects a controlled amount of charge onto the loop filter 105. For good performance, the amount of charge from the charge pump 104 should be same in early phase and late phase, as mismatch in the amount of charge would create static phase offset between the incoming data and VCO clock. As the Bang-Bang phase detector switches from early to late or late to early, the charge pump would introduce charge glitches. Mismatch or incorrect amount of charge would create undesirable phase offset between the clock edge and center of the data eye. During the switching from one phase to another phase, the amount of glitch charge introduced into the loop filter should be very small relative to the actual charge that is used to operate the VCO 106. It is to be appreciated that embodiments of the present invention effectively reduces undesirable charge glitches at the charge pump.

[0026] FIG. 2 is a diagram illustrating a conventional charge pump circuit with gain control. The behavior the charge pump circuit in FIG. 2 is controlled by the switches. When the late signal is high, switches S.sub.1 and S.sub.4 are on and charge pump current (the current of transistor M.sub.5) is injected into the loop filter and charges the filter. When the early signal is high, switches S.sub.2 and S.sub.3 are on and charge pump current (current of transistor M.sub.3) flows out of the loop filter and discharges the filter. The operational amplifier of the charge pump reduces the charge sharing between the node Z and W during current switching. Unfortunately, there are various drawbacks with the charge pump implementation illustrated in FIG. 2. The sizes of transistors M.sub.5 and M.sub.3 depend on the mismatch requirement between currents. Generally, these transistors are bulky components of the circuit. The bulky size of transistors M.sub.5 and M.sub.3 often leads to undesirable (and often significant) parasitic at node X (e.g., capacitor C.sub.1) and node Y (e.g., capacitor C.sub.2). During early/late switching, glitch current resulting from charging/discharging of capacitor C.sub.1 and capacitor C.sub.2 can be high, and hence this architecture is at least unsuitable for low current high linear charge pump. It is also be noted that charge pump noise depends on the transconductance of transistors M.sub.5 and M.sub.3. The noise attribute to the charge pump usually contributes significant amount to the overall CDR jitter. To address this issue, a low noise architecture is implemented by relying on substantially noise-less resisters and transistor currents.

[0027] FIG. 3 is a diagram illustrating another conventional charge pump circuit. The charge pump circuit includes two sections: CP Bias and CP Switch. The CP Bias section creates a pair of differential voltages (Bias_p and Bias_n as shown) around the loop filter output voltage as common mode. Node voltages bias_p and bias_n are fully differential bias voltages and their magnitudes can be controlled by the DAC. The opamp (op.sub.1) at the CP Bias section adjusts the NMOS (N.sub.1) current to be equal to the DAC current. The operation of the CP Switch section is based on the early (E) and late (L) signals, and it converts bias_p and bias_n voltages into current. For example, the charge put current I.sub.CP can be expressed in the equation bellow:

[00001]$I_{C.Math.P}=\frac{V_{\mathrm{Bias\_p}}-V_{C.Math.P}}{R_{C.Math.P}}$

[0028] There are drawbacks associated with the charge pump illustrated in FIG. 3. During the transitions between Early/Late, node Y is disconnected from node X and connected to the loop filter (LFP) output. As a result, the parasitic capacitance C.sub.2 would share the charge from loop filter capacitor C.sub.1. This charging current is usually undesirably spiky, as there is no resistance in this path with the parasitic capacitor C.sub.2. The charge from the parasitic capacitor C.sub.2 would be added to the charge-pump current.

[0029] FIG. 4 is a graph illustrating performance of conventional charge pump implantations as illustrated in FIG. 3. When Early is high and Late is low, the current is positive, and vice versa. The desired current is about 23 A, but the current spikes causes capacitance C.sub.2 charging to about 170 A, which is undesirable for causing non-linearity and mismatch. The undesirable current is somewhat limited by the parasitic resistance in the charging path. It is to be appreciated that embodiments of the present invention effectively reduce the parasitic capacitance and improve charge pump performance.

[0030] The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0031] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

[0032] The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[0033] Furthermore, any element in a claim that does not explicitly state means for performing a specified function, or step for performing a specific function, is not to be interpreted as a means or step clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of step of or act of in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

[0034] Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object.

[0035] FIG. 5A is a simplified diagram illustrating an exemplary charge pump circuit 550 according to embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. A charge pump switch (CP Switch) section 500 receives bias signals Bias_P and Bias_N from the charge pump bias (CP Bias) section 510. CP Bias section 510 receives control signal from DAC 520, which as shown provides a current IDAC. Bias section 510 is additionally coupled to voltage V.sub.CP. Bias section 510 generates bias signals Bias_P and Bias_N as outputs. The charge pump section 500 receives the bias signals and generates an output current that is coupled to the loop filer (LPF). It is to be appreciate that charge pump section 500 generates much less undesirable glitch current compared to conventional charge pump designs.

[0036] As shown in FIG. 5A, Bias_P signal is coupled to the source of switch M.sub.P1 (implemented with a PMOS transistor), which is controlled by the early signal E coupled to its gate. Bias_N signal is coupled to the source of switch M.sub.N1 (implemented with an NMOS transistor), which is controlled by the late single L coupled to its gate. It is to be noted that the drains of transistors P.sub.4 and N.sub.3 in FIG. 3 are directly connected to each other and connected to the low-pass filter (LPF). For charge pump 550, the drain of switch M.sub.P1 is coupled to charge pump resistor R.sub.CP 503, and the drain of switch M.sub.N1 is coupled to the charge pump resistor R.sub.CP 504. It is also to be noted that resistors 503 and 504 are not directly coupled to bias signals Bias_P and Bias_N. Resistor 503 is connected to capacitance C.sub.2 via node Y as shown. At node Y, Bias_P signal needs to go through switch M.sub.P1 before reaching resistor 503 and capacitor C.sub.2. As explained above, undesirable parasitic capacitance is attributed to glitch charges from the low-pass filter (LPF) to capacitor C.sub.2. As shown, the LPF include resistor 501 and capacitor 502 and has a charge pump voltage of V.sub.CP. It is to be appreciated that resistor 503 effectively limits the amount of charge flows from LPF to capacitor C.sub.2 to a substantially negligible level, and the spike current from LPF (as shown in FIG. 4) is substantially minimized.

[0037] CP Switch section 500 additionally includes PMOS switch M.sub.P2. The source terminal of switch M.sub.P2 is coupled to node Y. The gate of switch M.sub.P2 is coupled to the inverted early signal as shown. An NMOS switch M.sub.N2 is coupled to switch M.sub.N1. More specifically, the drain of switch M.sub.N1 is coupled to the source of switch M.sub.N2. Switch M.sub.N2 is operated by the inverted late signal, which is coupled to its gate. Switch M.sub.P2 and switch M.sub.N2 share their drains at node X, which is also coupled to capacitor C.sub.1.

[0038] FIG. 5B is a timing diagram illustrating operation of an exemplary charge pump circuit according to embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the Late and Early signals are applied to switches M.sub.P1, M.sub.P2, M.sub.N1, and M.sub.N2. It is to be appreciated that the corresponding currents level at charge pump (CP) is stable with minimal spiking.

[0039] As an example, the exemplary charge pump illustrated in FIG. 5A and described above can be readily incorporated into a CDR. For example, CDR 100 illustrated in FIG. 1 includes charge pump 104, which can be implemented using the charge pump illustrated in FIG. 5A. For example, phase detector 103 generates early and late signals, which charge pump 550 uses to generate an output current. For example, early and late signals from phase detector 103 are coupled to switches M.sub.P1, M.sub.P2, M.sub.N1, and M.sub.N2. The output of charge pump 550 will charge or discharge the LPF 105.

[0040] The use of charge pump 550 in CDR 100 is merely one of the implementations. It is to be appreciated that charge pump 550 and variations thereof according to embodiments of the present invention can be used in a variety of applications and implementations. For example, there are other CDR devices can be implemented using the design of exemplary charge pump 550. Charge pumps according to embodiments of the present invention can also be implemented in other applications. For example, CDRs implemented according to embodiments of the present invention are used in various data communication devices, such as transceivers, SerDes, receivers, and others.

[0041] FIG. 6 is a graph illustrating charge pump current according to embodiments of the present invention. The plot shows the charge-pump current corresponding to early and late signals. When the Early signal is high and Late is low, the current is positive, and vice versa. The desired current is about 23 A, and as shown in FIG. 6, there is a negligible glitch current during Early to Late (or Late to Early) transition, which provides a significant advantage over the conventional charge pump designs.

[0042] FIG. 7 is a graph illustrating performance of a charge pump according to embodiments of the present invention. Plot 701 shows that charge pump current from a charge pump according to embodiments of the present invention gradually reaches the desired current level during each of the transitions. In comparison, current from a conventional charge pump shows large undesirable current spikes that would lead to poor performance.

[0043] While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.