METHOD FOR MINIMIZING DC CAPACITANCE FOR CASCADE MULTILEVEL CONVERTER

Abstract

A method for minimizing DC capacitance of a cascade multilevel converter is provided. On the basis of balancing of capacitor voltages, the method estimates instantaneous value of the DC side capacitor voltages in a circuit through an energy conservation law, and uses a proportional resonance controller to control a grid-connected current to realize adjustment of the grid-connected current without static difference, such that the cascade multilevel converter can operate in a small capacitance mode, the system volume is greatly reduced, the system cost is reduced, the control is easy to be implemented, and the capacitor voltage is free from overshoot and the system has a better rapidity.

Claims

1. A method for minimizing DC capacitance of a cascade multilevel converter, where in the method comprises steps of: step 1: measuring an initial value V.sub.n0(n=1, 2, . . . , N) of each of capacitor voltages of H-bridges and a grid-connected current i.sub.g, and then using an reactive current detection algorithm, to obtain an reactive current given signal I.sub.qref; step 2: as balancing the capacitor voltages, instantaneous estimation values of the capacitor voltages of N H-bridges are equal, that is, V.sub.c1=V.sub.c2=V.sub.c3= . . . =V.sub.cN, an expression for the instantaneous estimation values of the capacitor voltages of the H-bridges is: $V_{c.Math.n}=\sqrt{\frac{C.Math.V_{1.Math.0}^2+C.Math.V_{2.Math.0}^2+\mathrm{.Math.}+C.Math.V_{N.Math.0}^2+L.Math.i_g^2+2.Math.{}_{t_0}^t.Math.i_g.Math.v_g.Math.d.Math.t}{N.Math.C}}$ calculating to obtain a value of the instantaneous estimation value V.sub.cn(n=1, 2, . . . , N) of the capacitor voltage of the H-bridges; in the expression for the instantaneous estimation values of the capacitor voltage of the H-bridges, C is a capacitance value of each of the H-bridges in a cascade multilevel converter system; V.sub.10, V.sub.20, . . . , V.sub.N0 is the initial value V.sub.n0(n=1, 2, . . . , N) of the capacitor voltage of each of the H-bridges measured in the step 1; L is a total inductance value in the cascade multilevel converter system; i.sub.g is the grid-connected current value in the cascade multilevel converter system; v.sub.g is a grid voltage value in the cascade multilevel converter system; t.sub.0 is an initial time in the cascade multilevel converter system and t is a current time in the cascade multilevel converter system; Step 3: multiplying V.sub.cn(n=1,2, . . . , N) by the total number N of the H-bridges to obtain N*V.sub.cn, u.sub.cn=u.sub.c1+u.sub.c2+u.sub.c3+ . . . +u.sub.cN is a sum of the instantaneous values of the capacitor voltages of the H-bridges, and subtracting u.sub.cn from N*V.sub.cn as an input of the voltage control loop PR controller; when the grid voltage and the grid-connected current are in the same direction, a logic signal g is 1; and when the grid voltage and the grid-connected current are in the opposite direction, the logic signal g is 1; multiplying the output of the voltage control loop PR controller by the logic signal g to obtain a signal I.sub.dref; Step 4: subtracting the signal I.sub.dref from the reactive current given signal I.sub.qref, and then subtracting the grid-connected current i.sub.g as the input of the current control loop PR controller, and to be output as a modulation signal u.sub.ref; Step 5, dividing a sum u.sub.cn of the instantaneous values of the capacitor voltages of the N H-bridges by the total number N of the H-bridges to obtain an average value $\frac{.Math.u_{c.Math.n}}{N}$ of the instantaneous values of the capacitor voltages, and subtracting the instantaneous values u.sub.cn of the capacitor voltages of the H-bridges from the $\frac{.Math.u_{c.Math.n}}{N}$ as an input signal of a capacitor voltage balancing control loop PI controller; dividing the grid-connected current i.sub.g by a peak value of the grid-connected current to obtain an adjustment signal S; multiplying the output signal of the capacitor voltage balancing control loop PI controller by the adjustment signal S to obtain a fine adjustment signal u.sub.refn; and Step 6: adding the modulation signal u.sub.ref output by the current control loop PR controller to the fine adjustment signal u.sub.refn output by the capacitor voltage balancing control loop PI controller to obtain a modulation signal u.sub.refn, which generates a driving signal for controlling switches of the H-bridges through a PWM generator to control on-off of the switches.

2. The method for minimizing DC capacitance of a cascade multilevel converter according to claim 1, wherein a transfer function of the PR controller is $k_p+\frac{k_R.Math.s}{s^2+{}_0^2},$ in which k.sub.P is a proportional amplification coefficient, k.sub.R is a resonance coefficient and .sub.0 is a resonance angular frequency.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 is a schematic view of a cascade multilevel converter according to an embodiment of the present disclosure;

[0023] FIG. 2 is a schematic view of a control method in FIG. 1;

[0024] FIG. 3 is a waveform view of absolute values of a H-bridge DC side capacitor voltage and a grid according to the present disclosure;

[0025] FIG. 4 is a schematic waveform view of grid current according to the present disclosure; and

[0026] FIG. 5 is a schematic view of FFT analysis of the grid current in FIG. 4 according to the present disclosure.

DETAILED DESCRIPTION

[0027] Specific embodiments of the present disclosure will be further described in detail with reference to the accompanying drawings.

[0028] In this embodiment, under a situation of MATLAB/Simulink2013a, a method for minimizing DC capacitance of the cascade multilevel converter as provided in the present disclosure is simulated. As shown in FIG. 1, the cascade multilevel converter includes an inductance L and N H-bridges, wherein each of the H-bridges includes a DC side capacitance C and four switches S.sub.n1-S.sub.n1,S.sub.n1-S.sub.n4(n=1, 2, . . . N). In the simulation of this embodiment, N=3, that is, there are three H-bridges to be used, simulation parameters are shown in table 1 below:

TABLE-US-00001 TABLE 1 Simulation Parameters Initial value of the DC 100 V side capacitor voltage Filter inductor 5 mH Peak value of the grid 100 V voltage Peak value of the grid- 10 A connected current Switching frequency 10 kHz Capacitance value 60 F of the H-Bridge

[0029] FIG. 2 is a schematic view of a control method of the present disclosure, in which a capacitor voltage balancing control loop PI (Proportional-Integral) controller, a voltage PR (Proportional-resonant)controller, a current PR controller, and a carrier phase shift PWM;

[0030] Step 1: setting an initial value V.sub.n0(n=1, 2, 3) of the capacitor voltage of H-bridge to be 100V, and an reactive current given signal I.sub.qref=10 cos()(=02);

[0031] Step 2: on the basis of the capacitor voltage balancing, instantaneous estimation values of the capacitor voltage of the three H-bridges are equal, that is, V.sub.c1=V.sub.c2=V.sub.c3; the instantaneous estimation value V.sub.cn(n=1, 2, 3) of the capacitor voltage of each of the H-bridges can be obtained according to the formula (1);

[0032] Step 3: multiplying the instantaneous estimation value V.sub.cn(n=1, 2, 3) of each of the capacitor voltages of the H-bridges by total numbers 3 of the H-bridges to obtain 3*V.sub.cn, as a reference signal of the voltage control loop PR controller, a sum of the instantaneous estimation value of the capacitor values of each of the H-bridges is u.sub.cn=u.sub.c1+u.sub.c2+u.sub.c3, as a feedback signal of the voltage control loop PR controller;

[0033] subtracting the feedback signal u.sub.c1+u.sub.c2+u.sub.c3 from the reference signal 3*V.sub.cn(n=1, 2, 3) as input of the voltage control loop PR controller;

[0034] multiplying the output of the voltage control loop PR controller by a logic signal g to obtain an output signal I.sub.dref of the voltage control loop PR controller; when the grid voltage and the grid-connected current are in the same direction, the logic signal g is 1; and when the grid voltage and the grid-connected current are in the opposite directions, the logic signal g is 1;

[0035] a transfer function of the PR controller is

[00005]$k_p+\frac{k_R.Math.s}{s^2+{}_0^2},$

wherein k.sub.P is a proportional amplification coefficient, k.sub.R is a resonance coefficient, .sub.0 is a resonance angular frequency, the parameters of the voltage control loop PR controller are k.sub.P=0.01, k.sub.R=0.8 respectively; and the parameters of the current control loop PR controller are k.sub.P=0.5, k.sub.R=200 respectively;

[0036] Step 4: subtracting the output signal I.sub.dref of the voltage control loop PR controller from the reactive current given signal I.sub.qref, and then subtracting the grid-connected current i.sub.g as an input of the current control loop PR controller, and the output of the current control loop PR controller is a modulation signal u.sub.ref;

[0037] Step 5: dividing a sum u.sub.cn of the capacitor voltage instantaneous values of the three H-bridges by the total number N of the H-bridges to obtain an average value

[00006]$\frac{.Math.u_{\mathrm{cn}}}{3}.Math.\left(n=1,2,3\right)$

of the capacitor voltage instantaneous values, and subtracting the capacitor voltage instantaneous value u.sub.cn of each of the H-bridges from

[00007]$\frac{.Math.u_{c.Math.n}}{3}.Math.\left(n=1,2,3\right)$

as the input signal of the capacitor voltage balancing control loop PI controller;

[0038] dividing the grid-connected current i.sub.g by the peak value of the grid-connected current to obtain an adjustment signal; multiplying the output signal of the capacitor voltage balancing control loop PI controller by the adjustment signal S to obtain a fine adjustment signal u.sub.refn;

[0039] Step 6: adding the modulation signal I.sub.ref output by the current control loop PR controller to the fine adjustment signal u.sub.refn output by the capacitor voltage balancing control loop to obtain the modulation signal u.sub.refn of the cascade multilevel converter system, and then generating a drive signal by the PWM generator to drive the switches. In this embodiment, the carrier phase shift modulation is used to generate the drive signal, to be simply controlled and easily realized digitally.

[0040] Under the situation of the capacitor voltage balancing, a waveform view of the absolute values of the capacitor voltage on the DC side of the H-bridges and the grid voltage is shown in FIG. 3, and a waveform view of the grid current is shown in FIG. 4.

[0041] FFT analysis is performed on the grid current in FIG. 4, as a result shown in FIG. 5, the grid current THD=2.85% complies with the national power quality standard 14549-1993.

[0042] In the case of the same parameters, through the theoretical calculation, the traditional solution of controlling the average value of the capacitor voltage is adopted, and the required capacitance value is about 1.4 mF. In the solution as provided by the present disclosure, the capacitance value is 60 F , which can meet the system requirement, obviously reduce the capacitance value, and the capacitor voltage is free from overshoot and the system has a better rapidity.

[0043] In summary, the present disclosure provides a method for minimizing DC capacitance of a cascade multilevel converter, in which the proportional resonance controller is used for controlling the grid-connected current, to realize adjustment of the grid-connected current without static difference, such that the cascade multilevel converter can be operated in a small capacitance mode, thus greatly reducing cost of the system and easily controlling, and the capacitor voltage is free from overshoot and the system has better rapidity. In addition, compensation current range of the system can meet the system requirements when the system is operated in the small capacitance mode, and the output current quality and capacitor voltage control both can reach an ideal control target.

[0044] Finally, it should be noted that the above-mentioned embodiments are only used to illustrate the technical solution of the present disclosure, rather than limit the present disclosure. Although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by the person skilled in the art that it is allowable to modify the technical solution described in the foregoing embodiments or equivalently substituting some or all of the technical features; however, these modifications or substitutions do not cause the corresponding technical solutions to substantively depart from the scope of the technical solutions of various embodiments of the present disclosure.