Injection-locked oscillator with variable load impedance

Abstract

Injection-locked oscillator comprising: a control input receiving a control signal, the value of the natural frequency of the oscillator being a function of the amplitude of the control signal; a synchronisation input receiving a periodic synchronisation signal, the oscillator outputting an output signal with a frequency equal to the frequency of the synchronisation signal, and such that a phase shift between the output signal and the synchronisation signal depends on a difference between the natural frequency of the oscillator and the frequency of the synchronisation signal; a first load impedance onto which a load signal is applied; a second load impedance; a first coupling component periodically coupling the second load impedance to the first load impedance, at the synchronisation frequency.

Claims

1. An injection-locked oscillator comprising at least: one or several control inputs configured to receive one or several control signals, the oscillator being configured such that the value of its natural frequency depends on the amplitude of the control signal(s); a synchronisation input configured to receive a periodic synchronisation signal, the oscillator being configured to output an output signal with a frequency equal to the frequency of the synchronisation signal when the oscillator is locked to the frequency of the synchronisation signal, and such that a phase shift between the output signal and the synchronisation signal depends on a difference between the natural frequency of the oscillator and the frequency of the synchronisation signal; a first load impedance, the oscillator being configured such that a load signal is applied on the first load impedance; a second load impedance; a first coupling component configured to periodically couple the second load impedance to the first load impedance, at the frequency of the synchronisation signal, in parallel or in series, wherein each of the first and second load impedance comprises at least one of: a capacitor, a capacitive component, a coil, and an inductive component.

2. The injection-locked oscillator according to claim 1, wherein the oscillator is a relaxation oscillator.

3. The injection-locked oscillator according to claim 1, wherein the first coupling component comprises at least one first coupling transistor coupled in series or in parallel to the second load impedance.

4. The injection-locked oscillator according to claim 1, also comprising at least: a third load impedance, the oscillator being configured such that the load signal is applied on the third load impedance; a fourth load impedance; a second coupling component configured to periodically couple the fourth load impedance to the third load impedance, at the frequency of the synchronisation signal, in parallel or in series.

5. The injection-locked oscillator according to claim 4, also comprising at least: a flip-flop, of which a clock input is coupled to the first and second load impedances, including a reset input coupled to the third and fourth load impedances, and an output configured to output the oscillator output signal, or a lock, of which an input setting the lock into the low state is coupled to the first and second load impedances, of which an input setting the lock into a high state is coupled to the third and fourth load impedances, and of which an output is configured to output the oscillator output signal.

6. The injection-locked oscillator according to claim 5, wherein the first coupling component comprises at least one first coupling transistor coupled in series or in parallel to the second load impedance, and wherein a gate of the first coupling transistor is coupled to an output of a first NOR logic gate, a first input of which is coupled to the output of the flip-flop or the lock and a second input of which is configured to receive the synchronisation signal.

7. The injection-locked oscillator according to claim 4, wherein the second coupling component comprises at least one second coupling transistor coupled in series or in parallel to the fourth load impedance.

8. The injection-locked oscillator according to claim 5, wherein the second coupling component comprises at least one second coupling transistor coupled in series or in parallel to the fourth load impedance, and wherein a gate of the second coupling transistor is coupled to an output of a second NOR logic gate, a first input of which is coupled to an inverted output of the flip-flop or the lock and a second input of which is configured to receive an inverted signal of the synchronisation signal.

9. The injection-locked oscillator according to claim 5, wherein the oscillator comprises the flip-flop or the lock and: a first discharge transistor coupled in parallel to the first and second load impedances, the gate of which is coupled to the output of the flip-flop or the lock; a second discharge transistor coupled in parallel to the third and fourth load impedances, the gate of which is coupled to an inverted output of the flip-flop or the lock.

10. The injection-locked oscillator according to claim 5, wherein the oscillator comprises the flip-flop or the lock and: a first input transistor, a gate of which is coupled to the output of the flip-flop or the lock and configured such that the load signal, corresponding to a load current, is or is not applied on the first load impedance as a function of the conducting or blocked state of the first input transistor; a second input transistor, a gate of which is coupled to an inverted output of the flip-flop or the lock and configured such that the load signal is or is not applied on the third load impedance as a function of the conducting or blocked state of the second input transistor.

11. The injection-locked oscillator according to claim 1, wherein the control input or a first of the control inputs is coupled to the first load impedance such that the control signal or a first of the control signals forms the load signal.

12. The injection-locked oscillator according to claim 1, wherein: the first load impedance comprises at least one first capacitor and, when the oscillator comprises a third load impedance, the third load impedance comprises at least one second capacitor, or the first load impedance comprises at least one first capacitive transducer forming the control input or a second of the control inputs, the value of the natural frequency of the oscillator being a function of the value of the capacitance of the first capacitive transducer, and when the oscillator comprises the third load impedance, the third load impedance comprises at least one second capacitive transducer forming the control input or the second of the control inputs, the value of the natural frequency of the oscillator being a function of the value of the capacitance of the second capacitive transducer.

13. The injection-locked oscillator according to claim 5, wherein the oscillator comprises the flip-flop or the lock, and each of the load impedances is coupled to the flip-flop or the lock by means of at least one inverter, of which a threshold voltage control input forms the control input, or a third of the control inputs.

14. The injection-locked oscillator according to claim 1, wherein the oscillator is a harmonic oscillator comprising at least one LC circuit.

15. Oscillator according to claim 1, wherein the oscillator is a ring oscillator comprising at least an odd number of inverters greater than or equal to three, and such that an output of one of the inverters is coupled to the first load impedance.

16. The injection-locked oscillator according to claim 15, wherein an output of each of the inverters is coupled to a load impedance and to a coupling component configured to periodically couple another load impedance to said load impedance, at the frequency of the synchronisation signal and in parallel or series.

17. An interface circuit for a sensor, comprising at least one injection-locked oscillator according to claim 1, and a second oscillator of which an output is coupled to the synchronization input of the injection-locked oscillator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) This invention will be better understood after reading the description of example embodiments given purely for information and that is in no way limitative, with reference to the appended drawings on which:

(2) FIG. 1 shows an injection-locked oscillator used as a phase shifter;

(3) FIG. 2 shows an injection-locked oscillator according to a first embodiment;

(4) FIG. 3 shows an injection-locked oscillator according to a first variant of the first embodiment;

(5) FIG. 4 shows an injection-locked oscillator according to a second variant of the first embodiment;

(6) FIG. 5A shows an injection-locked oscillator according to a third variant of the first embodiment;

(7) FIG. 5B shows a controlled threshold voltage inverter used in the injection-locked oscillator according to the third variant of the first embodiment;

(8) FIG. 6 shows an injection-locked oscillator according to a second embodiment;

(9) FIG. 7 shows an injection-locked oscillator according to a third embodiment;

(10) FIG. 8 shows an interface circuit for a sensor according to one particular embodiment.

(11) Identical, similar or equivalent parts of the different figures described below have the same numeric references to facilitate comparison between the different figures.

(12) The different parts shown on the figures are not necessarily all at the same scale, to make the figures more easily understandable.

(13) The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

(14) An injection-locked oscillator 100 according to a first embodiment is described below with reference to FIG. 2.

(15) The oscillator 100 comprises a flip-flop 102 that, in the first embodiment, corresponds to a D flip-flop. The flip-flop 102 comprises a D data input coupled to an electric power supply potential VDD. A Q output of the D flip-flop 102 is connected to an output 103 of the oscillator 100 and is coupled to the gate of a first discharge transistor 104. A first electrode of the first discharge transistor 104, corresponding to the drain of the first discharge transistor 104 that is of the N type, is coupled to a first node 106. A second electrode of the first discharge transistor 104, corresponding to the source of the first discharge transistor 104, is coupled to the ground.

(16) The oscillator 100 also comprises a first load impedance 108. In this first embodiment, this first load impedance 108 corresponds to a first capacitor, or more generally a first capacitive component, with value C.sub.1. A first electrode of the first capacitor is coupled to the first node 106, and a second electrode of the first capacitor is coupled to the ground.

(17) A load current I.sub.0, in this case corresponding to a control signal received by the oscillator 100 (this control signal is symbolised by a current source 110 on FIG. 2) is applied on the first node 106, and therefore on the first load impedance 108, through a first input transistor 112. The Q output of the flip-flop 102 is coupled to the gate of the first input transistor 112.

(18) The oscillator 100 also comprises a second load impedance 114, and a first coupling component 116 controlled and configured to periodically couple the second load impedance 114 to the first load impedance 108. In this first embodiment, this second load impedance 114 corresponds to a second capacitor, or a second capacitive component, with value C.sub.synchro1 and the first coupling component 116 corresponds to a first coupling transistor 116. A first electrode of the second capacitor is connected to the first node 106. A second electrode of the second capacitor is connected to a first electrode of the first coupling transistor 116, and corresponds to the drain of the first coupling transistor 116 that is of the N type. A second electrode of the first coupling transistor 116, corresponding to the source of the first coupling transistor 116, is coupled to the ground.

(19) The gate of the first coupling transistor 116 is coupled to the output of a first NOR logic gate 118 comprising a first input coupled to the Q output of the flip-flop 102 and a second input onto which a synchronisation signal V.sub.synchro, with frequency f.sub.synchro, is applied. For example, the synchronisation signal corresponds to a square signal of which the high and low values are approximately equal to the values of the signal outputted on the Q output of the flip-flop 102. Due to the first NOR logic gate 118, the second load impedance 114 is coupled in parallel to the first load impedance 108 when the synchronisation signal V.sub.synchro and the output signal from the flip-flop 102 are both in the low state.

(20) The first node 106 is also coupled to the input of a first inverter 120, the output of this first inverter 120 being coupled to the input of a second inverter 122. The output of the second inverter 122 is coupled to the clock input of the flip-flop 102. These inverters 120, 122 straighten the front of the signal obtained on the first node 106 before it is applied on the clock input of the flip-flop 102.

(21) The Q output of the flip-flop 102 is also coupled to the input of a third inverter 124. Alternatively, the signal obtained on the output of the third inverter 124 corresponding to the inverted output signal Q, could be obtained on an inverted output of the flip-flop 102. The output of the third inverter 124 is coupled to the gate of a second discharge transistor 126.

(22) A first electrode of the second discharge transistor 126, corresponding to the drain of the second discharge transistor 126 that is of the N type, is coupled to a second node 128. A second electrode of the second discharge transistor 126, corresponding to the source of the second discharge transistor 126, is coupled to the ground.

(23) The oscillator 100 also comprises a third load impedance 130. In this first embodiment, this third load impedance 130 corresponds to a third capacitor, or a third capacitive component, with value C.sub.2. A first electrode of the third capacitor is coupled to the second node 128, and a second electrode of the third capacitor is coupled to the ground.

(24) The load current I.sub.0 is applied on the second node 128, and therefore on the third load impedance 130, through a second input transistor 132. The inverted output signal Q of the flip-flop 102 is applied on the gate of the second input transistor 132.

(25) The oscillator 100 also comprises a fourth load impedance 134, and a second coupling component 136 controlled and configured to periodically couple the fourth load impedance 134 to the third load impedance 108. In this first embodiment, this fourth load impedance 134 corresponds to fourth capacitor, or a fourth capacitive component, with a value C.sub.synchro2 and the second coupling component 136 corresponds a second coupling transistor.

(26) The values of the capacitors of the oscillator 100 herein are such that C.sub.1/C.sub.synchro1=C.sub.2/C.sub.synchro2.

(27) A first electrode of the fourth capacitor is connected to the second node 128. A second electrode of the fourth capacitor is connected to a first electrode of the second coupling transistor, corresponding to the drain of the second coupling transistor that is of the N type. A second electrode of the second coupling transistor, corresponding to the source of the second coupling transistor, is coupled to the ground.

(28) The gate of the second coupling transistor is coupled to the output of a second NOR logic gate 138 comprising a first input coupled to the output of the third inverter 124 and a second input onto which an inverted signal of the synchronisation signal V.sub.synchro, called V.sub.synchro and with frequency f.sub.synchro, is applied. Due to the second NOR logic gate 138, the fourth load impedance 134 is coupled in parallel to the third load impedance 130 when the signal V.sub.synchro and the inverted output signal Q of the flip-flop 102 are both in the low state.

(29) The second node 128 is also coupled to the input of a fourth inverter 140, the output of which is coupled to a reset input of the flip-flop 102. This inverter 140 straightens the signal front obtained on the second node 128 before it is applied on the reset input of the flip-flop 102.

(30) In the oscillator 100 described above, the transistors 104, 112, 116, 126, 132 and 136 may for example be MOSFET transistors. However, other types of transistor may be used.

(31) In the oscillator 100 shown on FIG. 2, the control signal corresponding to the load current I.sub.0 directly controls the natural frequency of the oscillator 100. The value of the natural frequency f.sub.0 of the oscillator 100 is a function of the amplitude of the load current I.sub.0, and therefore of the amplitude of the control signal received by the oscillator 100. This control signal may correspond to a measurement signal received by the oscillator 100, or it may correspond to a signal obtained from a measurement signal, for example a signal outputted at the output of a transconductance amplifier, one input of which receives the measurement signal.

(32) In this oscillator 100, synchronisation is not done by an injection of current (or voltage) additive to and then subtractive from the control signal of the oscillator 100 at the frequency of the synchronisation signal, but by a modification of the value of the load impedance(s) (the first and third load impedances 108, 130 in the first embodiment described above) of the oscillator 100, made at the frequency of the synchronisation signal f.sub.synchro. The value of this or these load impedances is modified by periodically coupling and decoupling one or several other load impedances (the second and fourth load impedances 114, 134 in the first embodiment described above), in series or in parallel (in parallel in the first embodiment described above) to this or these load impedances. Therefore in the first embodiment described above, the first load assembly comprising the first and second load impedances 108, 114 forms a capacitance for which the value alternates between the values C.sub.1 and C.sub.1+C.sub.synchro1. Therefore, similarly, the second load assembly comprising the third and fourth load impedances 130, 134 forms a capacitance for which the value alternates between the values C.sub.2 and C.sub.2+C.sub.synchro2.

(33) Thus, the oscillator 100 locks onto the frequency f.sub.synchro of the synchronisation signal V.sub.synchro by adjusting the phase of the signal outputted on the output 103, such that the value of the average load impedance of the oscillator 100 is equal to the value necessary such that the oscillator 100 is in free oscillation (with no synchronisation signal at the input to the oscillator 100) at the frequency f.sub.synchro of the synchronisation signal. Thus, the phase shift between the output signal outputted on the output 103 and the synchronisation signal V.sub.synchro is a function of the difference between the natural frequency f.sub.0 of the oscillator 100 and the frequency f.sub.synchro of the synchronisation signal V.sub.synchro.

(34) When C.sub.1=C.sub.2 and C.sub.synchro1=C.sub.synchro2, the signal obtained on the output 103 of the oscillator 100 has a cyclic ratio equal to 50% (on a period of this output signal, the duration of the high state is equal to the duration of the low state). The phase shift obtained between the synchronisation signal and the signal outputted on the output 103 of the oscillator 100 is then expressed by the following equation:

(35) $= [\frac{f_{synchro}}{f_{0}} (\frac{C_{1}}{C_{synchro 1}} + 1) - \frac{C_{1}}{C_{synchro 1}}]$

(36) In the above equation, the different terms (ratios C.sub.1/C.sub.synchro1 and f.sub.synchro/f.sub.0) are independent of the temperature of the environment in which the oscillator 100 functions when the oscillator producing the signal V.sub.synchro has the same topology as the injection-locked oscillator. Therefore the locking frequency range of the oscillator 100 is not dependent on this temperature, but is dependent on the variation of the value of load assemblies relative to their nominal value, in other words the total value of the first and second load impedances and the total value of the third and fourth load impedances relative to the value of the first load impedance alone and the value of the third load impedance alone, respectively. Furthermore, the locking frequency range of the oscillator 100 no longer depends on the amplitude of the control and synchronisation signals received by the oscillator 100.

(37) According to one variant embodiment, the values of capacitors C.sub.1 and C.sub.2 may be different from each other. In this case, the signal obtained on the output 103 of the oscillator 100 has a cyclic ratio different from 50%. In this variant, when the cyclic ratio is more than 50% and the oscillator 100 does not have the fourth load impedance 134, the phase shift obtained is expressed by the following equation:

(38) $= 2 .Math. .Math. (1 + \frac{C_{1}}{C_{synchro 1}}) [\frac{f_{synchro}}{f_{0}} + (\frac{C_{synchro 1}}{C_{1} + C_{synchro 1}}) - 1]$

(39) In particular, with such a variant the oscillator 100 can form a phase shifter that is linear over a phase range of more than pi.

(40) In the first embodiment described above, the oscillator 100 corresponds to a relaxation oscillator. The principle described above consisting of modifying the value of the load impedance(s) of the oscillator at the frequency of the synchronisation signal received by the oscillator may be applied to relaxation oscillators different from that described above.

(41) In the first embodiment described above, the oscillator 100 comprises input transistors 112, 132 that may be used to send the load current I.sub.0 onto either node 106 or 128 depending on the value of the output signal outputted on the Q output of the flip-flop 102. Therefore these input transistors 112, 132 can reduce the electricity consumption of the oscillator 100 due to the fact that the load current is not permanently applied on the first and second nodes 106, 128. However as a variant, the oscillator 100 does not necessarily comprise these input transistors 112, 132, and in this case the load current I.sub.0 is sent simultaneously and permanently on the nodes 106, 128.

(42) In the oscillator 100 made according to the first embodiment described above, the values of the capacitances C.sub.synchro1 and C.sub.synchro2 (corresponding to the second and fourth load impedances) may be chosen in particular as a function of variations in the load current I.sub.0. If the variations in the load current I.sub.0 are small, for example of the order of 10%, the values C.sub.synchro1 and C.sub.synchro2 of the second and fourth load impedances 114, 134 are advantageously chosen to be low, for example of the order of one tenth of the values C.sub.1 and C.sub.2.

(43) Furthermore, the values of the capacitors C.sub.synchro1 and C.sub.synchro2 may be less than, equal to or even more than the values of capacitors C.sub.1 and C.sub.2.

(44) An injection-locked oscillator 100 according to a first variant of the first embodiment is described below with reference to FIG. 3.

(45) In this first variant shown on FIG. 3, the flip-flop 102 is replaced by a lock 101. In the example embodiment shown on FIG. 3, the lock 101 is an RS lock.

(46) The first node 106 is coupled to the input S of the lock 101, in other words the input that sets the lock 101 to the high state, through the first and second inverters 120, 122 connected to each other in series.

(47) The second node 128 is coupled to the input R of the lock 101, in other words to the input that sets the lock 101 to the low state, through the fourth inverter 140 and another inverter 141 connected to each other in series.

(48) Like the Q output of the flip-flop 102 of the oscillator 100 shown on FIG. 2, in this case the Q output of the lock 101 is connected to the output of the oscillator 100 and is coupled to the gate of the first discharge transistor 104, to the gate of the first input transistor 112 and to the first input of the first NOR logic gate 118.

(49) The inverted output Q of the lock 101 is obtained directly from the lock 101, since the oscillator 100 shown on FIG. 3 does not have the third inverter 124. This inverted output Q of the lock 101 is coupled to the gate of the second discharge transistor 126, to the gate of the second input transistor 132 and to the first input of the second NOR logic gate 138.

(50) Operation of the oscillator 100 according to this first variant of the first embodiment is similar to operation of the oscillator described above with reference to FIG. 2.

(51) An injection-locked oscillator 100 according to a second variant of the first embodiment is described below with reference to FIG. 4.

(52) Compared with the oscillator 100 previously described with reference to FIG. 2, the first and third load impedances 108 do not correspond to capacitors forming capacitances with fixed values, but correspond to capacitive transducers forming capacitances with values that vary as a function of a control signal received by the first and third load impedances 108, 130. For example, this control signal corresponds to a pressure, an electric field, or a force received by the capacitive transducers.

(53) The value of the natural frequency of the oscillator 100 depends on the capacitance values of the first and third load impedances 108, 130. Advantageously, the load current I.sub.0 corresponds to a current with a constant value, in other words the value of which does not depend on a control signal received by the oscillator 100. Thus, the natural frequency of the oscillator 100 varies only as a function of variations in the control signal received by the first and third load impedances 108, 130.

(54) As a variant, the value of the load current I.sub.0 may be a function of a control signal received by the oscillator 100 and different from the value that varies the capacitance values of the first and third load impedances. In this case, the value of the natural frequency of the oscillator 100 depends on the amplitude of each of these two control signals.

(55) According to another embodiment, it is possible that the oscillator 100 is made according to the two variants described above, in other words it comprises the lock 101 and the capacitive transducers forming the first and the third load impedances 108, 130.

(56) An injection-locked oscillator 100 according to a third variant of the first embodiment is described below with reference to FIG. 5A.

(57) Compared with the oscillator 100 described above with reference to FIG. 2, each of the first and fourth inverters 120 and 140 of the oscillator 100 according to this third variant comprises a control input 121, 143 on which a control signal is applied to control the threshold voltage of the inverters 120, 140. An example embodiment of such an inverter is shown in FIG. 5B.

(58) The value of the natural frequency of the oscillator 100 is a function of the values of the threshold voltages of the inverters 120, 140, and therefore in this case depends on the amplitude of the control signal applied on the control inputs 121, 143 of the inverters 120, 140. According to one embodiment, the load current I.sub.0 may correspond to a current with a constant value, in other words the value of which does not depend on a control signal received by the oscillator 100. Thus, the value of the natural frequency of the oscillator 100 depends only on the values of the threshold voltages of the inverters 120, 140, and therefore-on the control signals applied on the control inputs 121, 143 of the inverters 120, 140. However as a variant, the load current I.sub.0 may be a function of another control signal received by the oscillator 100, and in this case the natural frequency of the oscillator 100 depends on the amplitudes of the two received control signals.

(59) According to another embodiment, the other inverters 122 and 124 of the oscillator 100 may also have a control input that may be used to vary their threshold voltage.

(60) This third variant may be combined with either or both of the first and second variants described above. Thus, the oscillator 100 according to this third variant may also comprise a lock 101 as described previously with reference to FIG. 3, and/or may comprise capacitive transducers forming the first and third load impedances 108, 130.

(61) In a second embodiment, the oscillator 100 may correspond to a harmonic oscillator. FIG. 3 diagrammatically shows part of such an oscillator 100.

(62) The oscillator 100 according to this second embodiment comprises a first input 142 on which the control signal I.sub.0 is applied. The oscillator 100 comprises a second input 144 on which the synchronisation signal V.sub.synchro is applied.

(63) In this second embodiment, the oscillator 100 is of the LC type and comprises an inductance, or coil, 146 coupled in parallel to the first load impedance 108 in this case corresponding to a capacitor. The second load impedance 114, also corresponding to a capacitor in this example embodiment, is coupled in series with the first coupling component 116, for example a coupling transistor, the assembly being coupled in parallel to the first load impedance 108. As in the first embodiment, a signal with frequency f.sub.synchro is applied on the gate of the first coupling transistor 116.

(64) The oscillator 100 also comprises other electronic components, for example such as a crossed pair of transistors designed to maintain oscillations by compensating for losses in the LC circuit, that are not described in detail herein.

(65) As in the first embodiment, the oscillator 100 according to this second embodiment has a load impedance with a value that is periodically modified, as a function of the frequency of the synchronisation signal applied on the oscillator 100. As previously described for the first embodiment, the phase shift obtained between the synchronisation signal and the signal outputted on the output 103 of the oscillator 100 is representative of the difference f.sub.0f.sub.synchro.

(66) In the second embodiment described above, the oscillator 100 corresponds to an LC oscillator. The principle described above consisting of modifying the value of the load impedance at the frequency of the synchronisation signal received by the oscillator 100 may be applied to harmonic oscillators different from that described above.

(67) In a third embodiment, the oscillator 100 may correspond to a ring oscillator. FIG. 7 diagrammatically shows such an oscillator 100.

(68) The oscillator 100 according to this third embodiment comprises three inverters 148, 150 and 152 coupled in series and looped, the output of the third inverter 152 being coupled to the input of the first inverter 148. In general, the ring oscillator 100 comprises an odd number of inverters greater than or equal to three.

(69) The output of the first inverter 148 is coupled to a first electrode of the first load impedance 108, the second electrode of the first load impedance 108 being connected to the ground. As in the previous two embodiments, the first load impedance 108 corresponds to a capacitor.

(70) The second load impedance 114 and the first coupling component 116 corresponding to a capacitor and a transistor respectively, form an assembly coupled in parallel to the first load impedance 108.

(71) The output of the second inverter 150 is coupled to a first electrode of the third load impedance 130, the second electrode of the third load impedance 130 being connected to the ground. As in the previous two embodiments, the third load impedance 130 corresponds to a capacitor. The fourth load impedance 134 and the second coupling component 136 corresponding to a capacitor and a transistor respectively, form an assembly coupled in parallel to the third load impedance 130.

(72) The output of the third inverter 152 is coupled to a first electrode of a fifth load impedance 154, the second electrode of the fifth load impedance 154 being connected to the ground. The fifth load impedance 154 corresponds to a capacitor. A sixth load impedance 156 and a third coupling component 158 corresponding to a capacitor and a transistor respectively, form an assembly coupled in parallel to the fifth load impedance 154.

(73) As in the previous embodiments, the gates of the coupling transistors 116, 136 and 158 receive a signal with frequency f synchro thus modulating the value of load impedances coupled to the outputs of inverters 148, 150 and 150 at this frequency. However, the signals applied on the gates of coupling transistors 116, 136, 158 are out-of-phase with each other such that the modulation of the value of each of the load impedances takes place at different moments. This, in the example in FIG. 7, these signals are out-of-phase with each other by 2/3. In general, in such a ring oscillator, the phase shift between the synchronisation signals applied on the gates of the coupling transistors is 2/n, in which n corresponds to the number of inverters in the oscillator 100.

(74) The phase shift obtained between the synchronisation signal and the signal outputted on the output 103 of the oscillator 100 is similar to that previously described for the first embodiment except for a gain factor, in other words it is a function of the number of inverters included in the oscillator 100.

(75) In the configuration shown on FIG. 7, the output of each of the inverters of the oscillator 100 is coupled to a load impedance and to a coupling component configured to periodically couple another load impedance to said load impedance, at the frequency of the synchronisation signal and in parallel or series. As a variant, it is possible that only one of the inverters of the oscillator 100 has its output coupled to a load impedance with a variable value. In this case, and reconsidering the configuration shown on FIG. 7, the oscillator 100 does not have any load impedances 134, 156 nor coupling components 136, 158.

(76) In a relaxation oscillator like that described above with reference to FIG. 2, the phase shift is linear over the entire locking range of the oscillator 100. On the other hand, in other types of oscillator such as for example a harmonic oscillator, this phase shift is not linear over the entire locking range of the oscillator. In this case, it is preferable if the oscillator is configured to function on a part of this locking range in which the phase shift varies linearly.

(77) In the embodiments described above, the second load impedance 114 is coupled in parallel to the first load impedance 108 by the coupling component 116. As a variant, the second load impedance 114 may be coupled in series with the first load impedance 108 by the coupling component 116. In this case, the first and second load impedances 108, 114 may be connected with each other in series, and the coupling component 116, for example consisting of a transistor, may be coupled in parallel to the second load impedance 114. Thus, when the coupling component 116 is in the blocked state, the second load impedance 114 is not short circuited by the coupling component 116 and therefore the global value of the load impedance of the oscillator 100 is modified by the addition of the value of the second load impedance 114. When the coupling component 116 is in the conducting state, the second load impedance 114 is then short circuited by the coupling component 116, and therefore it does not modify the global value of the load impedance of the oscillator 100. This configuration may for example be applicable for the oscillator 100 described above for the second embodiment, by coupling a second inductive component in series with the inductive component 146.

(78) Regardless of its embodiment, the oscillator 100 may be used in an interface circuit 200 for a sensor. FIG. 8 diagrammatically shows such an configuration.

(79) The interface circuit 200 comprises an injection-locked oscillator 100 made according to one of the previously described embodiments. The oscillator 100 receives a data signal (corresponding to the control signal I.sub.0 in the previously described embodiments) on a first input sent from an amplifier 350 that receives an output signal sent by a sensor 300 as input. The interface circuit 200 also comprises a reference oscillator 202 that outputs a periodic synchronisation signal with frequency f.sub.synchro. The synchronisation signal is sent on a second input of the oscillator 100.

(80) The synchronisation signal is also sent on a first input of a measurement device 400 that also receives the output signal outputted by the oscillator 100 on a second input. The measurement device 400 detects the phase shift between the signals sent on its first and second inputs, this phase shift being representative of the data signal sent by the sensor 300. For example, the measurement device 400 may comprise a PLL to supply a frequency that is an integer multiple of the synchronisation frequency and a counter. The count frequency is the frequency of the signal output from the PLL. The count is made between the rising front of the synchronisation signal and the rising front of the signal output from the injection-locked oscillator.

Injection-locked oscillator with variable load impedance

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H03L7/24

ELECTRICITY

Classification Explorer

H03B19/14

ELECTRICITY

Classification Explorer

H03L7/08

ELECTRICITY

Classification Explorer

H03B5/12

ELECTRICITY

Classification Explorer

H03K3/03

ELECTRICITY

Abstract

Claims

Description