Power management circuit for fast average power tracking voltage switching

Abstract

A power management circuit for fast average power tracking (APT) voltage switching is provided. The power management circuit includes a primary voltage circuit configured to generate an APT voltage based on an APT target voltage. However, the primary voltage circuit may be inherently slow in ramping up the APT voltage to the APT target voltage. As such, a secondary voltage circuit is provided in the power management circuit to help drive the APT voltage to a desired level by a defined temporal limit. Once the APT voltage reaches the desired level, the secondary voltage circuit will automatically shut off, while the primary voltage circuit continues operating at a selected duty cycle to maintain the APT voltage at the APT target voltage. By utilizing the secondary voltage circuit to quickly drive up the APT voltage, the power management circuit is capable of supporting dynamic power control under stringent switching delay budget.

Claims

1. A power management circuit comprising: a primary voltage circuit configured to generate an average power tracking (APT) voltage at a voltage output based on a battery voltage; a secondary voltage circuit configured to raise the APT voltage at the voltage output based on a supply voltage higher than the battery voltage; and a control circuit configured to: receive an APT target voltage that indicates an increase of the APT voltage at the voltage output; and control the primary voltage circuit to provide the supply voltage to the secondary voltage circuit to thereby activate the secondary voltage circuit to raise the APT voltage to the APT target voltage by a defined temporal limit, wherein the secondary voltage circuit is further configured to automatically shut off when the APT voltage reaches the APT target.

2. The power management circuit of claim 1 wherein the primary voltage circuit is further configured to generate the supply voltage that is equal to two times the battery voltage.

3. The power management circuit of claim 1 wherein the control circuit is further configured to: assert a first control signal to thereby control the primary voltage circuit to provide the supply voltage to the secondary voltage circuit; de-assert the first control signal after the APT voltage is raised to the APT target voltage at the voltage output; and assert a second control signal to thereby control the primary voltage circuit to generate the APT voltage based on a selected duty cycle.

4. The power management circuit of claim 3 wherein the control circuit is further configured to assert the first control signal and the second control signal concurrently.

5. The power management circuit of claim 3 wherein the control circuit is further configured to assert the second control signal after asserting the first control signal.

6. The power management circuit of claim 3 wherein the secondary voltage circuit is further configured to raise the APT voltage to equal a modified APT target voltage by the defined temporal limit in response to receiving the supply voltage, wherein the modified APT target voltage is equal to the APT target voltage minus a predetermined offset voltage.

7. The power management circuit of claim 6 wherein the secondary voltage circuit comprises: an error amplifier configured to compare the APT voltage at the voltage output against the modified APT target voltage to output a bias voltage; and a low dropout (LDO) transistor comprising: a gate electrode coupled to the error amplifier to receive the bias voltage; a drain electrode coupled to the primary voltage circuit to receive the supply voltage; and a source electrode coupled to the voltage output to raise the APT voltage to equal the modified APT target voltage based on the supply voltage.

8. The power management circuit of claim 7 wherein the secondary voltage circuit further comprises a calculator configured to: receive the APT target voltage and the predetermined offset voltage; and generate and provide the modified APT target voltage to the error amplifier.

9. The power management circuit of claim 7 wherein the error amplifier is further configured to turn off the LDO transistor when the APT voltage is raised to the modified APT target voltage at the voltage output.

10. The power management circuit of claim 9 wherein the error amplifier is further configured to turn off the LDO transistor independent of whether the first control signal is deasserted.

11. The power management circuit of claim 7 wherein the secondary voltage circuit further comprises a pulldown switch coupled between the gate electrode and a ground, and the control circuit is further configured to close the pulldown switch to pull the bias voltage to the ground to thereby cause the APT voltage to be raised to the modified APT target voltage within the defined temporal limit.

12. The power management circuit of claim 7 wherein the primary voltage circuit comprises: a multi-level charge pump configured to generate a low-frequency voltage at multiple levels at a reference node based on the battery voltage and in accordance with the selected duty cycle; and an inductor-capacitor (LC) circuit coupled between the reference node and the voltage output and configured to output an average of the multiple levels of the low-frequency voltage as the APT voltage.

13. The power management circuit of claim 12 wherein the control circuit is further configured to assert the second control signal to cause the multi-level charge pump to generate the low-frequency voltage at one or more of the multiple levels in accordance with the selected duty cycle.

14. The power management circuit of claim 12 wherein the multi-level charge pump comprises: an input node coupled to a battery to receive the battery voltage; an output node coupled to the reference node to output the low-frequency voltage; a first switch coupled between the input node and a first intermediate node; a second switch coupled between the first intermediate node and the output node; a third switch coupled between the input node and a second intermediate node; a fourth switch coupled between the second intermediate node and a ground; a fifth switch coupled between the input node and the output node; a sixth switch coupled between the reference node and the ground; and a fly capacitor coupled between the first intermediate node and the second intermediate node.

15. The power management circuit of claim 14 wherein the drain electrode of the LDO transistor is coupled to the first intermediate node of the multi-level charge pump to receive the supply voltage.

16. The power management circuit of claim 14 wherein the control circuit is further configured to: close the first switch and the fourth switch to charge the fly capacitor to thereby pull the first intermediate node up to the battery voltage; and open the second switch, the third switch, the fifth switch, and the sixth switch to thereby not output the low-frequency voltage at the reference node.

17. The power management circuit of claim 14 wherein the control circuit is further configured to: close the sixth switch, while keeping the second switch, the third switch, and the fifth switch open, to pull the reference node down to the ground to thereby output the low-frequency voltage at zero volt; and close the first switch and the fourth switch to thereby charge the fly capacitor to thereby pull the first intermediate node up to the battery voltage.

18. The power management circuit of claim 14 wherein the control circuit is further configured to: close the fifth switch, while keeping the second switch, the third switch, and the sixth switch open, to output the low-frequency voltage at the battery voltage; and close the first switch and the fourth switch to thereby charge the fly capacitor to thereby pull the first intermediate node up to the battery voltage.

19. The power management circuit of claim 14 wherein the control circuit is further configured to: close the second switch and the third switch to output the low-frequency voltage at two times the battery voltage; and open the first switch, the fourth switch, the fifth switch, and the sixth switch such that the fly capacitor is not charged.

20. The power management circuit of claim 14 wherein the control circuit is further configured to assert the first control signal to cause the third switch and the fifth switch to be closed to thereby provide the supply voltage from the first intermediate node to the drain electrode of the LDO transistor and to output the low-frequency voltage at the battery voltage.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 is a schematic diagram of an exemplary power management circuit configured according to an embodiment of the present disclosure to support fast average power tracking (APT) voltage switching;

(3) FIG. 2A-2D are schematic diagrams providing exemplary illustration of different operating modes of a multi-level charge pump in the power management circuit of FIG. 1;

(4) FIG. 3 is a schematic diagram providing an exemplary illustration of a secondary voltage circuit in the power management circuit of FIG. 1;

(5) FIG. 4 is a schematic diagram providing an exemplary illustration of another operating mode of the multi-level charge pump in FIGS. 2A-2D to activate the secondary voltage circuit in FIG. 3;

(6) FIG. 5 is a graphic diagram providing an exemplary illustration of an operation of the power management circuit of FIG. 1 according to an embodiment of the present disclosure; and

(7) FIG. 6 is a graphic diagram providing an exemplary illustration of an operation of the power management circuit of FIG. 1 according to another embodiment of the present disclosure.

DETAILED DESCRIPTION

(8) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(9) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(10) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(11) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(12) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(13) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(14) Embodiments of the disclosure relate to a power management circuit for fast average power tracking (APT) switching. The power management circuit includes a primary voltage circuit configured to generate an APT voltage based on an APT target voltage. However, the primary voltage circuit may be inherently slow in ramping up the APT voltage to the APT target voltage. As such, a secondary voltage circuit is provided in the power management circuit to help drive the APT voltage to a desired level by a defined temporal limit. Once the APT voltage reaches the desired level, the secondary voltage circuit will automatically shut off, while the primary voltage circuit continues operating at a selected duty cycle to maintain the APT voltage at the APT target voltage. By utilizing the secondary voltage circuit to quickly drive up the APT voltage, the power management circuit is capable of supporting dynamic power control under stringent switching delay budget.

(15) FIG. 1 is a schematic diagram of an exemplary power management circuit 10 configured according to an embodiment of the present disclosure to support fast APT voltage switching. The power management circuit 10 includes a primary voltage circuit 12. The primary voltage circuit 12 is coupled to a voltage output 14 and configured to generate an APT voltage V.sub.CC at the voltage output 14 based on a battery voltage V.sub.BAT. In a non-limiting example, the primary voltage circuit 12 includes a multi-level charge pump 16 and an inductor-capacitor (LC) circuit 18, which is coupled between the multi-level charge pump 16 and the voltage output 14.

(16) As discussed below in FIGS. 2A-2D, the multi-level charge pump 16 is configured to generate a low-frequency voltage V.sub.DC (e.g., a constant voltage) at multiple levels based on a selected duty cycle. For example, the multi-level charge pump 16 can be configured to generate the low-frequency voltage V.sub.DC at zero volt (0 V) and four volts (4 V) based on a 25%-75% duty cycle. As a result, the multi-level charge pump 16 would generate an average of the low-frequency voltage V.sub.DC that equals three volts (3 V).

(17) The LC circuit 18, which includes a power inductor 20 and a bypass capacitor 22, functions as a low-pass filter to output an average of the multiple levels of the low-frequency voltage V.sub.DC as the APT voltage V.sub.CC. Specifically, the power inductor 20 induces a respective low-frequency current IDC (e.g., a constant current) based on each of the multiple levels of the low-frequency voltage V.sub.DC to charge the bypass capacitor 22. As a result, the LC circuit 18 outputs the APT voltage V.sub.CC that equals the average of the multiple levels of the low-frequency voltage V.sub.DC.

(18) In a non-limiting example, the power inductor 20 can have an inductance of 1 μH and the bypass capacitor 22 can have a capacitance of 2.2 μF. In this regard, the LC circuit 18 will have a resonance frequency of approximately 107 KHz. Accordingly, the LC circuit 18 may take 2.5 to 3 microseconds (μs) to change the APT voltage V.sub.CC from one level to another. However, as discussed earlier, to employ the power management circuit 10 to support dynamic power control in, for example 802.11ax, the power management circuit 10 must be able to change the APT voltage V.sub.CC under a stringent switching delay budget (e.g., 0.5 μs). Clearly, the primary voltage circuit 12 alone would not be able to satisfy the stringent switching delay budget.

(19) As such, the power management circuit 10 is further configured to include a secondary voltage circuit 24. As discussed below in FIG. 3, the secondary voltage circuit 24 can help drive the APT voltage V.sub.CC to a desired level by a defined temporal limit (e.g., 0.5 μs). Once the APT voltage V.sub.CC reaches the desired level, the secondary voltage circuit 24 will automatically shut off, while the primary voltage circuit 12 continues operating at a selected duty cycle to maintain the APT voltage V.sub.CC. By utilizing the secondary voltage circuit 24 to quickly drive up the APT voltage V.sub.CC, the power management circuit 10 will be capable of supporting dynamic power control under the stringent switching delay budget.

(20) The secondary voltage circuit 24 may be activated to quickly ramp up the APT voltage V.sub.CC in response to receiving a supply voltage V.sub.SUP that is higher than the battery voltage V.sub.BAT. In a non-limiting example, the supply voltage V.sub.SUP can be substantially equal to two times the battery voltage V.sub.BAT (e.g., V.sub.SUP=2×V.sub.BAT±0.1 V). The secondary voltage circuit 24 may be configured to automatically turn itself off as soon as the APT voltage reaches the desired level. In the meantime, the primary voltage circuit 12 remains active to continue driving and/or maintaining the APT voltage V.sub.CC at the voltage output 14. In this regard, the primary voltage circuit 12 and the secondary voltage circuit 24 collectively cause the power management circuit 10 to increase the APT voltage V.sub.CC by the defined temporal limit.

(21) Notably, the secondary voltage circuit 24 can only serve as a current source as opposed to a current sink. As such, the secondary voltage circuit 24 will only be activated when the APT voltage V.sub.CC is set to increase. The secondary voltage circuit 24 will remain inactive when the APT voltage V.sub.CC is set to decrease. In this regard, the primary voltage circuit 12 will be solely responsible to reduce the APT voltage V.sub.CC by generating the low-frequency voltage V.sub.DC at appropriate levels based on an appropriate duty cycle.

(22) To control the primary voltage circuit 12 and/or the secondary voltage circuit 24 to collectively increase and/or decrease the APT voltage V.sub.CC at the voltage output 14, a control circuit 26 is provided in the power management circuit 10. The control circuit 26, which can be a field-programmable gate array (FPGA), as an example, receives an APT target voltage V.sub.TGT that indicates an increase of the APT voltage V.sub.CC from one level (e.g., 1 V) to another (e.g., 5V), or vice versa. In response to receiving the APT target voltage V.sub.TGT that indicates the increase of the APT voltage V.sub.CC, the control circuit 26 controls the primary voltage circuit 12 to provide the supply voltage V.sub.SUP to the secondary voltage circuit 24 to thereby cause the secondary voltage circuit 24 to raise the APT voltage V.sub.CC to a desired level that is substantially equal to the APT target voltage V.sub.TGT by the defined temporal limit. In a non-limiting example, the control circuit 26 can cause the primary voltage circuit 12 to generate and provide the supply voltage V.sub.SUP to the secondary voltage circuit 24 by asserting a first control signal 28.

(23) Concurrent to or subsequent to asserting the first control signal 28, the control circuit may assert a second control signal 30 to set a selected duty cycle for the primary voltage circuit 12 to thereby cause the primary voltage circuit 12 to generate the low-frequency voltage V.sub.DC independent of whether the secondary voltage circuit 24 is active. In this regard, the primary voltage circuit 12 and the secondary voltage circuit 24 can both be active, at least before the APT voltage V.sub.CC reaches the desired level that is substantially equal to the APT target voltage V.sub.TGT.

(24) The second control signal 30 can cause the multi-level charge pump 16 to operate in a number of different modes, as discussed next with reference to FIGS. 2A-2D. Common elements between FIGS. 1 and 2A-2D are shown therein with common element numbers and will not be re-described herein.

(25) As illustrated in FIGS. 2A-2D, the multi-level charge pump 16 includes an input node 32, an output node 34, a reference node 36, a first intermediate node 38 (denoted as “n1”), and a second intermediate node 40 (denoted as “n2”). Specifically, the input node 32 is coupled to a battery 42 to receive the battery voltage V.sub.BAT, and the output node 34 is coupled to the reference node 36 to output the low-frequency voltage V.sub.DC. The multi-level charge pump 16 includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, and a sixth switch SW6. The first switch SW1 is coupled between the input node 32 and the first intermediate node 38. The second switch SW2 is coupled between the first intermediate node 38 and the output node 34. The third switch SW3 is coupled between the input node 32 and the second intermediate node 40. The fourth switch SW4 is coupled between the second intermediate node 40 and a ground (GND). The fifth switch SW5 is coupled between the input node 32 and the output node 34. The sixth switch SW6 is coupled between the reference node 36 and the GND. The multi-level charge pump 16 also includes a fly capacitor C.sub.FLY that is coupled between the first intermediate node 38 and the second intermediate node 40.

(26) FIG. 2A illustrates a first operation mode of the multi-level charge pump 16 to charge the fly capacitor C.sub.FLY without outputting the low-frequency voltage V.sub.DC at the reference node 36. In the first operation mode, the control circuit 26 asserts the second control signal 30 to close the first switch SW1 and the fourth switch SW4 to charge the fly capacitor C.sub.FLY to pull the first intermediate node 38 up to a node voltage V.sub.n1 that equals the battery voltage V.sub.BAT. The control circuit 26 further opens the second switch SW2, the third switch SW3, the fifth switch SW5, and the sixth switch SW6 to cause the multi-level charge pump 16 not to output the low-frequency voltage V.sub.DC at the reference node 36.

(27) FIG. 2B illustrates a second operation mode of the multi-level charge pump 16 to charge the fly capacitor C.sub.FLY while outputting the low-frequency voltage V.sub.DC at zero volt (0 V). In the second operation mode, the control circuit 26 asserts the second control signal 30 to close the sixth switch SW6, while keeping the second switch SW2, the third switch SW3, and the fifth switch SW5 open, to pull the reference node 36 to the GND to thereby output the low-reference voltage V.sub.DC at 0 V. In the meantime, the control circuit 26 may further close the first switch SW1 and the fourth switch SW4 to charge the fly capacitor C.sub.FLY to pull the first intermediate node 38 up to the node voltage V.sub.n1 that equals the battery voltage V.sub.BAT.

(28) FIG. 2C illustrates a third operation mode of the multi-level charge pump 16 to charge the fly capacitor C.sub.FLY while outputting the low-frequency voltage V.sub.DC at the battery voltage V.sub.BAT. In the third operation mode, the control circuit 26 asserts the second control signal 30 to close the fifth switch SW5, while keeping the second switch SW2, the third switch SW3, and the sixth switch SW6 open, to couple the output node 34 directly to the battery 42 to thereby output the low-reference voltage V.sub.DC at the battery voltage V.sub.BAT. In the meantime, the control circuit 26 may further close the first switch SW1 and the fourth switch SW4 to charge the fly capacitor C.sub.FLY to pull the first intermediate node 38 up to the node voltage V.sub.n1 that equals the battery voltage V.sub.BAT.

(29) FIG. 2D illustrates a fourth operation mode of the multi-level charge pump 16 to output the low-frequency voltage V.sub.DC at two times the battery voltage V.sub.BAT without charging the fly capacitor C.sub.FLY. In the fourth operation mode, the control circuit 26 asserts the second control signal 30 to close the second switch SW2 and the third switch SW3, while keeping the first switch SW1, the fourth switch SW4, the fifth switch SW5, and the sixth switch SW6 open, to thereby output the low-reference voltage V.sub.DC at two times the battery voltage V.sub.BAT. Notably, the fly capacitor C.sub.FLY will not be charged in the fourth operation mode. As a result, the node voltage V.sub.n1 can decay over time.

(30) With reference back to FIG. 1, the control circuit 26 can use the second control signal 30 to toggle the multi-level charge pump 16 between the first operation mode, the second operation mode, the third operation mode, and/or the fourth operation mode based on a selected duty cycle to generate the low-frequency voltage V.sub.DC at multiple levels to thereby enable the LC circuit 18 to output the average of the multiple levels of the low-frequency voltage V.sub.DC as the APT voltage V.sub.CC. Assuming that the battery voltage V.sub.BAT is 4 V, the control circuit 26 may toggle the multi-level charge pump 16 between the third operation mode and the fourth operation mode based on a 25%-75% duty cycle to thereby cause the LC circuit 18 to output the APT voltage V.sub.CC at 7 V (4V*25%+8V*75%). Thus, by toggling the multi-level charge pump 16 between different operation modes in accordance with different duty cycles, it is possible to cause the LC circuit 18 to output the APT voltage V.sub.CC at different levels.

(31) As discussed earlier, the secondary voltage circuit 24 is provided in the power management circuit 10 to swiftly drive up the APT voltage V.sub.CC within the defined temporal limit. In this regard, FIG. 3 is a schematic diagram providing an exemplary illustration of the secondary voltage circuit 24 in the power management circuit 10 of FIG. 1. Common elements between FIGS. 1 and 3 are shown therein with common element numbers and will not be re-described herein.

(32) In a non-limiting example, the secondary voltage circuit 24 includes an error amplifier 44 and a low dropout (LDO) transistor 46, which is a p-type field-effect transistor (pFET) in this example. The LDO transistor 46 includes a gate electrode 48, a drain electrode 50, and a source electrode 52. The gate electrode 48 is coupled to an output 54 of the error amplifier 44 to receive a bias voltage V.sub.BIAS. The drain electrode 50 is coupled to the first intermediate node 38 in the multi-level charge pump 16 in FIGS. 2A-2D to receive the supply voltage V.sub.SUP. The source electrode 52 is coupled to the voltage output 14 to raise the APT voltage V.sub.CC based on the supply voltage V.sub.SUP. Notably, when the LDO transistor 46 is turned on, the supply voltage V.sub.SUP can drive an LDO current Imo, which can be up to 13 Amps, toward the voltage output 14 to thereby quickly raise the APT voltage V.sub.CC at the voltage output 14.

(33) Notably, when the secondary voltage circuit 24 is activated to help quickly raise the APT voltage V.sub.CC toward the APT target voltage V.sub.TGT, the primary voltage circuit 12 is concurrently driving the APT voltage V.sub.CC toward the APT target voltage V.sub.TGT. To prevent the primary voltage circuit 12 and the secondary voltage circuit 24 from competing with each other, the secondary voltage circuit 24 may be configured to raise the APT voltage V.sub.CC to a modified APT target voltage V.sub.TGTM that is lower than but substantially close to the APT target voltage V.sub.TGT (V.sub.TGTM<V.sub.TGT).

(34) In this regard, the secondary voltage circuit 24 may include a calculator 56 configured to generate the modified APT target voltage V.sub.TGTM. The modified APT target voltage V.sub.TGTM may be generated by subtracting a predetermined offset voltage V.sub.OFF (e.g., 0.2 V) from the APT target voltage V.sub.TGT (V.sub.TGTM=V.sub.TGT−V.sub.OFF). The error amplifier 44 may be configured to compare the APT voltage V.sub.CC against the modified APT target voltage V.sub.TGTM to thereby generate the bias voltage V.sub.BIAS at the output 54 to drive the LDO transistor 46. As such, the LDO transistor 46 and, thus, the secondary voltage circuit 24 will be automatically turned off when the APT voltage V.sub.CC becomes equal to the modified APT target voltage V.sub.TGTM. In the meantime, the primary voltage circuit 12 will remain active to continue driving the APT voltage V.sub.CC toward the APT target voltage V.sub.TGT.

(35) As previously mentioned, the primary voltage circuit 12 is configured to generate the supply voltage V.sub.SUP that can be equal to two times the battery voltage V.sub.BAT. As such, the multi-level charge pump 16 is further configured to operate in a fifth operation mode, which will be further discussed below with reference to FIG. 4. In this regard, FIG. 4 is a schematic diagram providing an exemplary illustration of a fifth operating mode of the multi-level charge pump 16 in FIGS. 2A-2D to activate the secondary voltage circuit 24 in FIG. 3. Common elements between FIGS. 2A-2D and 4 are shown therein with common element numbers and will not be re-described herein.

(36) Prior to operating in the fifth operation mode, the multi-level charge pump 16 may need to operate in the first operation mode (as shown in FIG. 2A), the second operation mode (as shown in FIG. 2B), or the third operation mode (as shown in FIG. 2C) such that the fly capacitor C.sub.FLY can be charged to thereby pull the first intermediate node 38 (a.k.a. “n1”) up to the node voltage V.sub.n1 that equals the battery voltage V.sub.BAT. Subsequently, in the fifth operation mode, the control circuit 26 may assert the first control signal 28 to close the third switch SW3 and the fifth switch SW5, while keeping the first switch SW1, the second switch SW2, the fourth switch SW4, and the sixth switch SW6 open. By closing the third switch SW3, the node voltage V.sub.n1 is pulled up to two times the battery voltage V.sub.BAT. By closing the fifth switch SW5, the multi-level charge pump 16 outputs the low-frequency voltage V.sub.DC at the battery voltage V.sub.BAT.

(37) As discussed earlier in FIG. 3, the drain electrode 50 of the LDO transistor 46 is coupled to the first intermediate node 38. As such, since the node voltage V.sub.n1 at the first intermediate node 38 has been pulled up to two times the battery voltage V.sub.BAT, the LDO transistor 46 will receive the supply voltage V.sub.SUP that equals two times the battery voltage V.sub.BAT, thus allowing the secondary voltage circuit 24 to raise the APT voltage V.sub.CC to the modified APT target voltage V.sub.TGTM by the defined temporal limit (e.g., 0.5 μs).

(38) Given that the secondary voltage circuit 24 is able to quickly raise the APT voltage V.sub.CC by the defined temporal limit, it may not be necessary for the primary voltage circuit 12 to stay in the fifth operation mode for very long. For example, the control circuit 26 can de-assert the first control signal 28 after a predetermined delay (e.g., 2 μs) to bring the primary voltage circuit 12 out of the fifth operation mode, thus allowing the fly capacitor C.sub.FLY to be recharged. Concurrently or subsequently, the control circuit may assert the second control signal 30 to toggle between closing the second switch SW2 and opening the fifth switch SW5 to output the low-reference voltage V.sub.DC at two times the battery voltage V.sub.BAT and closing the fifth switch SW5 and opening the second switch SW2 to output the low-frequency voltage V.sub.DC at the battery voltage V.sub.BAT based on a selected duty cycle. By doing so, the primary voltage circuit 12 can continue driving the APT voltage V.sub.CC toward the APT target voltage V.sub.TGT after the secondary voltage circuit 24 turns itself off.

(39) Operation of the power management circuit 10 for supporting fast APT voltage switching can be further illustrated via a graphic diagram. In this regard, FIG. 5 is a graphic diagram providing an exemplary illustration of an operation of the power management circuit 10 of FIG. 1 according to an embodiment of the present disclosure. Common elements between FIGS. 1, 2A-2D, and 5 are shown therein with common element numbers and will not be re-described herein.

(40) Prior to time T.sub.0, the multi-level charge pump 16 may operate in any of the first operation mode, the second operation mode, and the third operation mode to charge the fly capacitor C.sub.FLY to thereby pull the node voltage V.sub.n1 at the first intermediate node 38 to the battery voltage V.sub.BAT, which is 4 V in this example. The power management circuit 10 outputs the APT voltage V.sub.CC at 1 V in this example prior to the time T.sub.0.

(41) At time T.sub.0, the control circuit 26 receives the APT target voltage V.sub.TGT that indicates an increase of the APT voltage V.sub.CC from a present value of 1 V to a future value of 5 V. Immediately or subsequently, the control circuit 26 asserts the first control signal 28 to cause the multi-level charge pump 16 to operate in the fifth operation mode, as described in FIG. 4, to provide the node voltage V.sub.n1 as the supply voltage V.sub.SUP to the secondary voltage circuit 24 and to output the low-frequency voltage V.sub.DC at the battery voltage V.sub.BAT.

(42) In response to receiving the supply voltage V.sub.SUP, the LDO transistor 46 in the secondary voltage circuit 24 starts driving up the LDO current I.sub.LDO to thereby quickly raise the APT voltage V.sub.CC toward the modified APT target voltage V.sub.TGTM. By time T.sub.1, the APT voltage V.sub.CC is raised to the modified APT target voltage V.sub.TGTM and the LDO transistor 46 starts to shut itself off. In the meantime, the primary voltage circuit 12 continues to generate the low-frequency current IDC that continues to drive the APT voltage V.sub.CC toward the APT target voltage V.sub.TGT. At time T.sub.2, the secondary voltage circuit 24 becomes inactive as the LDO current I.sub.LDO disappears. The control circuit 26 may de-assert the first control signal 28 at time T.sub.3 such that the fly capacitor C.sub.FLY can be recharged. Note that the secondary voltage circuit 24 shuts itself off completely before the control circuit 26 de-asserts the first control signal 28. In this regard, it can be said that the secondary voltage circuit 24 automatically turns off independent of the first control signal 28.

(43) As shown in FIG. 5, the secondary voltage circuit 24 can raise the APT voltage V.sub.CC from 1 V to the modified APT target voltage V.sub.TGTM by time T.sub.1. However, it is possible to configure the secondary voltage circuit 24 based on another embodiment of the present disclosure to raise the APT voltage V.sub.CC from 1 V to the modified APT target voltage V.sub.TGTM even before time T.sub.1.

(44) With reference back to FIG. 3, the secondary voltage circuit 24 may be configured to further include a pulldown switch SW, which may be controlled by the control circuit 26 via a third control signal 58. The pulldown switch SW is coupled between the gate electrode 48 and the GND. The control circuit 26 may close the pulldown switch SW to pull the bias voltage V.sub.BIAS to the GND to force the LDO transistor 46 to operate nonlinearly to thereby cause the APT voltage V.sub.CC to be raised to the modified APT target voltage V.sub.TGTM within the defined temporal limit. FIG. 6 is a graphic diagram providing an exemplary illustration of an operation of the power management circuit of FIG. 1 according to this embodiment of the present disclosure. Common elements between FIGS. 5 and 6 are shown therein with common element numbers and will not be re-described herein.

(45) As shown in FIG. 6, the control circuit asserts the third control signal 58 at time T.sub.0 to close the pulldown switch SW in the secondary voltage circuit 24. As a result, the LDO transistor 46 may drive the LDO current I.sub.LDO up faster than without closing the pulldown switch SW. As a result, the secondary voltage circuit 24 can raise the APT voltage V.sub.CC to the modified APT target voltage V.sub.TGTM at time T.sub.1, which is earlier than time T.sub.1 in FIG. 5.

(46) Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.