Distribution Mixer

Abstract

A distributed mixer is configured of an artificial transmission line of which an input end is connected to an LO terminal and a terminal end is connected to an IF terminal, an artificial transmission line of which an input end is connected to an RF terminal, FETs that perform frequency synthesis of LO signals and RF signals and that are disposed following the artificial transmission lines and of which gates are connected to the artificial transmission line and sources are grounded, a bias circuit that applies gate bias voltage to a terminal end of the artificial transmission line, a terminating resistor that connects the terminal end of the artificial transmission line and a ground, and a plurality of transmission lines provided between the artificial transmission line and a drain of each FET.

Claims

1.-5. (canceled)

6. A distributed mixer, comprising: a first transmission line having an input end connected to a local oscillator (LO) terminal for LO signal input, wherein a terminal end of the first transmission line is connected to an intermediate frequency (IF) terminal for IF signal output; a second transmission line having an input end connected to a radio frequency (RF) terminal for RF signal input; a plurality of transistors between the first transmission line and the second transmission line, wherein the plurality of transistors is arrayed equidistantly in a direction of signal flow of the first transmission line and the second transmission line, wherein gates of the plurality of transistors are connected to the second transmission line, wherein drains of the plurality of transistors are connected to the first transmission line, and wherein sources of the plurality of transistors are grounded; a bias circuit that applies a bias voltage to a terminal end of the second transmission line; and a terminating resistor connecting the terminal end of the second transmission line to a ground, wherein the bias circuit applies the bias voltage so that a direct current voltage between a respective gate and a respective source of each of the plurality of transistors is a respective threshold voltage of a respective transistor of the plurality of transistors, wherein the direct current voltage between a respective drain and the respective source of each of the plurality of transistors is equal, and wherein the IF signal obtained by performing frequency conversion of the RF signal is output from the terminal end of the first transmission line.

7. The distributed mixer according to claim 6, further comprising a plurality of third transmission lines between the first transmission line and the drains of the plurality of transistors.

8. The distributed mixer according to claim 6, wherein: the first transmission line has a differential configuration and comprises: a fourth transmission line, wherein an input end of the fourth transmission line is connected to a positive phase side of the LO terminal, and wherein a terminal end of the fourth transmission line is connected to a positive phase side of the IF terminal; and a fifth transmission line, wherein an input end of the fifth transmission line is connected to a negative phase side of the LO terminal, and wherein a terminal end of the fifth transmission line is connected to a negative phase side of the IF terminal; and the second transmission line has a differential configuration and comprises: a sixth transmission line, wherein an input end of the sixth transmission line is connected to a positive phase side of the RF terminal; and a seventh transmission line, wherein an input end of the seventh transmission line is connected to a negative phase side of the RF terminal.

9. The distributed mixer according to claim 8, wherein the plurality of transistors have a differential configuration, and wherein the plurality of transistors comprise: first transistors, wherein gates of the first transistors are connected to the sixth transmission line, wherein drains of the first transistors are connected to the fourth transmission line, and wherein sources of the first transistors are grounded; and second transistors, wherein gates of the second transistors are connected to the seventh transmission line, drains of the second transistors are connected to the fifth transmission line, and sources of the second transistors are grounded.

10. The distributed mixer according to claim 9, wherein the terminating resistor comprises: a first terminating resistor connected between a terminal end of the sixth transmission line and the ground; and a second terminating resistor connected between a terminal end of the seventh transmission line and the ground.

11. The distributed mixer according to claim 8, wherein the bias circuit applies a bias voltage to a terminal end of the sixth transmission line and a terminal end of the seventh transmission line.

12. A distributed mixer, comprising: a first transmission line, wherein an input end of the first transmission line is connected to a local oscillator (LO) terminal for LO signal input, and wherein a terminal end of the first transmission line is connected to an radio frequency (RF) terminal for RF signal output; a second transmission line, wherein an input end of the second transmission line is connected to an intermediate frequency (IF) terminal for IF signal input; a plurality of transistors disposed between the first transmission line and the second transmission line, wherein the plurality of transistors is arrayed equidistantly in a direction of signal flow of the first transmission line and the second transmission line, wherein gates of the plurality of transistors are connected to the second transmission line, wherein drains of the plurality of transistors are connected to the first transmission line, and wherein sources of the plurality of transistors are grounded; a bias circuit that applies a bias voltage to a terminal end of the second transmission line; and a terminating resistor that connects the terminal end of the second transmission line to a ground, wherein the bias circuit applies the bias voltage so that a direct current voltage between a respective gate and a respective source of each of the plurality of transistors is a respective threshold voltage of a respective transistor of the plurality of transistors, wherein the direct current voltage between a respective drain and the respective source of each of the plurality of transistors is equal, and wherein the RF signal obtained by performing frequency conversion of the IF signal is output from the terminal end of the first transmission line.

13. The distributed mixer according to claim 12, further comprising a plurality of third transmission lines between the first transmission line and the drains of the plurality of transistors.

14. The distributed mixer according to claim 12, wherein: the first transmission line has a differential configuration and comprises: a fourth transmission line, wherein an input end of the fourth transmission line is connected to a positive phase side of the LO terminal, and wherein a terminal end of the fourth transmission line is connected to a positive phase side of the RF terminal; and a fifth transmission line, wherein an input end of the fifth transmission line is connected to a negative phase side of the LO terminal, and wherein a terminal end of the fifth transmission line is connected to a negative phase side of the RF terminal; and the second transmission line has a differential configuration and comprises: a sixth transmission line, wherein an input end of the sixth transmission line is connected to a positive phase side of the IF terminal; and a seventh transmission line, wherein an input end of the seventh transmission line is connected to a negative phase side of the IF terminal.

15. The distributed mixer according to claim 14, wherein the plurality of transistors have a differential configuration, and wherein the plurality of transistors comprise: first transistors, wherein gates of the first transistors are connected to the sixth transmission line, wherein drains of the first transistors are connected to the fourth transmission line, and wherein sources of the first transistors are grounded; and second transistors, wherein gates of the second transistors are connected to the seventh transmission line, drains of the second transistors are connected to the fifth transmission line, and sources of the second transistors are grounded.

16. The distributed mixer according to claim 15, wherein the terminating resistor comprises: a first terminating resistor connected between a terminal end of the sixth transmission line and the ground; and a second terminating resistor connected between a terminal end of the seventh transmission line and the ground.

17. The distributed mixer according to claim 14, wherein the bias circuit applies a bias voltage to a terminal end of the sixth transmission line and a terminal end of the seventh transmission line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG. 1 is a diagram for describing the principle of a drain injection mixer.

[0026] FIG. 2 is an equivalency circuit diagram of the drain injection mixer.

[0027] FIG. 3 is a conceptional diagram for describing frequency conversion operations of a drain injection mixer.

[0028] FIG. 4 is a diagram illustrating drain current-drain voltage characteristics of an FET model used for operation analysis of a drain injection mixer.

[0029] FIG. 5 is a diagram illustrating drain voltage dependency of transconductance obtained from the characteristics of the FET model illustrated in FIG. 4.

[0030] FIG. 6 is a diagram illustrating drain voltage dependency of drain conductance obtained from the characteristics of the FET model illustrated in FIG. 4.

[0031] FIG. 7 is a diagram illustrating gate voltage dependency of P(Vg, Vd).

[0032] FIG. 8 is a diagram illustrating gate voltage dependency of P(Vg, Vd)/Vd.

[0033] FIG. 9 is a circuit diagram illustrating a configuration of a drain injection distributed mixer according to a first embodiment of the present invention.

[0034] FIG. 10 is a circuit diagram illustrating a configuration of a conventional drain injection distributed mixer used for comparison with the first embodiment of the present invention.

[0035] FIG. 11 is a diagram illustrating calculation results of conversion gain for the drain injection distributed mixer according to the first embodiment of the present invention and the conventional drain injection distributed mixer.

[0036] FIG. 12 is a circuit diagram illustrating a configuration of a drain injection distributed mixer according to a second embodiment of the present invention.

[0037] FIG. 13 is a circuit diagram illustrating a configuration of a conventional drain injection distributed mixer.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Principle of Embodiments of the Invention

[0038] FIG. 1 is a diagram for describing the principle of a single-ended drain injection mixer that uses one FET. The drain injection mixer is configured of a FET Q1, a bias circuit 10 that applies drain bias voltage to the drain (D) of the FET Q1, a bias circuit 11 that applies gate bias voltage to the gate (G) of the FET Q1, a matching circuit 12 that matches the impedance of the LO terminal 5 and IF terminal 7 and the impedance of the drain of the FET Q1 as viewed from the LO terminal 5 and IF terminal 7, and a matching circuit 13 that matches the impedance of the RF terminal 6 and the impedance of the gate of the FET Q1 a viewed from the RF terminal 6.

[0039] The drain injection mixer performs mixing of LO signals and RF signals or mixing of LO signals and IF signals, utilizing change in transconductance g.sub.m by modulating voltage applied to the drain of the FET Q1. Besides the knee voltage that had been thought to be the optimal bias condition for conventional drain injection mixers, a separate operation bias point where high conversion gain is obtained exists, which will be described below by way of a simple analysis model of a drain injection mixer.

[0040] FIG. 2 is an equivalency circuit diagram of the drain injection mixer illustrated in FIG. 1. The operating principle of embodiments of the present invention will be described by way of this FIG. 2. There are transconductance g.sub.m and drain conductance g.sub.d of the FET Q1 as nonlinear parameters that bring about mixing operations in a drain injection mixer. These nonlinear elements are represented as current source g.sub.m (Vd, Vg)v.sub.gs and drain resistance R.sub.d(Vd, Vg)=1/g.sub.d in FIG. 2. Vd is the drain voltage of the FET Q1, and Vg is the gate voltage. Also, v.sub.RF in FIG. 2 is voltage of RF signals, R.sub.i is input impedance, and C.sub.gs is gate-source capacitance of the FET Q1. Change in the two values of transconductance g.sub.m and drain conductance g.sub.d allows IF signals generated by RF signals and LO signals being mixed to be extracted from a load Z.sub.L in FIG. 2.

[0041] At this time, IF signals appear as an envelope 30 of signals generated by FR signals and LO signals being mixed, and the IF signal component alone is normally extracted using a low-pass filter, as illustrated in FIG. 3. The magnitude of conversion gain of the drain injection mixer is expressed by amount of amplitude change i.sub.IF of the envelope 30 in FIG. 3. That is to say, in order to increase the conversion gain of drain injection mixer, a design can be made so that the amount of change i.sub.IF illustrated in Formula (1) is larger.

i.sub.IF=|i.sub.IFMAXi.sub.IFMIN|Formula 1

[0042] i.sub.IFMAX is the maximum value of amplitude of current i.sub.IF flowing through the load Z.sub.L, and i.sub.IFMIN is the minimum value of amplitude. In FIG. 2, current i.sub.IF flowing through the load Z.sub.L is expressed by the following Formula.

[00001] $\begin{matrix} .Math. Formula .Math. .Math. 2 \\ i_{IF} = g_{m} (Vd, Vg) .Math. v_{gs} .Math. \frac{R_{d} (Vd, Vg)}{R_{L} + R_{d} (Vd, Vg)} = g_{m} (Vd, Vg) .Math. v_{gs} .Math. \frac{1}{1 + g_{d} (Vd, Vg) .Math. R_{L}} & (2) \end{matrix}$

[0043] From Formula (2), Formula (3) holds.

[00002] $\begin{matrix} Formula .Math. .Math. 3 \\ i_{IF} \frac{g_{m} (Vd, Vg)}{1 + g_{d} (Vd, Vg) .Math. R_{L}} & (3) \end{matrix}$

[0044] Accordingly, the value of i.sub.IF that decides the conversion gain of the drain injection mixer shown in Formula (1) is proportionate to the amount of change of the absolute value of the right side of Formula (3) when the drain voltage Vd changes. The absolute value of the right side of Formula (3) is expressed as P (Vg, Vd) as in Formula (a).

[00003] $\begin{matrix} Formula .Math. .Math. 4 \\ P (Vg, Vd) = .Math. \frac{g_{m} (Vd, Vg)}{1 + g_{d} (Vd, Vg) .Math. R_{L}} .Math. & (4) \end{matrix}$

[0045] The values of transconductance g.sub.m and drain conductance g.sub.d can be obtained from current-voltage measurement of the FET Q1. When designing the drain injection mixer, the design can be made regarding a point where the amount of change of P (Vg, Vd) in Formula (4) as to the drain voltage Vd is great. A large-signal model of a MESFET with a gate width of 10 m will be used for description of the FET Q1 here. FIG. 4 illustrates drain current iddrain voltage Vd characteristics of this FET model.

[0046] The transconductance g.sub.m and drain conductance g.sub.d of the FET model can be defined as in Formula (5) and Formula (6).

[00004] $\begin{matrix} Formula .Math. .Math. 5 \\ g_{m} = \frac{i_{d}}{v_{g}} & (5) \\ Formula .Math. .Math. 6 \\ g_{d} = \frac{i_{d}}{v_{d}} & (6) \end{matrix}$

[0047] From the characteristics in FIG. 4, calculating the drain voltage Vd dependency of the transconductance g.sub.m with gate voltage Vg as a parameter to plot on a graph yields that in FIG. 5. Also, calculating the drain voltage Vd dependency of the drain conductance g.sub.d with gate voltage Vg as a parameter to plot on a graph yields that in FIG. 6. Calculating the gate voltage Vg dependency of the P(Vg, Vd) in Formula (4) with drain voltage Vd as a parameter to plot on a graph, using the characteristics shown in FIG. 5 and FIG. 6 here, yields that in FIG. 7.

[0048] The gate voltage Vg and drain voltage Vd that optimizes conversion gain of the drain injection mixer can be derived from FIG. 7. It can be understood from FIG. 7 that the greater the gate voltage Vg is, the greater the amount of change of P(Vg, Vd) becomes. Accordingly, it is thought that the greater the gate voltage Vg is, the greater the conversion gain of the drain injection mixer is.

[0049] The drain voltage Vd is decided as follows. For example, conditions for the drain voltage Vd to increase the conversion gain of the drain injection mixer in a case where the gate voltage Vg is 0.2 V will be considered. The drain voltage Vd where the value of P(Vg, Vd) is minimal is Vd=0 V. Where the value of P(Vg, Vd) is maximal is Vd=1.0 V, however, the value of P(Vg, Vd) at that time is hardly unchanged from the cases of Vd=0.6 V and 0.8 V.

[0050] Accordingly, it is preferable to increase/reduce the drain voltage Vd in the range of 0 V to 0.6 V, in order to conserve LO signal power as well. Accordingly, the greatest conversion gain with the lowest LO signal power can be obtained by setting the drain voltage Vd to 0.3 V, which is the medium value between 0 V and 0.6 V. The (Vg, Vd)=(0.2 V, 0.3 V) derived from the above speculation is equivalent to the knee voltage of the FET Q1, which can be understood from the drain current iddrain voltage Vd characteristics in FIG. 4. Accordingly, it can be understood that near the knee voltage, which is the bias point of conventional drain injection mixers, is optimal to obtain high conversion gain, from the index P(Vg, Vd).

[0051] Now, a case where LO signal power is even lower will be considered. Considering a case where only up to 0.2 V can be obtained as swing amplitude of the drain voltage Vd, for example, the conditions using the above-described drain voltage Vd as the bias point does not yield sufficiently large change of amount of P(Vg, Vd) as to the drain voltage Vd, and a great conversion gain cannot be obtained.

[0052] In order to obtain bias conditions where a great conversion gain of the drain injection mixer can be obtained with LO signal power as small as possible, the rate of change of P(Vg, Vd) as to the drain voltage Vd can be calculated as P(Vg, Vd)/Vd, and a bias point where this value is the greatest can be obtained. FIG. 8 illustrates gate voltage Vg dependency of P(Vg, Vd)/Vd with the drain voltage Vd as a parameter.

[0053] It can be understood from FIG. 8 that P(Vg, Vd)/Vd is maximal around drain voltage Vd=0 V and gate voltage Vg=0.35 V. That is to say, high conversion gain of the drain injection mixer with the lowest LO signal power can be obtained at drain voltage Vd=0 V and gate voltage Vg=0.35 V.

[0054] Qualitatively, the reason why P(Vg, Vd)/Vd is maximal at drain voltage Vd=0 V and gate voltage Vg=0.35 V can be explained as follows. Gate voltage Vg=0.35 V is equivalent to the threshold voltage of the Schottky barrier junction of the gate of the FET Q1.

[0055] In a case of using the FET Q1 at drain bias voltage of 0 V, when the drain voltage Vd becomes negative voltage in accordance with LO signals, the gate voltage Vgd as viewed from the drain of the FET Q1 is greater than the threshold voltage of the Schottky barrier junction making up the gate of the FET Q1, and a large current flows from the gate to the drain.

[0056] Conversely, when the drain voltage Vd becomes positive voltage in accordance with LO signals under conditions of drain bias voltage of 0 V, Vgd becomes smaller than the threshold voltage of the Schottky barrier junction making up the gate of the FET Q1, so the current flowing from the gate to the drain rapidly drops. This indicates that the drain conductance g.sub.d rapidly changes near the origin. Also, when the drain voltage Vd becomes positive voltage, gain as to RF signals input to the gate, due to transconductance g.sub.m, can also be used, as can be understood from FIG. 5.

[0057] Normally, it is assumed that mixers are driven by sufficiently great LO signal power so that the greatest conversion gain can be obtained. Accordingly, in a case where the frequency of LO signals is low and an LO signal source for great output power can be easily obtained, it is thought that the conventional use of the drain injection mixer near the knee voltage is good.

[0058] However, in a case where the LO signal frequency is extremely high, such as exceeding 100 GHz for example, the signal source that can supply sufficient LO signal power is small, so a mixer that can be driven by LO signal power that is as low as possible is desired. Embodiments of the present invention can obtain high conversion gain at low LO signal power in a case where the signal frequency is high, and accordingly is effective in, for example, a fundamental wave mixer that performs downconversion of signals where the RF signal frequency exceeds 100 GHz, or the like. Also, there is no need to supply bias voltage to the drain of the FET Q1 in embodiments of the present invention, so an advantage can be obtained in that the electric power consumption is markedly small as compared with conventional drain injection mixers.

[0059] Description has been made that, according to the above principle, even in a case where the direct current voltage of the drain of the FET Q1 is zero (the direct current voltages of the drain and source are equal), a great conversion gain can be obtained by setting the direct current voltage between the gate and source to the threshold voltage of the FET Q1. Applying this principle to a drain injection distributed mixer does away with the need for the bias circuit at the drain side, and accordingly the above-described difficulty regarding the drain-side bias circuit can be avoided, and further, a drain injection distributed mixer with lower electric power consumption than conventional arrangements can be realized.

[0060] Next, as an embodiment, a drain injection distributed mixer according to embodiments of the present invention is actually designed, calculated results are shown, and description will be made that embodiments of the present invention is effective.

FIRST EMBODIMENT

[0061] An example of application to a single-ended drain injection distributed mixer will be described as a first embodiment of the present invention. FIG. 9 is a circuit diagram illustrating the configuration of the drain injection distributed mixer according to the present embodiment. The drain injection distributed mixer according to the present embodiment is configured of the artificial transmission line 1 of which the input end is connected to the LO terminal 5 and the terminal end is connected to the IF terminal 7, the artificial transmission line 2 of which the input end is connected to the RF terminal 6, a plurality of FETs Q1 that are unit mixers that perform frequency synthesis of LO signals and RF signals, and that are disposed along the artificial transmission lines 1 and 2 and of which the gates are connected to the artificial transmission line 2 and the sources are grounded, a bias circuit 4a that applies gate bias voltage to the terminal end of the artificial transmission line 2, a terminating resistor R1 of 50 that connects the terminal end of the artificial transmission line 2 and the ground, and a plurality of transmission lines CPW3 (third transmission lines) provided between the artificial transmission line 1 and the drains of the FETs Q1.

[0062] In a case of applying embodiments of the present invention to a drain injection distributed mixer, the bias circuit at the drain side is unnecessary to begin with, so the above problem can be avoided.

[0063] In the present embodiment, identical InP-HEMTs with a gate width of 10 m were used for all of the plurality of FETs Q1. The artificial transmission line 1 is configured of a plurality of transmission lines CPW1 (first transmission lines) that are serially connected. A coplanar line having characteristic impedance of 60 and 70 m in length was used for each transmission line CPW1. In the same way, the artificial transmission line 2 is configured of a plurality of transmission lines CPW2 (second transmission lines) that are serially connected. A coplanar line having characteristic impedance of 65 and 70 m in length was used for each transmission line CPW2. That is to say, the plurality of FETs Q1 are disposed equidistantly between the artificial transmission lines 1 and 2, following the direction of signals flowing over these artificial transmission lines 1 and 2 (the direction from left to right in FIG. 9).

[0064] The characteristic impedances and length of these transmission lines are values calculated so that the cutoff frequency of the artificial transmission lines 1 and 2 is a high value (a value where LO signals and RF signals can be propagated over the artificial transmission lines 1 and 2) when the drain-source voltage of the FETs Q1 is 0 V and the gate-source voltage is 0.35 V, which is the threshold voltage of the FETs Q1.

[0065] Also, a choke coil L1 having inductance of 1 H was used for the bias circuit 4a, to apply gate bias voltage to the terminal end of the artificial transmission line 2.

[0066] In a case of using the drain injection distributed mixer as a downconversion mixer as in the present embodiment, traveling waves of the RF signals and traveling waves of the LO signals are mixed at the FETs Q1 (unit mixers), and post-frequency-conversion IF signals are output from the IF terminal 7.

[0067] Calculation was also performed regarding a conventional drain injection distributed mixer where bias voltage is applied to the drain of the FETs Q1, for comparison with the present embodiment. The configuration of this drain injection distributed mixer is illustrated in FIG. 10. For a bias circuit 3a that applies drain bias voltage, a choke coil L2 having inductance of 1 H was used, and the drain voltage Vd of the FETs Q1 was set to 0.2 V.

[0068] The calculation results of conversion gain CG of the drain injection distributed mixer according to the present embodiment illustrated in FIG. 9, and the conventional drain injection distributed mixer illustrated in FIG. 10, are illustrated in FIG. 11. CG0 in FIG. 11 shows the conversion gain of the drain injection distributed mixer according to the present embodiment, and CG1 shows the conversion gain of the conventional drain injection distributed mixer. The horizontal axis is the gate voltage Vg here, and drain voltage Vd is a parameter. The frequency of RF signals was set to 125 GHz, the frequency of LO signals to 119 GHz, and the frequency of IF signals to 6 GHz. Also, the power of RF signal input was set to 30 dBm, and the power of LO signal input to 4 dBm.

[0069] It can be understood from FIG. 11 that by setting the drain voltage Vd of the FETs Q1 to 0 V and the gate voltage Vg to 0.35 V, which is the threshold voltage of the FETs Q1, as in the present embodiment, yields conversion gain of 8.979 dB. It can also be understood that the conversion gain, in a case of setting the drain voltage Vd of the FETs Q1 to 0.2 V that is the knee voltage and the gate voltage Vg to 0.3 V as in the conventional drain injection distributed mixer, is 10.276 dB.

[0070] Thus, in the present embodiment, conversion gain that is higher than conventionally obtained can be obtained. The reason why high conversion gain can be thus obtained is that the amount of change of i.sub.IF, which decides the conversion gain of the mixer, is greater under bias conditions where the drain voltage Vd is 0 V and the gate voltage Vg is the threshold voltage, than conventionally-used bias conditions, as described above in the principle of embodiments of the invention. Table 1 illustrates comparison results of electric power consumption and conversion gain for the conventional configuration and the configuration according to the present embodiment.

TABLE-US-00001 TABLE 1 Drain Drain current Total Drain Drain electric Drain per drain voltage application power Conversion voltage FET 1 current drop voltage consumption gain [V] [mA] [mA] [V] [V] [mW] [dB] Conventional 0.2 4.25 34 0 0.2 6.8 10.276 configuration when using L2 Conventional 0.2 4.25 34 1.7 1.9 64.6 10.276 configuration when using Rdd Present 0 0 0 0 0 0 8.979 embodiment

[0071] The when using L2 in the conventional configuration shows a case of using the choke coil L2 as the bias circuit 3a, as illustrated in FIG. 10. Also, the when using Rdd in the conventional configuration shows a case of using the resistor Rdd of 50 as the bias circuit 3, as illustrated in FIG. 13. Drain voltage drop refers to voltage drop at the bias circuits 3 and 3a. Drain application voltage is the Vdd in FIG. 13 and FIG. 10.

[0072] In a configuration where the bias circuits 3 and 3a are used to apply voltage to the drains of the FETs Q1 as done conventionally, current flows to the bias circuits 3 and 3a, and accordingly electric power consumption occurs. In a case of using the bias circuit 3a, there is no direct current voltage drop at the choke coil L2, so electric power consumption can be suppressed, but it is difficult to realize a choke coil that has a great inductance value at frequencies of 100 GHz and above.

[0073] Accordingly, in reality the drains of the FETs Q1 are biased via the bias circuit 3 made up of the resistor Rdd. In a case of using the bias circuit 3, there is a need to apply a large voltage Vdd taking the voltage drop at the resistor Rdd into consideration, so electric power consumption is even greater.

[0074] Conversely, the bias voltage on the drains of the FETs Q1 is zero in the present embodiment, so the electric power consumption by the bias circuit at the drain side is zero.

SECOND EMBODIMENT

[0075] Next, a second embodiment of the present invention will be described. FIG. 12 is a circuit diagram illustrating a configuration of a drain injection distributed mixer according to the present embodiment. In the present embodiment, a drain injection distributed mixer of a double-balanced configuration is shown where the individual unit mixers making up the distributed mixer have a differential configuration, and further the artificial transmission line where LO signals are input and the artificial transmission line where RF signals are input both have differential configurations.

[0076] The drain injection distributed mixer according to the present embodiment is configured of an artificial transmission line 1p of which the input end is connected to an LO terminal 5p at the positive phase side and the terminal end is connected to an IF terminal 7p at the positive phase side, an artificial transmission line in of which the input end is connected to an LO terminal 5n at the negative phase side and the terminal end is connected to an IF terminal 7n at the negative phase side, an artificial transmission line 2p of which the input end is connected to an RF terminal 6p at the positive phase side, an artificial transmission line 2n of which the input end is connected to an RF terminal 6n at the negative phase side, a plurality of FETs Q1p and Q1n having differential configurations that are arrayed along the artificial transmission lines 1p, 1n, 2p, and 2n, and of which the gates are connected to the artificial transmission lines 2p and 2n and of which the drains are connected to the artificial transmission lines 1p and 1n and the sources are grounded, a bias circuit 4b that applies gate bias voltage to the terminal ends of the artificial transmission lines 2p and 2n, and terminating resistors R1p and R1n of 50 that connect the terminal ends of the artificial transmission lines 2p and 2n and the ground.

[0077] In FIG. 12, LOp is positive-phase-side LO signals, LOn is LO signals complementary to LOp, RFp is positive-phase-side RF signals, RFn is RF signals complementary to RFp, IFp is positive-phase-side IF signals, and IFn is IF signals complementary to IFp.

[0078] The artificial transmission line 1p is configured of a plurality of transmission lines CPW1p that are serially connected, and the artificial transmission line in is configured of a plurality of transmission lines CPW1n that are serially connected. In the same way, the artificial transmission line 2p is configured of a plurality of transmission lines CPW2p that are serially connected, and the artificial transmission line 2n is configured of a plurality of transmission lines CPW2n that are serially connected. The plurality of FETs Q1p are disposed equidistantly between the artificial transmission lines 1p and 2p, following the direction of signals flowing over these artificial transmission lines 1p and 2p, and the plurality of FETs Q1n are disposed at the same intervals as the FETs Q1p between the artificial transmission lines 1n and 2n, following the direction of signals flowing over these artificial transmission lines 1n and 2n, in the same way as in the first embodiment.

[0079] The bias circuit 4b is configured of a resistor Rgp of which one end is connected to the terminal end of the artificial transmission line 2p and drain bias voltage Vgg is applied to the other end, a resistor Rgn of which one end is connected to the terminal end of the artificial transmission line 2n and drain bias voltage Vgg is applied to the other end, a capacitor Cp of which one end is connected to the other end of the resistor Rgp and the other end is grounded, and a capacitor Cn of which one end is connected to the other end of the resistor Rgn and the other end is grounded.

[0080] In the present embodiment, the RF signals RFp and RFn that have differential configurations and the LO signals LOp and LOn that have differential configurations are mixed at the FETs Q1p and Q1n that have differential configurations, and IF signals IFp and IFn that have differential configurations are output from the IF terminals 7p and 7n.

[0081] In the present embodiment as well, the problem regarding applying drain bias that was a problem in conventional drain injection distributed mixers can be solved by the same principle as with the first embodiment. Specifically, the direct current voltage of the drains of the FETs Q1p and Q1n can be set to zero, and the gate-source direct current voltage of the FETs Q1p and Q1n can be set to the threshold voltage of the FETs Q1p and Q1n.

[0082] In a case of applying embodiments of the present invention to a balanced distributed mixer where the artificial transmission lines 1p and 1n at the drain side have been designed as a balanced type as in the present embodiment, two bias circuits are reduced at the drain side, leading to simplification of the layout as well. The present invention is also applicable to a single-balanced configuration where RF signals are single-phase input and artificial transmission line at the gate side is singular.

[0083] Note that while examples of downconversion mixers have been given in the description of the first and second embodiments, embodiments of the present invention can be applied to upconversion mixers as well. In a case of applying embodiments of the present invention to an upconversion mixer, the input ends of the artificial transmission lines 2, 2p, and 2n in FIG. 9 and FIG. 12 can be connected to the IF terminals 7, 7p, and 7n, the terminal ends of the artificial transmission lines 1, 1p, and 1n connected to the RF terminals 6, 6p, and 6n, IF signals input to the artificial transmission lines 2, 2p, and 2n instead of RF signals, and RF signals output from the terminal ends of the artificial transmission lines 1, 1p, and 1n.

INDUSTRIAL APPLICABILITY

[0084] Embodiments of the present invention can be applied to circuit technology that handles radio frequency electrical signals.

REFERENCE SIGNS LIST

[0085] 1, 1p, 1n, 2, 2p, 2n Artificial transmission line

[0086] 4a, 4b Bias circuit

[0087] 5, 5p, 5n LO terminal

[0088] 6, 6p, 6n RF terminal

[0089] 7, 7p, 7n IF terminal

[0090] Q1, Q1p, Q1n FET

[0091] R1, R1p, R1n, Rgp, Rgn Resistor

[0092] L1 Choke coil

[0093] Cp, Cn Capacitor

[0094] CPW1, CPW1p, CPW1n, CPW2, CPW2p, CPW2n, CPW3 Transmission line

Distribution Mixer

Inventors

Cpc classification

Classification Explorer

H03D2200/0017

ELECTRICITY

Classification Explorer

H03D7/1441

ELECTRICITY

Classification Explorer

H03D7/1458

ELECTRICITY

Classification Explorer

H03D7/1466

ELECTRICITY

Classification Explorer

H03D9/0675

ELECTRICITY

Classification Explorer

H03D7/125

ELECTRICITY

Classification Explorer

H03D2200/0076

ELECTRICITY

Classification Explorer

H03D2200/0043

ELECTRICITY

International classification

Classification Explorer

H03D9/06

ELECTRICITY

Classification Explorer

H03D7/14

ELECTRICITY

Abstract

Claims

Description