Phase difference generator error compensation method of digital frequency generator

Abstract

The invention provides a phase difference generator error compensation method of a digital frequency generator, wherein the digital frequency generator comprises a phase difference generator, the phase difference generator comprises a phase compensation module and an adjusting module, the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; the adjusting module compensates the error of the third clock signal according to the clock phase difference. The method has the benefits that process errors in the phase difference generator are compensated.

Claims

1. A phase difference generator error compensation method of a digital frequency generator, applied to the digital frequency generator, the digital frequency generator comprising the phase difference generator, the phase difference generator comprising a phase compensation module and an adjusting module, wherein the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal and a second clock signal, and a phase difference exists between the first clock signal and the second clock signal; the phase compensation module outputs a third clock signal according to the first clock signal and the second clock signal, and the third clock signal is a difference signal of the first clock signal and the second clock signal; and the adjusting module compensates an error of the third clock signal according to the clock phase difference; the phase difference generator comprises a phase difference circuit, the phase difference circuit provides a comparator, a non-inverting input end of the comparator is connected to a reference voltage, an inverting input end of the comparator is connected in parallel with a voltage source VDD; the phase difference generator further comprises a first current source and a second current source; the phase difference generator further comprises a capacitor connecting the inverting input end of the comparator to GND; a first switch controlled by the first clock signal is connected in series between the first current source and the inverting input end of the comparator; and a second switch controlled by the second clock signal is connected in series between the second current source and the inverting input end of the comparator; wherein the adjusting module compensates the error of the third clock signal according to the clock phase difference by the following formula: $\left(\mathrm{VDD}-\mathrm{Vref}\right)=A*T_{\mathrm{VCO}}*2\text{/}{2}^N*\frac{I}{C}$ wherein VDD represents the voltage source VDD; V.sub.ref represents the reference voltage; T represents the time corresponding to the phase difference; I represents an overall current, and the overall current is a sum of the current of the first current source and the current of the second current source; C represents the capacitance value of the capacitor; and A represents a ratio of the current of the first current source to the overall current.

2. The phase difference generator error compensation method of a digital frequency generator of claim 1, wherein the clock phase difference is expressed by T.sub.VCO*2/2.sup.N; wherein T.sub.VCO represents a time when clock signals are input to a fraction divider for generating the first clock signal and the second clock signal; 2.sup.N represents the number of the clock signals configured to generate the third clock signal.

3. The phase difference generator error compensation method of a digital frequency generator of claim 1, wherein the adjusting module adjusts a current of the first current source, and/or a current of the second current source.

4. The phase difference generator error compensation method of a digital frequency generator of claim 1, wherein the adjusting module adjusts a capacitance value of the capacitor, and/or a charging/discharging speed.

5. The phase difference generator error compensation method of a digital frequency generator of claim 1, wherein the adjusting module adjusts an amplitude value of the reference voltage.

6. The phase difference generator error compensation method of a digital frequency generator of claim 1, wherein a relationship between the current of the first current source and the current of the second current source satisfies the following formula:
A*I+B*I=I; wherein B represents a ratio of the current of the second current source to the overall current.

7. The phase difference generator error compensation method of a digital frequency generator of claim 1, wherein a value of the current of the first current source is in a range from 0 to I, and a value of the current of the second current source is in a range from 0 to I.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present disclosure, and, together with the description, serve to explain the principles of the present invention.

(2) FIG. 1 is a circuit diagram of a phase difference circuit according to the present invention; and

(3) FIG. 2 is a schematic diagram showing the relationship between a difference voltage, a reference voltage and a third clock signal according to the present invention.

DETAILED DESCRIPTION

(4) The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

(5) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises and/or comprising, or includes and/or including or has and/or having when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

(6) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(7) As used herein, around, about or approximately shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term around, about or approximately can be inferred if not expressly stated.

(8) As used herein, the term plurality means a number greater than one.

(9) Hereinafter, certain exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings.

(10) The invention comprises phase difference generator error compensation method of a digital frequency generator, applied to the digital frequency generator, the digital frequency generator comprising the phase difference generator, the phase difference generator comprising a phase compensation module and an adjusting module, wherein

(11) the phase compensation module provides at least two clock signals, the at least two clock signals comprise a first clock signal CLKA and a second clock signal CLKB, and a phase difference exists between the first clock signal CLKA and the second clock signal CLKB; the phase compensation module outputs a third clock signal CLKOUT according to the first clock signal CLKA and the second clock signal CLKB, and the third clock signal CLKOUT is a difference signal of the first clock signal CLKA and the second clock signal CLKB; and

(12) the adjusting module compensates an error of the third clock signal CLKOUT according to the clock phase difference.

(13) In the above-mentioned embodiment, a plurality of clock signals are provided by the phase compensation module, a difference signal of the first clock signal and the second clock signal is obtained, then an error of the difference signal is compensated by the adjusting module according to the clock phase difference. In this way, process errors in the phase difference generator are correspondingly compensated, so that the compensation precision of the phase difference generator is improved, and the product quality is improved.

(14) Furthermore, as a preferred embodiment, the number of the third clock signal CLKOUT generated from the phase difference generator is 2.sup.N+1, and two clock signals, the first clock signal CLKA and the second clock signal CLKB, are selected at a particular time point; a clock phase difference exists between the first clock signal CLKA and the second clock signal CLKB, then a compensation error of the phase difference generator is obtained by the adjusting module of the phase difference generator according to the clock phase difference.

(15) The above-mentioned embodiment may work in a TSMC 28 nm 12 nm chip, and process errors in the phase difference generator are precisely compensated, and the product quality is improved.

(16) Furthermore, in the above-mentioned embodiment, the clock phase difference is expressed by T.sub.VCO*2/2.sup.N;

(17) wherein T.sub.VCO represents a time when clock signals are input to a fraction divider for generating the first clock signal CLKA and the second clock signal CLKB;

(18) 2.sup.N represents the number of the clock signals configured to generate the third clock signal CLKOUT.

(19) Furthermore, in the above-mentioned embodiment, as shown in FIG. 1, the phase difference generator comprises a phase difference circuit, the phase difference circuit provides a comparator CMP, a forward input end of the comparator CMP is connected to a reference voltage Vref, a reverse input end of the comparator CMP is connected in parallel with a voltage source VDD;

(20) the phase difference generator further comprises a first current source I.sub.A and a second current source I.sub.B;

(21) the phase difference generator further comprises a capacitor C connecting the reverse input end of the comparator CMP to GND;

(22) a first switch controlled by the first clock signal CLKA is connected in series between the first current source I.sub.A and the reverse input end of the comparator CMP; and a second switch controlled by the second clock signal CLKB is connected in series between the second current source I.sub.B and the reverse input end of the comparator CMP.

(23) Furthermore, as a preferred embodiment, a relationship between a difference voltage PI and the reference voltage Vref is compared in the comparator CMP, wherein the difference voltage PI refers to a voltage obtained by performing charging and discharging operation on the capacitor C through the first current source and the second current source; as shown in FIG. 2, when the difference voltage PI is less than the reference voltage Vref, the frequency of the third clock signal CLKOUT increases, and the comparator CMP outputs the third clock signal CLKOUT.

(24) Furthermore, as a preferred embodiment, when the phase difference generator selects three clock signals at a particular time point, that is, a third current source is added to the phase difference circuit, and a third switch controlled by the third clock signal is connected in series between the third current source and the reverse input end of the comparator CMP. Therefore, the adjusting module is connected to a reference current source I bias. The adjusting module may adjust the current of the first current source I.sub.A, and/or the current of the second current source I.sub.B, and/or the current of the third current source through the reference current source I bias, so that process errors in the phase difference generator are correspondingly compensated.

(25) Furthermore, in the above-mentioned embodiment, the adjusting module is connected to a reference current source I bias. The adjusting module may adjust the current of the first current source I.sub.A, and/or the current of the second current source I.sub.B through the reference current source I bias, so that process errors in the phase difference generator are correspondingly compensated.

(26) Furthermore, in the above-mentioned embodiment, the adjusting module adjusts a capacitance value of the capacitor C, and/or a charging/discharging speed, so that process errors in the phase difference generator are correspondingly compensated.

(27) Furthermore, in the above-mentioned embodiment, the adjusting module adjusts an amplitude value of the reference voltage Vref, so that process errors in the phase difference generator are correspondingly compensated.

(28) Furthermore, in the above-mentioned embodiment, a relationship between the current of the first current source I.sub.A and the current of the second current source I.sub.B satisfies the following formula:
p A*I+B*I=I.

(29) Furthermore, in the above-mentioned embodiment, a value of the current of the first current source I.sub.A is in a range from 0 to I, and a value of the current of the second current source I.sub.B is in a range from 0 to I.

(30) Furthermore, in the above-mentioned embodiment, the following formula may be obtained from the phase difference circuit:
I*A*(T+T.sub.VCO*2/2.sup.N)+I*B*T=(VDDVref)*C;(1)

(31) wherein VDD represents the voltage source VDD;

(32) Vref represents the reference voltage Vref;

(33) T represents the time corresponding to the phase difference;

(34) I represents an overall current, and the overall current is a sum of the current of the first current source I.sub.A and the current of the second current source I.sub.B;

(35) C represents the capacitance value of the capacitor C; and

(36) A represents a ratio of the current of the first current source I.sub.A to the overall current; and

(37) B represents a ratio of the current of the second current source I.sub.B to the overall current.

(38) The following formula is obtained from the formula (1):

(39) $\begin{array}{cc}T=\frac{\left(\mathrm{VDD}-\mathrm{Vref}\right)*C}{I}-A*T_{\mathrm{VCO}}*2\text{/}{2}^N;& \left(2\right)\end{array}$

(40) T1 and T2 (two time points corresponding to two phase differences) are substituted into the formula (2), then the following formula is obtained:
T2T1=(A1A2)*T.sub.VCO*2/2.sup.N;(3)

(41) wherein T2T1 represents a compensation phase difference between two compensation cycles of the phase compensation module;

(42) A1 represents a ratio of the current of the first current source I.sub.A to the overall current at the period of time T1; and

(43) A2 represents a ratio of the current of the first current source I.sub.A to the overall current at the period of time T2.

(44) From the formula (3), process errors in the phase difference generator are correspondingly compensated by adjusting the current of the first current source I.sub.A.

(45) From the formula (2), when A=1, B=0, the following formula may be obtained by conversion:

(46) $\begin{array}{cc}\left(\mathrm{VDD}-\mathrm{Vref}\right)=\left(A*T_{\mathrm{VCO}}*2\text{/}{2}^N+T\right)*\frac{I}{C};& \left(4\right)\end{array}$

(47) and a target optimum value may be obtained from the formula (4).

(48) The adjusting module compensates the error of the third clock signal CLKOUT by formula (4) according to the clock phase difference.

(49) Furthermore, as a preferred embodiment, when T=0 for formula (4), the following formula is obtained:

(50) $\begin{array}{cc}\left(\mathrm{VDD}-\mathrm{Vref}\right)=A*T_{\mathrm{VCO}}*2\text{/}{2}^N*\frac{I}{C};& \left(5\right)\end{array}$

(51) In formula 5, the overall current I, the capacitance value C of the capacitor C, and the reference voltage Vref may all deviate from set values. Since the process errors of each manufactured product are different, that is, the overall current I, the capacitance value C of the capacitor C, and the reference voltage Vref are different, when the adjusting module sets as A=1, B=0, the overall current, the capacitance value of the capacitor C, and the reference voltage Vref are adjusted according to the third clock signal CLKOUT, and the overall current, the capacitance value C of the capacitor C, and the reference voltage Vref are made to be closer to the set values, so that process errors in the phase difference generator are correspondingly compensated, the compensation precision of the phase difference generator is improved, and the clock quality is improved.

(52) The above descriptions are only the preferred embodiments of the invention, not thus limiting the embodiments and scope of the invention. Those skilled in the art should be able to realize that the schemes obtained from the content of specification and drawings of the invention are within the scope of the invention.