Time-efficient offset cancellation for multi-stage converters

Abstract

Techniques to reduce the on-time of a multi-stage ADC circuit by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. The techniques can allow the signal conditioning circuit and the residue amplifier to settle together.

Claims

1. A method of canceling an offset of a signal conditioning circuit coupled to an input of a multi-stage analog-to-digital converter (ADC) circuit, the method comprising: sampling an analog input signal and the offset; performing; by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset; canceling the offset and amplifying a residue of the sampled analog input signal; performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal; and generating a digital output signal representing the sampled analog input signal.

2. The method of claim 1, wherein canceling the offset comprises: shorting an input of the signal conditioning circuit to determine the offset; and subtracting the offset from the sampled analog input signal and offset.

3. The method of claim 1, wherein performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes: performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset using a successive approximation register (SAR) algorithm.

4. The method of claim 1, wherein performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes: performing; by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset using a delta-sigma algorithm.

5. The method of claim 1, wherein performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes: performing; by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset using a flash converter.

6. The method of claim 1, wherein performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input includes: performing; by the second stage of the ADC circuit; the second conversion on the residue of the sampled analog input using a successive approximation register (SAR) algorithm.

7. The method of claim 1, wherein performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input includes: performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input using a delta-sigma algorithm.

8. The method of claim 1, wherein performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input includes: performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input using a flash converter.

9. A multi-stage analog-to-digital converter (ADC) circuit having an input coupled to a signal conditioning circuit having an offset, the ADC circuit comprising: a sample-and-hold circuit that samples an analog input signal and the offset; a first stage including a first ADC sub-circuit that performs a first conversion on the sampled analog input signal and offset; a control circuit that operates a plurality of switches to generate the residue of the first conversion and eliminate the signal conditioning circuit offset from the residue; a residue amplifier that amplifies the residue of the sampled analog input signal; a second stage including a second ADC sub-circuit that performs a second conversion on the residue of the sampled analog input signal; and an encoder circuit that combines first and second conversion results and generate a digital output signal representing the sampled analog input signal.

10. The circuit of claim 9, wherein the first ADC sub-circuit includes a successive approximation register (SAR) ADC configured to perform a SAR algorithm.

11. The circuit of claim 9, wherein the first ADC sub-circuit includes a delta-sigma ADC that performs a delta-sigma algorithm.

12. The circuit of claim 9, wherein the first ADC sub-circuit includes a flash ADC that performs a flash algorithm.

13. The circuit of claim 9, wherein the second ADC sub-circuit includes a successive approximation register (SAR) ADC that performs a SAR algorithm.

14. The circuit of claim 9, wherein the second ADC sub-circuit includes a delta-sigma ADC that performs a delta-sigma algorithm.

15. The circuit of claim 9, wherein the second ADC sub-circuit includes a flash ADC configured that performs a flash algorithm.

16. The circuit of claim 9, wherein the first ADC sub-circuit and/or the second ADC sub-circuit is a hybrid ADC circuit that performs at least two algorithms selected from a group consisting of a successive approximation register (SAR) algorithm, a delta-sigma algorithm, and a flash algorithm.

17. The circuit of claim 9, wherein the signal conditioning circuit is a buffer circuit.

18. A multi-stage analog-to-digital converter (ADC) circuit having an input coupled to a signal conditioning circuit having an offset, the ADC circuit comprising: a sample-and-hold circuit configured to sample an analog input signal and the offset; means for performing, by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset; means for canceling the offset and amplifying a residue of the sampled analog input signal; means for performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal; and means for generating a digital output signal representing the sampled analog input signal.

19. The circuit of claim 18, wherein the means for performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes a successive approximation register (SAR) ADC configured to perform a SAR algorithm.

20. The circuit of claim 18, wherein the means for performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input signal includes a successive approximation register (SAR) ADC configured to perform a SAR algorithm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

(2) FIG. 1A is a conceptual block diagram of an example of a multi-stage ADC circuit during a first phase of an operation that can implement various techniques of this disclosure.

(3) FIG. 1B is a conceptual block diagram of the multi-stage ADC circuit of FIG. 1A during a second phase of operation.

(4) FIG. 1C is a conceptual block diagram of the multi-stage ADC circuit of FIG. 1A during a third phase of operation.

(5) FIG. 1D is a conceptual block diagram of the multi-stage ADC circuit of FIG. 1A during a fourth phase of operation.

(6) FIG. 2 is a conceptual block diagram of another example of a multi-stage ADC circuit that can implement various techniques of this disclosure.

(7) FIG. 3 is a flowchart of an example of a method of canceling an offset of a signal conditioning circuit coupled to an input of a multi-stage analog-to-digital converter (ADC) circuit using various techniques of this disclosure

DETAILED DESCRIPTION

(8) Multi-stage analog-to-digital converters can utilize a successive series of stages (or cycles of operation) each arranged to develop a digital output of limited scope, e.g., one or more bits, and to produce from each stage (or cycle of operation) an analog residue signal as the input for the next stage (or cycle), In this way, a high-resolution output can be developed by combining the digital outputs of the several stages or cycles.

(9) Multi-stage ADC architectures can use inter-stage amplification, e.g., using a residue amplifier, particularly when the overall resolution exceeds about nine bits. Such amplification is for the purpose of raising the residue of one conversion to a level that can be digitized by the next subsequent stage.

(10) Multi-stage ADC architectures can use various analog-to-digital converter (ADC) topologies, including delta-sigma, flash, and successive approximation register (SAR) data converters. One of the attractive characteristics of SAR data converters is their ability to scale power consumption with conversion rate. The data converter only requires power during a conversion and can be powered down between conversions. Hence, the shorter the duty cycle the converter is on, the less power is consumed.

(11) Zero-drive data converters, e.g., converters that do not draw current from the input, can incorporate a buffer amplifier at the input, such that they can be driven by sources with a high impedance. Zero-drive converters can include buffer circuits, e.g., buffer amplifiers, or other signal conditioning circuitry, e.g., instrumentation amplifiers, transimpedance amplifiers, and filters, coupled to their inputs. To eliminate offset and 1/f noise generated by the signal conditioning circuitry, it can be chopped or auto-zeroed, for example. Both chopping and auto-zeroing can extend the time that the data-converter is powered up, and hence increase the duty, cycle.

(12) In an existing approach to offset cancellation in a multi-stage ADC circuit, the offset of the signal conditioning circuit, e.g., buffer circuit, coupled to an input of the multi-stage ADC circuit can be auto-zeroed. Then, the analog input signal can be sampled.

(13) The first stage of the multi-stage ADC circuit can perform a coarse conversion on the sampled analog input signal to generate an output, e.g., the most significant bits (MSBs) and a residue signal. The residue signal is the difference between a feedback DAC output, which converts the coarse conversion output (MSBs) to an analog signal, and the sampled analog input signal. The residue signal can be amplified by a residue amplifier and transferred to the second stage of the multi-stage ADC circuit and the second stage can perform a fine conversion on the amplified residue signal to generate the remaining bits, e.g., the least significant bits (LSBs).

(14) In the case of chopping, the two sampling phases can include the sum of two half samples, each with an opposite polarity of the offset of the signal conditioning circuit. As such, the total conversion time would be similar to the approach described above.

(15) For a continuous running ADC, the signal conditioning circuit can perform auto-zeroing during one conversion (while the ADC is performing either a coarse conversion or a fine conversion, for example), and next apply the auto-zeroed signal conditioning circuit during the sampling phase of the next conversion. Hence, the algorithm can measure offset in one conversion, and correct for it in the next conversion. The offset therefore should be substantially constant between any two subsequent samples. Due to drift and lit noise, this condition fails when the time between two subsequent samples is too long, like in the case of convert on demand. In that case, the offset should be measured and eliminated within a conversion.

(16) The present inventors have recognized a need to eliminate the extra time needed for offset cancellation in a multi-stage ADC circuit. Using various techniques of this disclosure, the on-time of the multi-stage ADC circuit can be reduced by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. As described in detail below, the techniques of this disclosure can allow the signal conditioning circuit and the residue amplifier to settle together.

(17) FIG. 1A is a conceptual block diagram of an example of a multi-stage ADC circuit 10 during a first phase of an operation that can implement various techniques of this disclosure. A signal conditioning circuit 12, e.g., buffer circuit, having an offset voltage Von is coupled to an input of the multi-stage ADC circuit 10 and is configured to receive and condition an analog input signal V.sub.IN. The multi-stage ADC circuit 10 shown in FIG. 1A can include two stages. The first stage can include a first sample-and-hold circuit (S/H) 14, a first ADC sub-circuit 16, a first digital-to-analog converter (DAC) circuit 18, and a residue amplifier circuit 20. The second stage can include a second S/H circuit 22, a second ADC sub-circuit 24, and an encoder circuit 26. A control circuit 28 can control various operations of ADC circuit 10, including closing and opening switches S1-S5. The control circuit 28 can operate the switches S1-S5 to generate or establish a residue of the first conversion and eliminate, e.g., concurrently, the signal conditioning circuit offset from that residue.

(18) Operation of the multi-stage ADC circuit 10 will now be briefly described, without specific reference to the first phase of operation. The first ADC sub-circuit 16 of the first stage can perform a first conversion, e.g., coarse conversion, on the sampled analog input signal to generate an output, e.g., the MSBs. A residue signal can be generated by subtracting the output of the first DAC circuit 18 from the sampled analog input signal V.sub.IN. The residue signal can be amplified by the residue amplifier 20 and transferred to the second S/H circuit 22 of the second stage of the multi-stage ADC circuit 10. The second ADC sub-circuit 24 of the second stage can perform a second conversion, e.g., fine conversion, on the amplified residue signal to generate an output containing the remaining bits, e.g., the LSBs. The encoder circuit 26 can receive the output of the first ADC sub-circuit 16 (a first conversion result) and the output of the second ADC sub-circuit 24 (a second conversion result) and generate a digital output signal Dour.

(19) During the first phase of operation, a control circuit 28 can close the switches S1 and S4, open the switches S2, S3, and S5, and the first S/H circuit 14, e.g., including one or more capacitors, can sample the analog input signal V.sub.IN. The offset voltage V.sub.OFF of the signal conditioning circuit 12 is added to the analog input signal V.sub.IN and sampled. During sampling, the remaining circuitry of the multi-stage ADC circuit 10 can be inactive and, as such, consuming little to no power.

(20) FIG. 1B is a conceptual block diagram of the multi-stage ADC circuit of FIG. 1A during a second phase of operation. During the second phase of operation, the control circuit 28 can open the switch S1 and close the switch S2 to couple the input of the signal conditioning circuit 12 to ground (if single-ended) to establish the offset V.sub.OFF of the signal conditioning circuit 12, and close the switch S5 to couple the first S/H circuit 14 to the first ADC sub-circuit 16. The first stage of the multi-stage ADC circuit 10 can perform a conversion, e.g., coarse conversion, on the combination of the sampled analog input signal V.sub.IN and the offset voltage V.sub.OFF associated with that sample and generate a first stage output. During this phase, one or more of the signal conditioning circuit 12, the residue amplifier 20, the second S/H circuit 22, the second ADC sub-circuit 24, and the encoder circuit 26 can be inactive and, as such, consume little to no power.

(21) FIG. 1C is a conceptual block diagram of the multi-stage ADC circuit of IA during a third phase of operation. During this phase, the signal conditioning circuit 12, the first S/H circuit 14, the first DAC circuit 18, the residue amplifier 20, and the second S/H circuit 22 can be active, and the first ADC sub-circuit 16, the second ADC sub-circuit 24, and the encoder circuit 26 can be inactive. During the third phase of operation, the control circuit 28 can close the switch S3 to apply the offset voltage V.sub.OFF to the summing node 15. The offset voltage V.sub.OFF can be canceled by subtracting the offset voltage V.sub.OFF (from coupling the input of the signal conditioning circuit 12 to ground) from the sum of the sampled analog input signal V.sub.IN and the offset voltage V.sub.OFF. For example, the summing node 15 can be configured to invert the offset input and the inverted offset voltage V.sub.OFF can be combined with the sum of the sampled analog input signal V.sub.IN and the offset voltage V.sub.OFF. Then, the residue amplifier 20 can amplify the residue of the sampled analog input signal V.sub.IN.

(22) In this manner, the offset voltage V.sub.OFF can be canceled while the multi-stage ADC circuit 10 performs the residue amplification. The residue amplifier 20 takes time to amplify and the signal conditioning circuit takes time to settle. However, using the techniques described in this disclosure, the speed of the multi-stage ADC circuit can be improved because the time for the residue amplifier to amplify and the time for the signal conditioning circuit to settle happen concurrently rather than sequentially (as in other approaches). As such, the net time is the time of the residue amplifier to amplify.

(23) FIG. 1D is a conceptual block diagram of the multi-stage ADC circuit of FIG. 1A during a fourth phase of operation. During this phase, the second S/H circuit 22 and the second ADC sub-circuit 24 can be active while the other circuitry can be powered off. During the fourth stage of operation, the control circuit 28 can open the switch S3 and the second stage of the multi-stage ADC circuit 10 can perform a conversion, e.g., a fine conversion, on the residue of the sampled analog input signal V.sub.IN (and generate a second stage output). The encoder circuit 26 can receive the first stage output and the second stage output and generate a digital output D.sub.OUT that represents the sampled analog input signal V.sub.IN. It should be noted that in some implementations, the second ADC sub-circuit 24 can be configured to accommodate an extra correction range for the offset that was added during the first stage of operation.

(24) Although FIGS. 1A-1D were described with respect to a two-stage ADC circuit, the techniques of this disclosure are applicable to multi-stage ADC circuits having more than two stages. In multi-stage converters, there can be a second, a third, and more stages. There can be a second residue amplifier, that amplifies the second residue from the second stage. And a third ADC sub-circuit can perform a third conversion on the residue from the second stage. An encoder combines the outputs of all ADC sub-circuits stages and generates the digital output.

(25) The first ADC sub-circuit 16 of the first stage can be implemented using various ADC circuit topologies. For example, the first ADC sub-circuit 16 can be a SAR ADC circuit configured to perform a conversion using a SAR algorithm. In other example implementations, the first ADC sub-circuit 16 can be a delta-sigma ADC circuit configured to perform a conversion using a delta-sigma algorithm. In other example implementations, the first ADC sub-circuit 16 can be a flash converter.

(26) Similarly, the second ADC sub-circuit 24 of the second stage can be implemented using various ADC circuit topologies. For example, the second ADC sub-circuit 24 can be a SAR ADC circuit configured to perform a conversion using a SAR algorithm. In other example implementations, the second ADC sub-circuit 24 can be a delta-sigma ADC circuit configured to perform a conversion using a delta-sigma algorithm. In other example implementations, the second ADC sub-circuit 24 can be a flash converter.

(27) In other example configurations, the first ADC sub-circuit 16 can be a hybrid ADC circuit configured to perform at least two algorithms selected from a group consisting of a successive approximation register (SAR) algorithm, a delta-sigma algorithm, and a flash algorithm. For example, the first ADC sub-circuit 16 can include both flash converter circuitry and SAR circuitry. Alternatively, or additionally, the second ADC sub-circuit can be configured as a hybrid ADC circuit.

(28) FIG. 2 depicts a specific non-limiting multi-stage ADC circuit that can implement various techniques in this disclosure. In particular, the multi-stage ADC circuit of FIG. 2 utilizes SAR ADC sub-circuits.

(29) FIG. 2 is a conceptual block diagram of another example of a multi-stage ADC circuit that can implement various techniques of this disclosure. The multi-stage ADC circuit 50 shown in FIG. 2 includes two stages, but the techniques are applicable to more than two stages. The multi-stage ADC circuit 50 of FIG. 2 can include components similar to those shown in FIGS. 1A-ID and are depicted with similar reference numbers.

(30) The first stage can include a first sample-and-hold circuit (S/H) 14, a first SAR ADC sub-circuit including a first comparator circuit 52 and a first SAR register circuit 54, a first DAC circuit 18, and a residue amplifier circuit 20. The second stage can include a second S/H circuit 22, a second SAR ADC sub-circuit including a second comparator circuit 56 and a second SAR register circuit 58, and an encoder circuit 26. A buffer circuit 60, having an offset voltage V.sub.OFF and coupled to an input of the multi-stage ADC circuit 50, is configured to receive and buffer an analog input signal V.sub.IN.

(31) The multi-stage ADC circuit 50 shown in FIG. 2 can operate in several phases, such as described above with respect to FIGS. 1A-1D. In general, the phases can include sampling the analog input signal V.sub.IN without auto-zeroing the buffer circuit 60, performing a first conversion, e.g., coarse conversion, using the first SAR ADC sub-circuit, performing residue amplification of the sampled residue while cancelling the buffer offset, and performing a second conversion, e.g., fine conversion, using the second SAR ADC sub-circuit.

(32) FIG. 3 is a flowchart of an example of a method 70 of canceling an offset of a signal conditioning circuit coupled to an input of a multi-stage analog-to-digital converter (ADC) circuit using various techniques of this disclosure. At block 72, the method 70 can include sampling an analog input signal and the offset. For example, the control circuit 28 of FIG. 1A can close the switch S1 and the first S/H circuit 14 can sample the analog input signal V.sub.IN and the offset voltage V.sub.OFF of the signal conditioning circuit 12.

(33) At block 74, the method 70 can include performing, by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset V.sub.OFF. For example, the control circuit 28 of FIG. 1B can open the switch S1 and close the switch S2 to couple the input of the signal conditioning circuit 12 to ground (if single-ended) to establish the offset V.sub.OFF of the signal conditioning circuit 12. The first stage of the multi-stage ADC circuit 10 can perform a conversion, e.g., coarse conversion, on the combination of the sampled analog input signal V.sub.IN and the offset voltage V.sub.OFF associated with that sample.

(34) At block 76, the method 70 can include canceling the offset and amplifying a residue of the sampled analog input signal. For example, the offset voltage V.sub.OFF can be canceled by subtracting the offset voltage V.sub.OFF (from coupling the input of the signal conditioning circuit 12 to ground) from the sum of the sampled analog input signal V.sub.IN and the offset voltage V.sub.OFF. Then, the residue amplifier 20 can amplify the residue of the sampled analog input signal V.sub.IN.

(35) At block 78, the method 70 can include performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal. For example, the second stage of the multi-stage ADC circuit 10 of FIG. 1D can perform a conversion, e.g., a fine conversion, on the residue of the sampled analog input signal V.sub.IN (and generate a second stage output, or conversion result).

(36) At block 80, the method 70 can include generating a digital output signal representing the sampled analog input signal. For example, the encoder circuit 26 of FIG. 11) can receive the first stage output (first stage conversion result) and the second stage output (second stage conversion result) and generate a digital output D.sub.OUT that represents the sampled analog input signal V.sub.IN.

(37) Using the techniques described above, the speed of the multi-stage ADC circuit can be improved because the time for the residue amplifier to amplify and the time for the signal conditioning circuit to settle happen concurrently rather than sequentially (as in other approaches). Thus, the net time is the time of the residue amplifier to amplify.

NOTES

(38) Each of the non-limiting aspects or examples described herein may stand on its own or may be combined in various permutations or combinations with one or more of the other examples.

(39) The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as examples. Such examples may include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

(40) In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.

(41) In this document, the terms a or an are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of at least one or one or more. In this document, the term or is used to refer to a nonexclusive or, such that A or B includes A but not B, B but not A, and A and B, unless otherwise indicated. In this document, the terms including and in which are used as the plain-English equivalents of the respective terms comprising and wherein. Also, in the following claims, the terms including and comprising are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms first, second, and third, etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

(42) Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

(43) The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.