Semiconductor thin-film and manufacturing method thereof, thin-film transistor, and display apparatus

Abstract

A method for manufacturing a semiconductor thin film includes sequentially forming a first semiconductor layer, an intermediate layer, and a second semiconductor layer over a substrate. The first semiconductor layer and the second semiconductor layer can be one and another of an n-type semiconductor layer and a p-type semiconductor layer. At least one of the first semiconductor layer, the intermediate layer, or the second semiconductor layer is formed via a solution process. The n-type semiconductor layer can include indium oxide. The intermediate layer can include a self-assembly material. The p-type semiconductor layer can include a p-type organic semiconductor material, and can be pentacene. On the basis, a semiconductor thin film manufactured thereby, a semiconductor thin film transistor, and a display apparatus, are also disclosed.

Claims

1. A method for manufacturing a semiconductor thin film, comprising: forming a first semiconductor layer over a substrate; forming an intermediate layer over the first semiconductor layer, wherein the intermediate layer is formed of a phosphate ester; and forming a second semiconductor layer over the intermediate layer; wherein: one of the forming a first semiconductor layer over a substrate and the forming a second semiconductor layer over the intermediate layer comprises: forming an n-type semiconductor layer; another of the forming a first semiconductor layer over a substrate and the forming a second semiconductor layer over the intermediate layer comprises: forming a p-type semiconductor layer; at least one of the forming a first semiconductor layer over a substrate, the forming an intermediate layer over the first semiconductor layer, or the forming a second semiconductor layer over the intermediate layer is via a solution process; each of the forming a first semiconductor layer over a substrate, the forming an intermediate layer over the first semiconductor layer, and the forming a second semiconductor layer over the intermediate layer is via a solution process; the intermediate layer comprises a self-assembly material, configured to reduce surface roughness between an inorganic semiconductor layer and an organic semiconductor layer and improve hole mobility in the p-type semiconductor material; and the self-assembly material comprises a phosphate ester capable of self-assembly, and the forming an intermediate layer over the first semiconductor layer comprises: submerging a top surface of the first semiconductor layer in an alcohol solution of the phosphate ester for a certain amount of time to form a thin layer of phosphate ester over the top surface of the first semiconductor layer.

2. The method of claim 1, wherein the forming an n-type semiconductor layer is via a solution process.

3. The method of claim 1, wherein the n-type semiconductor layer comprises an inorganic oxide semiconductor material.

4. The method of claim 3, wherein the n-type semiconductor layer comprises indium oxide, and the forming an n-type semiconductor layer comprises: coating a first surface with a solution of indium chloride; and treating the first surface to thereby form an n-type semiconductor thin film thereon.

5. The method of claim 4, wherein the forming an n-type semiconductor layer further comprises: patterning the n-type semiconductor thin film to thereby form the n-type semiconductor layer on the first surface.

6. The method of claim 1, wherein the p-type semiconductor layer comprises a p-type organic semiconductor material capable of solution preparation to thereby form the p-type semiconductor layer.

7. The method of claim 6, wherein the forming a p-type semiconductor layer comprises: spin-coating, printing, or pulling a solution of the p-type organic semiconductor material.

8. A method for manufacturing a thin-film transistor (TFT), comprising: forming a semiconductor active layer over a substrate, comprising the method for manufacturing a semiconductor thin film according to claim 1.

9. The method according to claim 8, further comprising: forming a source electrode and a drain electrode over the semiconductor thin film.

10. The method according to claim 9, wherein each of the forming a gate electrode over the substrate, the forming a gate electrode insulating layer over the gate electrode, the forming the semiconductor thin film over the gate electrode insulating layer, and the forming a source electrode and a drain electrode over the semiconductor thin film is carried out under a temperature of no more than 230 C.

11. The method according to claim 10, wherein each of the forming a gate electrode over the substrate, the forming a gate electrode insulating layer over the gate electrode, the forming the semiconductor thin film over the gate electrode insulating layer, and the forming a source electrode and a drain electrode over the semiconductor thin film is carried out via a solution process.

12. The method according to claim 8, further comprising, prior to the forming a semiconductor active layer over a substrate: forming a gate electrode over the substrate; and forming a gate electrode insulating layer over the gate electrode; wherein: the forming a semiconductor active layer over a substrate comprises: forming the semiconductor thin film over the gate electrode insulating layer.

13. The method according to claim 12, wherein at least one of the forming a gate electrode over the substrate and the forming a source electrode and a drain electrode over the semiconductor thin film comprises: printing a conductive material, wherein the conductive material comprises at least one of silver gel, PEDOT, or a carbon nanotube.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) To more clearly illustrate some of the embodiments, the following is a brief description of the drawings. The drawings in the following descriptions are only illustrative of some embodiments. For those of ordinary skill in the art, other drawings of other embodiments can become apparent based on these drawings.

(2) FIG. 1A illustrates a structural diagrams of a thin-film transistor (TFT) according to a first embodiment of the present disclosure;

(3) FIG. 1B illustrates a structural diagrams of a thin-film transistor according to a second embodiment of the present disclosure;

(4) FIG. 2 illustrates a flowchart of a method for manufacturing a semiconductor thin film according to some embodiments of the present disclosure;

(5) FIG. 3A illustrates a flowchart of a method for manufacturing a TFT according to one embodiment of the present disclosure;

(6) FIG. 3B illustrates a flowchart of a method for manufacturing a TFT according to another embodiment of the present disclosure;

(7) FIG. 4A illustrates an n-type switching ratio curve of a TFT according to some embodiments of the present disclosure;

(8) FIG. 4B illustrates a p-type switching ratio curve of a TFT according to some embodiments of the present disclosure;

(9) FIG. 5A illustrates output I-V curves for n-type forward currents of a TFT according to some embodiments; and

(10) FIG. 5B illustrates output I-V curves for p-type reverse currents of a TFT according to some embodiments.

DETAILED DESCRIPTION

(11) In the following, with reference to the drawings of various embodiments disclosed herein, the technical solutions of the embodiments of the disclosure will be described in a clear and fully understandable way.

(12) The present disclosure provides a semiconductor thin film and a manufacturing method thereof, a thin-film transistor (TFT) and a manufacturing method thereof, an array substrate, and a display apparatus, aiming at improving the performance, reliability, and stability of the thin-film transistors.

(13) In a first aspect, the present disclosure provides a semiconductor thin film. The semiconductor thin film comprises an n-type semiconductor layer and a p-type semiconductor layer, which can be stacked together. In some embodiments, the semiconductor thin film can further comprise a self-assembly layer disposed between, and coupled to, the n-type semiconductor layer and the p-type semiconductor layer. In some implementations, the self-assembly layer can comprise a self-assembly material, such as a phosphate ester. Herein the phosphate ester can be polyol phosphoester, polyoxyethylene alkyl ether, tributyl phosphate, and trioctyl phosphate, etc.

(14) The semiconductor thin film as described above has improved performances compared with conventional semiconductor thin films in a number of aspects. In addition, because of the presence of both the n-type semiconductor layer and the p-type semiconductor layer that are stacked over one another in the semiconductor thin film, a TFT having such a semiconductor thin film as an active layer can be a bipolar TFT.

(15) Because of the stacked arrangement of the n-type semiconductor layer and the p-type semiconductor layer in the semiconductor thin film, during fabrication of the TFT, the n-type semiconductor layer and the p-type semiconductor layer can be separately manufactured.

(16) As such, compared with fabricating a bipolar TFT using a conventional method, which has either a mixed n-type and p-type semiconductor materials or a single semiconductor material having both n-type and p-type properties, the TFT according to various embodiments disclosed herein can have improved reliability, stability, and performance.

(17) In the semiconductor thin film as described above, the arrangement of the self-assembly layer can improve the contact between the n-type semiconductor layer and the p-type semiconductor layer, which in turn can lead to an improved performance of the TFT having the semiconductor thin film.

(18) In addition, because the n-type semiconductor layer and the p-type semiconductor layer are stacked over one another in the semiconductor thin film, and the self-assembly layer disposed between the n-type semiconductor layer and the p-type semiconductor layer comprises a phosphate ester that is capable of self-assembly, the semiconductor thin film has an improved semiconducting performance.

(19) Mover, the TFT can be fabricated via a solution process. The solution process can greatly simplify the manufacturing process, and is especially useful for the fabrication of large-area and flexible electronic components.

(20) According to some embodiments of the present disclosure, the n-type semiconductor layer can comprise an n-type inorganic semiconductor material, such as an inorganic oxide semiconductor material. The inorganic oxide semiconductor material can be, for example, zinc oxide (ZnO), indium zinc oxide (IZO), or indium oxide (In.sub.2O.sub.3).

(21) In some embodiments, the inorganic oxide semiconductor material has a composition that allows for a solution-based fabrication process. One example of such materials is the In.sub.2O.sub.3. To process the indium oxide n-type semiconductor layer, for example, a solution of indium chloride (InCl.sub.3) can be first applied to a surface by spin-coating, which then undergoes heating to get rid of the solvent to thereby form a thin film of InCl.sub.3. Upon UV exposure in an environment containing oxygen (such as air), hydrolysis can occur on the InCl.sub.3 thin film to ultimately form the n-type semiconductor layer (i.e. In.sub.2O.sub.3 semiconductor layer) with desired patterns.

(22) In some other embodiments of the present disclosure, the n-type semiconductor layer can comprise an n-type organic semiconductor material. The n-type organic semiconductor material may have a poorer performance compared with an n-type inorganic semiconductor material.

(23) According to some embodiments of the present disclosure, the p-type semiconductor layer can comprise a p-type organic semiconductor material. According to some other embodiments of the present disclosure, the p-type semiconductor layer can comprise a p-type inorganic semiconductor material.

(24) To apply a solution process to manufacture the p-type semiconductor layer, the p-type semiconductor layer can comprise a p-type organic semiconductor material, such as pentacene. Specifically, a solution of pentacene can be spin-coated onto the self-assembly layer, which then undergoes heating to get rid of the solvent to thereby obtain the p-type semiconductor layer.

(25) It is further noted that the composition for the self-assembly layer can be selected to have a good semiconductor property, and can be a phosphate ester that is capable of self-assembly. Herein the phosphate ester can be polyol phosphoester, polyoxyethylene alkyl ether, tributyl phosphate, and trioctyl phosphate, etc.

(26) Herein self-assembly is defined as process in which a plurality of basic structural units (e.g. molecules, nanomaterials) form a highly organized structure or pattern as a consequence of specific, local interactions (such as non-covalent bonds) among the basic structural units themselves, without external direction.

(27) In another aspect, a TFT is also provided. The TFT can comprise a substrate, and a semiconductor active layer disposed over the substrate. The semiconductor active layer comprises the semiconductor thin film according to any of the embodiments disclosed herein.

(28) As a result of adopting the semiconductor thin film described above as the semiconductor active layer, the TFT according to embodiments disclosed herein can have an improved reliability and stability compared with conventional TFTs.

(29) In the following, with reference to the drawings, a detailed description is provided for the TFT according to some specific implementations.

(30) It is noted that thicknesses, sizes, and shapes of the individual layers or components as shown in the drawings are for illustration purposes only, and do not necessarily reflect real dimensions.

(31) FIG. 1A illustrates a structural diagram of a TFT according to a first embodiment of the present disclosure. As shown, the TFT comprises, from bottom up, a substrate 10, a gate electrode 11, a gate electrode insulating layer 12, an n-type semiconductor layer 13, a self-assembly layer 14, a p-type semiconductor layer 15, a source electrode 16, and a drain electrode 17.

(32) As shown, the gate electrode 11 is disposed over the substrate 10; the gate electrode insulating layer 12 is disposed over the gate electrode 11; the n-type semiconductor layer 13 is disposed over the gate electrode insulating layer 12; the self-assembly layer 14 is disposed over the n-type semiconductor layer 13; the p-type semiconductor layer 15 is disposed over the self-assembly layer 14; and the source electrode 16 and the drain electrode 17 are disposed over the p-type semiconductor layer 15.

(33) FIG. 1B illustrates a structural diagram of a TFT according to a second embodiment of the present disclosure. The TFT comprises, from bottom up, a substrate 10, a gate electrode 11, a gate electrode insulating layer 12, an p-type semiconductor layer 15, a self-assembly layer 14, an n-type semiconductor layer 13, a source electrode 16, and a drain electrode 17.

(34) As shown, the gate electrode 11 is disposed over the substrate 10; the gate electrode insulating layer 12 is disposed over the gate electrode 11; the p-type semiconductor layer 15 is disposed over the gate electrode insulating layer 12; the self-assembly layer 14 is disposed over the p-type semiconductor layer 15; the n-type semiconductor layer 13 is disposed over the self-assembly layer 14; and the source electrode 16 and the drain electrode 17 are disposed over the n-type semiconductor layer 13.

(35) In some embodiments of the TFT, the n-type semiconductor layer 13 can comprise an inorganic oxide semiconductor material, such as indium oxide; the self-assembly layer 14 can comprise a phosphate ester material capable of self-assembly; and the p-type semiconductor layer 15 can comprise a p-type organic semiconductor material. The above mentioned combination of the compositions for each of the n-type semiconductor layer, the self-assembly layer, and the p-type semiconductor layer in the TFT as described above allows for fabrication of the TFT via solution processes, which in turn result in an improved property and performance of the TFT.

(36) In either the first embodiment or the second embodiment of the TFT described above, the substrate 10 can be glass, or can be a plastic. One of the gate electrode 11, the source electrode 16, or the drain electrode 17 can comprise a metal, a conductive adhesive such as a silver gel, or a conductive polymer such as PEDOT and carbon nanotubes. The gate electrode insulating layer 12 can comprise an organic insulating material such as PVP.

(37) In another aspect, an array substrate is provided. The array substrate comprises a plurality of TFTs according to any of the embodiments as described above.

(38) In another aspect, a display apparatus is provided. The display apparatus comprises the array substrate as described above.

(39) In another aspect, a method is provided for manufacturing a semiconductor thin film according to some of the embodiments as described above. The method can comprise the following steps:

(40) S201: providing a substrate;

(41) S202: forming an n-type semiconductor layer, a self-assembly layer, and a p-type semiconductor layer over the substrate via solution processes, wherein the n-type semiconductor layer and the p-type semiconductor layer are stacked over one another, the self-assembly layer is disposed between, and arranged to contact, the n-type semiconductor layer and the p-type semiconductor layer. The self-assembly layer comprises a material capable of self-assembly. In some embodiments, the material capable of self-assembly can be, for example, a phosphate ester.

(42) In the method for manufacturing a semiconductor thin film as described above, a set of solution processes can be applied. The solution processes can greatly simplify the manufacturing process of semiconductor thin films, and are especially useful for the fabrication of large-area and flexible electronic components.

(43) Specifically, the step of forming an n-type semiconductor layer, a p-type semiconductor layer, and a self-assembly layer over the substrate via a solution process (i.e., S202) can comprise the following sub-steps.

(44) In a first embodiment of the method, the step of S202 comprises:

(45) (1) forming the n-type semiconductor layer over the substrate via a first solution process;

(46) According to some embodiments of the present disclosure, a solution of indium chloride (InCl.sub.3) can be applied over the substrate by spin-coating, printing, or pulling to thereby form the n-type semiconductor layer.

(47) (2) forming the self-assembly layer over the n-type semiconductor layer via a second solution process;

(48) According to some embodiments of the present disclosure, the substrate having the n-type semiconductor layer disposed thereover can be submerged in an alcohol solution of a phosphate ester for a certain amount of time before taking out and cleansing to thereby form the self-assembly layer.

(49) (3) forming the p-type semiconductor layer over the self-assembly layer via a third solution process.

(50) According to some embodiments of the present disclosure, a solution containing a p-type semiconductor material can be applied over the self-assembly layer by spin-coating, printing, or pulling to thereby form the p-type semiconductor layer.

(51) In a second embodiment of the method, the step S202 comprises:

(52) (1) forming the p-type semiconductor layer over the substrate via a fourth solution process;

(53) According to some embodiments of the present disclosure, a solution containing a p-type semiconductor material can be applied over the substrate by spin-coating, printing, or pulling to thereby form the p-type semiconductor layer.

(54) (2) forming the self-assembly layer over the p-type semiconductor layer via a fifth solution process;

(55) According to some embodiments of the present disclosure, the substrate having the p-type semiconductor layer disposed thereover can be submerged in an alcohol solution of a phosphate ester for a certain amount of time before taking out and cleansing to thereby form the self-assembly layer.

(56) (3) forming the n-type semiconductor layer over the self-assembly layer via a sixth solution process;

(57) According to some embodiments of the present disclosure, a solution of indium chloride (InCl.sub.3) can be applied over the self-assembly layer by spin-coating, printing, or pulling to thereby form the n-type semiconductor layer.

(58) In another aspect, a method for manufacturing a TFT is provided.

(59) The method can comprise steps of forming a gate electrode, a semiconductor active layer, a source electrode, and a drain electrode, respectively, wherein the step of forming the semiconductor active layer are described above with respect to the fabrication of a semiconductor thin film.

(60) Although a method of fabricating a bottom-gate TFT is described as an illustrative example, other types of TFTs can be fabricated using methods similar to the embodiments disclosed herein.

(61) According to some embodiments of the present disclosure, the method for manufacturing a TFT can comprise: sequentially forming a gate electrode, a gate electrode insulating layer, a semiconductor active layer, a source electrode, and a drain electrode.

(62) The semiconductor active layer can be fabricated using the method for manufacturing the semiconductor thin film as described above.

(63) Specifically, as shown in FIG. 3A, the method for manufacturing the TFT can comprise the following steps:

(64) S301: forming a gate electrode and a gate electrode insulating layer sequentially over the substrate;

(65) S3011: forming an n-type semiconductor layer over the gate electrode insulating layer via a first solution process;

(66) S3012: forming a self-assembly layer over the n-type semiconductor layer via a second solution process;

(67) S3013: forming a p-type semiconductor layer over the self-assembly layer via a third solution process;

(68) S3014: forming a source electrode and a drain electrode over the p-type semiconductor layer.

(69) In the abovementioned method, the step of forming a gate electrode over the substrate (e.g., part of step S301) can comprise:

(70) (1) forming a conductive thin film over the substrate via a vapor deposition or a solution process; and

(71) (2) performing a first patterning process to the conductive thin film to thereby form the gate electrode.

(72) The substrate can be a glass substrate, or can be a plastic substrate. The sub-step of performing a first patterning process to the conductive thin film to thereby form the gate electrode can be a conventional method to form a gate electrode.

(73) In the above embodiments of the method, after the gate electrode is formed over the substrate, a gate electrode insulating layer can be further formed over the gate electrode (e.g., part of step S301), and the step can comprise: forming an inorganic insulating layer over the gate electrode by deposition, printing, or spin-coating.

(74) Herein the sub-step of forming the inorganic insulating layer over the gate electrode can reference to a conventional method for forming a gate electrode insulating layer over the gate electrode, and the description of the technical details of the sub-step is thus skipped.

(75) In the above embodiments of the method, the step of forming an n-type semiconductor layer over the gate electrode insulating layer via a first solution process (i.e., step S3011) can comprise:

(76) (1) forming an n-type semiconductor thin film over the gate electrode insulating layer, wherein a solution of indium chloride (InCl.sub.3) can be applied over the gate electrode insulating layer by spin-coating, printing, or pulling to thereby form the n-type semiconductor thin film;

(77) (2) performing a second patterning process to the n-type semiconductor thin film to thereby form the n-type semiconductor layer.

(78) The second patterning process can include any one or a combination of coating, exposure, development, etching, or removal of a photoresist. In the embodiments of the method as described above, the solution of indium chloride (InCl.sub.3) can undergo spin-coating, heating, UV exposure, and hydrolysis on the gate electrode insulating layer to thereby form the n-type semiconductor layer having a specific pattern.

(79) In the above embodiments of the method as described above, the step of forming the self-assembly layer over the n-type semiconductor layer via a second solution process (i.e., step S3012) can comprise:

(80) (1) submerging the substrate having the n-type semiconductor layer disposed thereover in an alcohol solution of a phosphate ester for a certain amount of time before taking out and cleansing to thereby form a self-assembly thin film over the n-type semiconductor layer; and

(81) (2) performing a third patterning process to the self-assembly thin film to thereby form the self-assembly layer.

(82) For example, in some embodiments of the method, the substrate having the n-type semiconductor layer disposed thereover can be submerged in the alcohol solution of the phosphate ester for 2 hours, and is then taken out for supersonic cleansing to thereby form a self-assembly thin film over the n-type semiconductor layer.

(83) It should be noted that in the above step, the self-assembly layer can be formed on the n-type semiconductor layer by other ways, for example, by spin-coating. There are no limitations herein.

(84) In the embodiments of the method as described above, the step of forming a p-type semiconductor layer over the self-assembly layer via a third solution process (i.e., step S3013) can comprise:

(85) (1) forming a p-type semiconductor thin film over the self-assembly layer by spin-coating, printing, or pulling; and

(86) (2) performing a fourth patterning process to the p-type semiconductor thin film to thereby obtain the p-type semiconductor layer.

(87) In the embodiments of the method as described above, the step of forming a source electrode and a drain electrode over the p-type semiconductor layer (i.e., step S3014) can comprise:

(88) (1) forming a conductive thin film over the p-type semiconductor layer via a vapor deposition or a solution process; and

(89) (2) performing a fifth patterning process to the conductive thin film to thereby form the source electrode and the drain electrode.

(90) In the above sub-steps, the fifth patterning process to form the source electrode and the drain electrode can reference to conventional approaches, and there are no limitations herein.

(91) According to some embodiments disclosure herein, a self-assembly layer is disposed between, and configured to contact, the n-type semiconductor layer and the p-type semiconductor layer, which can effectively solve the issue of a poor contact between the n-type semiconductor layer and the p-type semiconductor layer in a conventional bipolar thin-film transistor; and the poor contact between the n-type semiconductor layer and the p-type semiconductor layer can lead to a poor performance of the thin-film transistor.

(92) With the self-assembly layer formed over the n-type semiconductor layer, surface roughness can be reduced to thereby decrease a surface energy, which in turn can facilitate an orderly formation of the p-type semiconductor thin film. The higher degree of order the p-type semiconductor layer can lead to a higher hole mobility rate of the p-type semiconductor layer. The problems of degraded performances of conventional TFTs resulting from poor direct contact between the n-type and p-type semiconductor layers, particularly between inorganic semiconductor and organic semiconductor layers, can thus be solved.

(93) In the method for manufacturing a semiconductor thin film and/or a TFT as mentioned above, a solution process can be applied for each of the n-type semiconductor layer, the p-type semiconductor layer, and the self-assembly layer. The solution process can greatly simplify the manufacturing process of semiconductor thin films, and is especially appropriate for the fabrication of large-area and flexible electronic components.

(94) In addition, in some embodiments of the semiconductor thin film and/or the TFT as mentioned above, the n-type semiconductor layer comprises an inorganic oxide semiconductor material, the self-assembly layer comprises a phosphate ester self-assembly material, and the p-type semiconductor layer comprises a p-type organic semiconductor material. During manufacturing, specific processes can be carefully designed and adjusted so as to obtain a bipolar thin-film transistor with superior performance.

(95) In the following, with reference to some illustrative embodiments, a method for manufacturing a TFT via all-solution processes is described in detail.

(96) First, a conductive thin film can be formed on a substrate by printing a silver gel, PEDOT, and a conductive polymer such as carbon nanotubes thereover; then a sixth patterning process is performed to the conductive thin film to thereby form a gate electrode. It is noted that in some embodiments, other approaches for forming a gate electrode over the substrate can also be applied, such as by a solution process involving spin-coating plus a patterning process.

(97) Second, an organic insulating layer can be formed over the gate electrode by printing or spin-coating to thereby form a gate electrode insulating layer.

(98) Third, a solution of indium chloride (InCl.sub.3) can be applied over the gate electrode insulating layer by spin-coating, printing, or pulling to thereby form the n-type semiconductor thin film, which then undergoes a seventh patterning process to thereby form an n-type semiconductor layer.

(99) Fourth, the substrate having the n-type semiconductor layer disposed thereover can be submerged in an alcohol solution of a phosphate ester for a certain amount of time before taking out and cleansing to thereby form the self-assembly thin film, which then undergoes an eighth patterning process to obtain a self-assembly layer.

(100) Fifth, a p-type semiconductor thin film can be formed on the self-assembly layer by spin-coating, printing, or pulling, and then the p-type semiconductor thin film can undergo a ninth patterning process to thereby obtain a p-type semiconductor layer.

(101) Sixth, a conductive thin film can be formed over the p-type semiconductor layer by printing a silver gel, PEDOT, and a conductive polymer such as carbon nanotubes thereover; then a tenth patterning process is performed to the conductive thin film to thereby form a source electrode and a drain electrode.

(102) It is noted that according to some embodiments, other approaches for forming a source electrode and a drain electrode over the p-type semiconductor layer can also be applied, such as by a solution process involving spin-coating plus a patterning process.

(103) In the aforementioned embodiment of the method (i.e., the all-solution method), the temperature for each of the processes as described above can be below 230 C. Additionally, the method applies all-solution processes for the manufacturing of bipolar thin-film transistor, which can greatly simplify the manufacturing process, and then involve simpler manufacturing equipment.

(104) It is noted that the method as described above is illustrated with a bottom-gate TFT as an example, but the method can also be applied to a top-gate TFTs, or other types of thin-film transistor.

(105) FIG. 3B illustrates a method for manufacturing a TFT according to a second embodiment of the present disclosure. The method can comprise the following steps:

(106) S301: forming a gate electrode and a gate electrode insulating layer sequentially over the substrate;

(107) S3021: forming a p-type semiconductor layer over the gate electrode insulating layer via a fourth solution process;

(108) S3022: forming a self-assembly layer over the p-type semiconductor layer via a fifth solution process;

(109) S3023: forming an n-type semiconductor layer over the self-assembly layer via a sixth solution process;

(110) S3024: forming a source electrode and a drain electrode over the n-type semiconductor layer.

(111) The property and performance of the TFT as described above have been tested. The test results for the switching ratios of the TFT according to some embodiments are shown in FIG. 4A and FIG. 4B.

(112) In FIGS. 4A and 4B, W/L represents a ratio of a width and a length of a TFT; the horizontal coordinate V.sub.G represents a voltage on the gate electrode of the TFT, having a unit of volt (V); the vertical coordinate ID represents a current through the drain electrode, having a unit of amp (A). The testing results of the switching ratio of the n-type TFT is shown in FIG. 4A, and the testing results of the switching ratio of the p-type TFT is shown in FIG. 4B. As indicated by FIGS. 4A and 4B, both the n-type TFT and the p-type TFT have good switching ratios.

(113) The test results for the output performance of the TFTs according to some embodiments are shown in FIG. 5A and FIG. 5B. Specifically, FIG. 5A illustrates output I-V curves for n-type forward currents of a TFT according to some embodiments; and FIG. 5B illustrates output I-V curves for p-type reverse currents of a TFT according to some embodiments.

(114) In view of the above, various embodiments disclosed herein provide a semiconductor thin film, including an n-type semiconductor layer, a p-type semiconductor layer, and a self-assembly layer, wherein the n-type semiconductor layer and the p-type semiconductor layer are stacked over one another, and the self-assembly layer comprises a phosphate ester self-assembly material, and is disposed between, and configured to contact, the n-type semiconductor layer and the p-type semiconductor layer.

(115) Because of the stacked arrangement of the n-type semiconductor layer and the p-type semiconductor layer, the semiconductor thin film can be used as an active layer of a bipolar TFT. Additionally, during the manufacturing of the bipolar TFT, the n-type semiconductor layer and the p-type semiconductor layer can be separately fabricated. Compared with a conventional bipolar TFT having either a mixed configuration or a single semiconductor material, the TFTs disclosed herein can have improved reliability, stability, and performance.

(116) Furthermore, the arrangement of the self-assembly layer can effectively mediate a good contact between the n-type semiconductor layer and the p-type semiconductor layer, further leading to improved performance of the TFT.

(117) In some embodiments of the present disclosure, because of the compositions selected for each of the n-type semiconductor layer (e.g., an inorganic oxide semiconductor material, such as indium oxide), the self-assembly layer (e.g., a phosphate ester), and the p-type semiconductor layer (e.g., an organic p-type semiconductor material), during manufacturing of the TFT, a solution process can be employed for fabrication of each of the above layers. The solution process can greatly simplify the manufacturing process, and is especially useful for the fabrication of large-area and flexible electronic components.

(118) All references cited in the present disclosure, if any, are incorporated by reference in their entirety. Although specific embodiments have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects described above are not intended as required or essential elements unless explicitly stated otherwise.

(119) Various modifications of, and equivalent acts corresponding to, the disclosed aspects of the exemplary embodiments, in addition to those described above, can be made by a person of ordinary skill in the art, having the benefit of the present disclosure, without departing from the spirit and scope of the disclosure defined in the following claims, the scope of which is to be accorded the broadest interpretation so as to encompass such modifications and equivalent structures.