High common-mode transient immunity high voltage level shifter

Abstract

A high-voltage level shifter circuit that is capable of level shifting a signal from a low-voltage rail to a high-voltage rail for effective gate driving of a top power switch, with a short propagation delay and a high common-mode transient immunity (CMTI). The high CMTI high-voltage level shifter circuit can include a differential input and isolation stage, a high dv/dt sensor and cancellation stage, at least one differential and common-mode gain stage, and an output buffer stage.

Claims

1. A level shifter circuit configured to receive an input signal in a first voltage domain by a differential input circuit and shift the input signal to a second voltage domain, the circuit comprising: a cancellation stage configured to: sense a first common-mode current generated in response to a transition of a switching node from a first voltage level to a second voltage level, wherein the transition of the switching node is caused by a transition of the input signal; and generate a second common-mode current that, when combined with the first common-mode current, produce a reduced common-mode current; a gain stage coupled to the cancellation stage, wherein the gain stage is configured to receive both a differential-mode current and the reduced common-mode current during the transition of the switching node, wherein the gain stage has a common-mode current gain of less than one, and wherein the gain stage includes a pair of cross-coupled current mirror circuits; and an output stage configured to receive both the differential-mode current and the common-mode output current from the gain stage and generate a representation of the input signal shifted to the second voltage domain.

2. The level shifter circuit of claim 1, wherein the output stage includes a latch circuit configured to store the second logic state of the input signal.

3. The level shifter circuit of claim 1, wherein the gain stage has a differential-mode current gain of at least one.

4. The level shifter circuit of claim 1, wherein the gain stage is a first gain stage, wherein the common-mode current gain is a first common-mode current gain, the level shifter circuit further comprising: a second gain stage coupled to an output of the first gain stage, wherein the second gain stage has a second common-mode current gain of less than one.

5. The level shifter circuit of claim 4, wherein the first common-mode current gain is one-half, and wherein the second common-mode current gain is one-half.

6. The level shifter circuit of claim 4, wherein the first gain stage includes a first common-mode gain stage and first differential-mode gain stage, and the second gain stage includes a second common-mode gain stage and second differential-mode gain stage.

7. The level shifter circuit of claim 1, wherein the gain stage is a first gain stage of a number of N gain stages, wherein individual ones of the N gain stages have corresponding common-mode current gains of less than one.

8. The level shifter circuit of claim 7, wherein the common-mode gain of at least one of the N gain stages is 1/2.sup.N.

9. The level shifter circuit of claim 8, wherein the differential-mode current gain is at least one.

10. The level shifter circuit of claim 1, further comprising: a pulse generator circuit coupled to the differential input circuit to reduce a propagation delay of the level shifter circuit.

11. A method of shifting an input signal in a first voltage domain to a second voltage domain, the method comprising: sensing a first common-mode current generated in response to a transition of a switching node from a first voltage level to a second voltage level, wherein the transition of the switching node is caused by a transition of the input signal and generating a replica common-mode current; receiving the replica common-mode current and combining with the first common-mode current to produce a reduced common-mode current to a gain stage, wherein the gain stage includes a pair of cross-coupled current mirror circuits; receiving, by the gain stage, both a differential-mode current and the reduced common-mode current during the transition of the switching node and generating a gain stage common-mode output current, wherein the gain stage has a common-mode current gain of less than one; and generating a representation of the input signal shifted to the second voltage domain.

12. The method of claim 11, further comprising: storing the second logic state the of input signal.

13. The method of claim 11, further comprising: generating a gain stage differential output current, wherein the gain stage has a differential current gain of at least one.

14. The method of claim 11, wherein the gain stage is a first gain stage, wherein the gain stage common-mode output current is a first gain stage common-mode output current, and wherein the common-mode current gain is a first common-mode current gain, the method further comprising: receiving, by a second gain stage, the first gain stage common-mode output current and generating a second gain stage common-mode output current, wherein the second gain stage has a second common-mode current gain of less than one.

15. The method of claim 14, wherein the first common-mode current gain is one-half, and wherein the second common-mode current gain is one-half.

16. The method of claim 11, further comprising: generating a pulse to increase a tail current to reduce a propagation delay of the level shifter circuit.

17. A level shifter circuit configured to receive an input signal in a first voltage domain by a differential input circuit and shift the input signal to a second voltage domain, the circuit comprising: means for sensing a first common-mode current generated in response to a transition of a switching node from a first voltage level to a second voltage level and generating a replica common-mode current; means for receiving the replica common-mode current and combining with the first common-mode current to produce a reduced common-mode current to a gain stage; means for receiving, by the gain stage, both a differential-mode current and the reduced common-mode current during the transition of the switching node and generating a gain stage common-mode output current, wherein the gain stage has a common-mode current gain of less than one, and wherein the gain stage includes a pair of cross-coupled current mirror circuits; and an output stage configured to receive both the differential-mode current and the common-mode output current from the gain stage and generate a representation of the input signal shifted to the second voltage domain.

18. The level shifter circuit of claim 17, wherein the output stage includes a latch circuit configured to store the second logic state the of input signal.

19. The level shifter circuit of claim 17, wherein the gain stage has a differential-mode current gain of at least one.

20. The level shifter circuit of claim 17, wherein the gain stage is a first gain stage, wherein the common-mode current gain is a first common-mode current gain, the level shifter circuit further comprising: a second gain stage coupled to an output of the first gain stage, wherein the second gain stage has a second common-mode current gain of less than one.

21. The level shifter circuit of claim 20, wherein the first common-mode current gain is one-half, and wherein the second common-mode current gain is one-half.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

(2) FIG. 1 is a schematic diagram of an example of system level circuit that includes a level shifter circuit.

(3) FIG. 2 is a simplified schematic diagram of an example of a mirror-based high-voltage level shifter circuit.

(4) FIG. 3 is a simplified schematic diagram of another example of a mirror-based high-voltage level shifter circuit.

(5) FIG. 4 is a simplified schematic diagram of an example of a latch-based high-voltage level shifter circuit.

(6) FIG. 5 is a schematic diagram of an example of a high-voltage level shifter circuit using various techniques of this disclosure.

(7) FIG. 6 is a schematic diagram of a portion of the circuit of FIG. 6 illustrating the rejection of the common-mode signal while effectively transmitting the differential signal.

DETAILED DESCRIPTION

(8) This disclosure describes a high-voltage level shifter circuit that is capable of level shifting a signal from a low-voltage rail to a high-voltage rail for effective gate driving of a top power switch, with a short propagation delay and a high common-mode transient immunity (CMTI). The high CMTI high-voltage level shifter circuit can include a differential input and isolation stage, e.g., high-voltage laterally-diffused metal-oxide semiconductor (LDMOS), a high dv/dt sensor and cancellation stage, at least one differential and common-mode gain stage, and an output buffer stage.

(9) The high dv/dt sensor and cancellation stage can use a transistor identical to the transistor of the differential-input stage, e.g., LDMOS, to detect a dv/dt transient at a switching node and feedback the transient signal to reject the common-mode transient current at the two main level shifting differential paths and reduce common-mode gain.

(10) Furthermore, the entire differential and common-mode gain stage as a whole can achieve unity differential gain, but less than one common-mode gain, e.g., one half. With a number N stages, the differential gain can remain at one while the common-mode gain becomes 1/2.sup.N. After the one or more gain stages, a signal can be shifted to a high-voltage rail, and a latch can store the logic state of the transition of the input signal from a first logic state, e.g., high, to a second logic state, e.g., low. The level-shifter circuit can achieve up to 100V/0.1 nanosecond (ns) (or 1 KV/ns equivalently) CMTI, nanosecond-level propagation delay and nearly-zero quiescent current at steady state for efficient and reliable gate driving, which makes it suited for gallium nitride (GaN) based switching power converter applications.

(11) FIG. 1 is a schematic diagram of an example of a system level circuit that includes a level shifter circuit. The system circuit 100 can include a top switch M r coupled to a top switch gate driver circuit 102 and a bottom switch M.sub.B coupled to a bottom switch gate driver circuit 104. The system circuit 100 can receive an input signal at the input IN at a first voltage domain, e.g., 0V (low) to 5V (high) and shift the signal, using the level shifter circuit 108, to a second voltage domain, e.g., 100V (low) to 105V (high), that includes the switching rail V.sub.SW and the boot-strap rail V.sub.BST.

(12) When the bottom switch M.sub.B is turned ON by the bottom switch gate driver circuit 104, the V.sub.SW voltage level is close to ground, and a bootstrap charging circuit 106 can charge the bootstrap capacitor C.sub.BST to maintain a constant voltage across V.sub.BST and V.sub.SW. When the input signal changes from low to high, the signal can be transmitted by the level shifter circuit 108 and applied to the top switch gate driver circuit 102 to drive the top switch M.sub.T e.g., silicon field-effect transistor (FET).

(13) As the input signal goes from low to high, the top gate node TG goes from low-to-high to turn ON the top switch M.sub.T, and V.sub.SW rises at a high dv/dt rate. If using a gallium nitride FET (which shows much lower parasitic capacitances) as the top and bottom switches (M.sub.T and M.sub.B), an even higher dv/dt occurs at V.sub.SW, which can false trigger the level shifter and cause a wrong state at nodes OUT and TG. With a false trigger, the top switch M.sub.T could be on-off-on, with many incorrect output states, which can cause further failures of the power system.

(14) FIG. 2 is a simplified schematic diagram of an example of a mirror-based high-voltage level shifter circuit. The circuit 10 can include a low-voltage metal-oxide-semiconductor (MOS) differential input section 12 that can include first and second inverter circuits 14, 16 and first and second transistors 18, 20. A current source 21 generating a current I.sub.S can be coupled to the first and second transistors 18, 20 and can provide a tail current. The circuit 10 can further include a high-voltage double-diffused MOS (DMOS) section 22 including transistors M.sub.DN1 and M.sub.DN2, which can be coupled to the first and second transistors 18, 20, respectively. Three current mirrors are shown at 24-28. The low voltage MOS section 12 can receive an input signal at the input IN at a first voltage domain, e.g., 0V (low) to 5V (high), and shift the signal to a second voltage domain, e.g., 100V (low) to 105V (high), that includes the switching rail V.sub.SW and the boot-strap rail V.sub.BST.

(15) In the example of FIG. 2, the high-voltage DMOS transistors M.sub.DN1 and M.sub.DN2 can provide high-voltage isolation, while the differential input structure supports a low dv/dt immunity. Under high dv/dt transients at rail V.sub.SW, the parasitic capacitances C.sub.PAR1, C.sub.PAR2 can trigger high dv/dt current I.sub.DVDT at the two respective paths shown. Due to a mismatch of the parasitic capacitances and current mirrors, the high dv/dt current I.sub.DVDT can cause a false trigger of the output signal at OUT. In addition, the level shifter circuit 10 can consume a static current of I.sub.S.

(16) FIG. 3 is a simplified schematic diagram of another example of a mirror-based high-voltage level shifter circuit. The circuit 30 of FIG. 3 can include at least some components that are similar to those shown in FIG. 3, which for purposes of conciseness, will not be described in detail again.

(17) The circuit 30 can include a pulse generator circuit 32 coupled to the differential input circuit and configured to reduce a propagation delay of the level shifter circuit. To reduce the propagation delay of the level shifter circuit, the pulse generator circuit can generate a pulse, e.g., 2-6 ns pulse, that can dramatically increase the tail current for a high slew rate during signal transition. In this manner, the parasitic capacitances C.sub.PAR1, C.sub.PAR2 (shown in FIG. 2) can be quickly charged or discharged. However, the rail V.sub.SW can ring after pulse expires and the dv/dt immunity can remain low, similar to the circuit 10 in FIG. 2. In addition, the level shifter circuit 30 can consume a static current of I.sub.S.

(18) FIG. 4 is a simplified schematic diagram of an example of a latch-based high-voltage level shifter circuit. The circuit 40 can include a differential input section 42 that can include first and second inverter circuits 44, 46 and first and second transistors M.sub.N1, M.sub.N2. The circuit 40 can further include transistors M.sub.D1 and M.sub.D2, which can be coupled to the first and second transistors M.sub.N1, M.sub.N2. The six transistors M.sub.N3, M.sub.N4, and M.sub.D3-M.sub.D6 can form a latch.

(19) The level shift circuit 40 of FIG. 4 can consume nearly zero static current in steady state. However, it can include six or more high-voltage DMOS transistors (M.sub.D1-M.sub.D6) and can have a large footprint, especially at voltages of 100V or higher. On the other hand, during high dv/dt transition at rail V.sub.SW, the parasitic capacitance C.sub.PAR1, C.sub.PAR2 at the drains of M.sub.D1 and M.sub.D2 can trigger two respective high dv/dt currents. These dv/dt currents can reset the state of the latch, which can lead to a false-trigger of output state. To provide high dv/dt immunity, the latch device sizes (including transistors M.sub.N3, M.sub.N4, and M.sub.D3-M.sub.D6) can be large to increase the strength of the latch. However, it can take a large die size and a high instant current to transmit the level-shifting signals, leading to a long propagation delay.

(20) To address the challenges described above, this disclosure describes a high common-mode transient immunity (CMTI) high voltage level shifter circuit that is capable of level shifting a signal from a low-voltage rail to a high-voltage rail under a high common mode transient (dv/dt) at rail V.sub.SW, and with sub-nanosecond propagation delay.

(21) FIG. 5 is a schematic diagram of an example of a high-voltage level shifter circuit using various techniques of this disclosure. The level shifter circuit 50 of FIG. 5 can include a differential input and isolation stage 52, e.g., high-voltage LDMOS-based, a pulse generator circuit 54 for slew rate enhancement, a dv/dt sensor and cancellation stage circuit 56, a first gain stage circuit 58, e.g., transistor-based, coupled to the dv/dt sensor and cancellation stage circuit 56, a second gain stage circuit 60, e.g., transistor-based, coupled to the first gain stage circuit 58, and an output buffer stage circuit 62.

(22) In some example configurations, the first gain stage circuit 58 can include P-type (or N-type) field-effect transistors (FETs) and the second gain stage circuit 60 can include N-type (or P-type) FETs. As described below in more detail with respect to FIG. 6, in some examples, the first gain stage circuit 58 can include a first common-mode gain stage and a first differential-mode gain stage, which can handle the common-mode current and differential-mode current differently. Similarly, in some examples, the second gain stage circuit 60 can include a second common-mode gain stage and second differential-mode gain stage.

(23) The dv/dt sensor and cancellation stage circuit 56 can be configured to reduce a common-mode current generated by a transition of the input signal from a first logic state, e.g., low, to a second logic state, e.g., high. The dv/dt sensor and cancellation stage circuit 56 can include a dummy transistor 64, e.g., LDMOS, that is the same size as the transistors 66, 68 of the differential input and isolation stage 52. An input signal can be received at node SIN and a corresponding level-shifted output signal can be output at node SOUT.

(24) During an input signal transition from a first logic state to a second logic stage, a pulse, e.g., a 2-ns pulse, can be generated at the gate terminal of the transistor 70, e.g., NMOS transistor, that is coupled to the source terminals of the transistors 66, 68 of the input and isolation stage circuit 52. The pulse can generate a high tail current to transmit the differential-mode signal effectively and with a short propagation delay.

(25) During a high dv/dt transient on the bootstrap (BOOT) and switch (SW) rails, a high dv/dt common-mode current can be generated through the drain path of the transistors 66, 68, e.g., LDMOS-based transistors, of the differential input and isolation stage 52. The dv/dt sensor and cancellation stage circuit 56 can include a high-voltage transistor 64, which is the same size as the transistors 66, 68 of the two main level shifting differential paths and will have a similar parasitic capacitance at its drain terminal. The dv/dt sensor and cancellation stage circuit 56 can sense a common-mode current generated by a transition of the input signal from a first logic state to a second logic state and generate a replica common-mode current.

(26) During a dv/dt transient, where the bootstrap (BOOT) and switch (SW) rails go high, the parasitic capacitance C.sub.PAR1, C.sub.PAR2 associated with the drain terminal of the transistor 64 will charge up via a current through node FLY_REF, which can be considered a replica common-mode current. The replica common-mode current through the transistor 64 can be mirrored by the current mirror formed by the transistors 72, 74. The transistors 72, 74 are coupled to nodes FLYP and FLYN, respectively, and those nodes receive the replica common-mode current and reduce the common-mode current to the gain stage 58. The current fed into nodes FLYP and FLYN by the dv/dt sensor and cancellation stage circuit 56 charges up the parasitic capacitances C.sub.PAR1, C.sub.PAR2 associated with the drain terminals of the transistors 66, 68. Charging up the parasitic capacitances can reduce (or cancel) the common-mode current through the transistors 66, 68, which can reduce (or cancel) the common-mode current in the gain stage circuit 58.

(27) In this manner, by using the dv/dt sensor and cancellation stage circuit 56, which has transistor 64 sized the same as the transistors 66, 68 of the differential input and isolation stage 52, the same amount of dv/dt current can be generated by the dv/dt sensor and cancellation stage circuit 56 and fed to the two main level shifting differential paths and reduce or cancel the dv/dt triggered common-mode current.

(28) However, due to potential mismatches and delays of the current mirrors of the gain stages, the dv/dt triggered current may not be fully cancelled. A gain stage, such as the first gain stage 58 (and the second gain stage 60 and more, if present) can play an important role in rejecting the common-mode signal while effectively transmitting the differential signal. The gain stage 58 can be coupled to the cancellation stage 56 and can be configured to receive a reduced common-mode current from the cancellation stage and a differential-mode current. The gain stage 58 can have a common-mode current gain of less than one. In some examples, the differential current gain through the first gain stage 58 and the second gain stage can be at least one.

(29) The output stage circuit 62 can be configured to receive both the differential-mode current and the common-mode output current from the gain stage and generate a representation of the input signal shifted to the second voltage domain. In some examples, the output stage can include a latch circuit configured to store the second logic state of the input signal to reflect the input state, e.g., after the input signal transitions from a first logic state to a second logic state.

(30) In the example configuration shown in FIG. 5, the first and second gains stages can include cross-coupled mirror circuits with a 1:1:1 ratio in each branch. Due to the cross-coupled structure with 1:1:1 ratio in each branch, the common-mode current gain can become one-half after the first gain stage 58 and can be further reduced to one-quarter after the second gain stage 68, as shown in FIG. 6. The configuration shown in FIG. 5 is a non-limiting example configuration. In other configurations, the current gain of the first stage 58 can be greater than or less than one-half, and the current gain of the second stage 60 can be greater than or less than one-half.

(31) FIG. 6 is a schematic diagram of a portion of the circuit of FIG. 5 illustrating the rejection of the common-mode signal while effectively transmitting the differential signal. As seen in FIG. 6, the common-mode current I.sub.CM through node FLYN (left-hand side of FIG. 6) is formed from the sum of the common-mode current I.sub.CM/2 through transistor 76 and the common-mode current I.sub.CM/2 through path 82 via the current mirror formed by transistor 78. Similarly, the common-mode current I.sub.CM through node FLYP (right-hand side of FIG. 6) is formed from the sum of the common-mode current I.sub.CM/2 through transistor 84 and the common-mode current I.sub.CM/2 through path 86 via the current mirror formed by transistor 90.

(32) The cross-coupled mirror circuits with 1:1:1 ratio in the left-hand branch of the first gain stage circuit (shown at 58 in FIG. 5) can generate a common-mode current of I.sub.CM/2 through the current mirror formed by transistors 88, 90. The cross-coupled structure with 1:1:1 ratio in the second gain stage circuit (shown at 60 in FIG. 5) can further reduce the common-mode current. In particular, the common-mode current of I.sub.CM/2 splits between the left-hand branch and the right-hand branch of the second gain stage circuit, resulting in a common-mode current of I.sub.CM/4 through each branch. In this manner, the common-mode current can be halved, for example, after each cross-coupled stage, from I.sub.CM to I.sub.CM/2 to I.sub.CM/4, for the non-limiting example configuration shown in FIGS. 4 and 5. In other examples, the common-mode current gain of the first gain stage or the second gain stage can be greater than or less than one-half.

(33) As seen in FIG. 6, the differential signal is OA through the node FLYN (left-hand side) and I.sub.DM through the node FLYP (right-hand side). Because there is no differential-mode current through the transistor 76 (left-hand side of FIG. 6), there is no differential-mode current flowing through the current mirror formed by transistors 88, 90 and thus no cancellation of the differential-mode current DM via cross-coupling in the way that the common-mode current was canceled. Instead, the differential-mode current I.sub.DM through the transistor 84 can be mirrored in a 1:1:1 ratio with the current mirror formed by transistors 78, 80 and outputted to the second gain stage circuit (shown at 60 in FIG. 5) with a gain of one or more, for example. The second gain stage circuit can receive the differential-mode signal I.sub.DM via the current mirror formed by the transistors 92, 94 and output a differential-mode signal with a gain of at least one, for example.

(34) For the differential signal I.sub.DM, the differential gain of the circuit shown in FIGS. 4 and 5 can be one (or more) because the differential current I.sub.DM (the input signal) is fully mirrored without degrading. The pull-up and pull-down capability are both I.sub.DM at the last stage, which can fully transmit the input signal transitions.

(35) By way of a non-limiting specific example, the differential-mode input current can be 2 mA, while the dv/dt common-mode current under 100V/ns can be about 6 mA (depending on the size of transistor and its parasitic capacitance). After dv/dt cancellation, the remaining dv/dt triggered common-mode current can be about 1 mA. After that, the remaining common-mode current of 1 mA can be further reduced to 0.25 mA after two differential-mode and common-mode gain stages, as described above.

(36) Advantageously, however, the differential-mode current can remain unchanged at 2 mA, which can help to effectively level-shift the signals and prevent false triggers. The common-mode current can be reduced to nearly zero in last stage (the cross-coupled stage 96 after the second gain stage), while the unity-gain differential-mode current can trigger the latch to transmit the input signal to the output. In this way, the input signal in the low-voltage rail can be effectively shifted to the high-voltage rails, while the high dv/dt common-mode transient is substantially rejected. Moreover, nearly zero static current is needed in steady state to save power.

(37) Moreover, to achieve even high dv/dt transient up to 100/0. Ins or 1 KV/ns, additional gain stages can be constructed to further reduce the common-mode current gain to 1/2.sup.N, where N is the stage number. However, additional stages can result in additional propagation delay.

(38) The high CMTI high-voltage level shifter circuit described above disclosure has several advantages. With the cross-coupled structure, the overall differential gain of the input signal is 1, while the common mode gain is 1/2.sup.N, where N is the number of gain stages. The techniques described can help to effectively transmit a signal from a low-voltage domain to a high-voltage domain with short propagation delay and reject the high dv/dt transient of the common-mode signal.

(39) In some example configurations, the high dv/dt sensor and cancellation circuit (shown at 56 in FIG. 5) can use a transistor identical to the input differential input transistor to detect a dv/dt transient at the switching node and feedback the transient to reject the common-mode transient current at the two main level shifting differential paths and reduce common-mode gain.

(40) In addition, the input low-voltage signal can be shifted to high-voltage rail, further triggering the latch circuit (shown at 62 in FIG. 5) to store the state. It can achieve 100V/0.1 ns CMTI (or more) and can achieve nanosecond-level propagation delay, and consume zero quiescent current in steady state.

NOTES

(41) Each of the non-limiting aspects or examples described herein may stand on its own or may be combined in various permutations or combinations with one or more of the other examples.

(42) The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as examples. Such examples may include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

(43) In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.

(44) In this document, the terms a or an are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of at least one or one or more. In this document, the term or is used to refer to a nonexclusive or, such that A or B includes A but not B, B but not A, and A and B, unless otherwise indicated. In this document, the terms including and in which are used as the plain-English equivalents of the respective terms comprising and wherein. Also, in the following claims, the terms including and comprising are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms first, second, and third, etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

(45) Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

(46) The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.