Nano power under-voltage lockout circuits (UVLO) using flipped-gate MOS

Abstract

An under-voltage lockout (UVLO) circuit configured for indicating that an electronic device may be enabled and disabled based on threshold levels of a power supply voltage. The UVLO circuit has a non-differential comparator configured to have a fixed threshold voltage. A voltage divider having a first terminal connected to the power supply voltage and configured to adapt a compare signal applied to the non-differential comparator to be proportional the power supply voltage such that a desired threshold voltage for the power supply voltage causes the non-differential comparator to change its output state. The UVLO circuit has a hysteresis controller configured for adjusting the compare voltage such that the power supply voltage has at least two threshold voltages to cause the non-differential comparator to change states. The non-differential comparator comprises a flipped gate transistor with a gate-to-source threshold greater than a normally gated transistor.

Claims

1. A comparison circuit is configured for receiving a first input voltage and a second input voltage and configured for comparing the first input voltage with the second input voltage and determining if a first input voltage is greater than or lesser than a threshold voltage between the first input voltage and the second input voltage, the comparison circuit comprising: a non-differential comparator configured for having a fixed threshold voltage at an input such that when a signal developed from the first and second input voltages is greater than the fixed threshold voltage, an output of the non-differential comparator is placed at a first voltage level and when the signal developed from the first and second input voltages is less than the fixed threshold voltage, an output of the non-differential comparator is placed at a second voltage level wherein the first and second voltage levels form a comparison output signal; wherein a flipped gate transistor is configured such that a gate-to-source threshold voltage is fixed threshold voltage; and a voltage divider having a first terminal connected to receive the first input voltage and a second terminal connected to receive the second input voltage and configured for dividing a difference in the first input voltage and the second input voltage such that a compare voltage is applied to the input of the non-differential comparator for comparison with the fixed threshold voltage.

2. The comparison circuit of claim 1 wherein the non-differential comparator comprises: the flipped gate transistor comprising: a gate configured to receive the signal developed from the first and second input voltages, a source connected to a reference terminal of a power supply voltage, a drain configured for providing the first and second voltage levels at the output of the comparison circuit; and a reference current source having a first terminal connected to the drain of the flipped gate transistor and a second terminal connected to a power terminal of the power supply voltage and configured for providing a reference current for the flipped gate transistor for developing the first and second voltage levels.

3. The comparison circuit of claim 2 wherein the voltage divider comprises: a first resistor with a first terminal connected for receiving the first input voltage, and a second terminal connected to a gate of the flipped gate transistor; a voltage to current converter connected to the junction of the connection between the second terminal of the first resistor and the gate of the flipped gate transistor, and configured for providing a conversion current that is proportional to an amplitude of the second input voltage; wherein, the resistance of the first resistor, an amplitude of the first input voltage, an amplitude of the second input voltage determine the compare voltage applied to the gate of the flipped gate transistor for determining a voltage difference at which the flipped gate transistor will change from the first input voltage level to the second voltage level.

4. The comparison circuit of claim 3 wherein the voltage to current converter comprises: a normally gated transistor comprising: a drain connected to the gate of the flipped gate transistor and the second terminal of the first resistor, a gate connected to receive the second input voltage, and a source; and a second resistor having a first terminal connected to the source of the normally gated transistor and a second terminal connected to receive a ground reference voltage.

5. The comparison circuit of claim 4 further comprising: an inverter buffer having an input connected to the output of the non-differential comparator and an output connected to circuitry of an electronic device, and configured for receiving the first voltage level and the second voltage level from the non-differential comparator for inverting and buffering the comparison output signal.

6. The comparison circuit of claim 5 wherein the inverter buffer comprises: a transistor of a first conductivity type comprising: a source connected to the power supply voltage, a drain connected to the external circuitry, and a gate connected to the output of the non-differential comparator; and a transistor of a second conductivity type comprising: a source connected to the ground reference voltage, a drain connected to the drain of the transistor of the first conductivity and to the external circuitry, and a gate connected to the output of the non-differential comparator and to the gate of the transistor of the first conductivity.

7. The comparison circuit of claim 4 wherein the current flowing through the second resistor flows through the first resistor to establish the compare voltage at the gate of the flipped gate transistor, wherein the first resistor and the second resistor are approximately equal.

8. The comparison circuit of claim 4 wherein when the compare voltage at the gate of the flipped gate transistor is greater than the threshold voltage of the flipped gate transistor, the first input voltage and the second input voltage are at a voltage difference that the compare voltage will turn on the flipped gate transistor and the input to the inverter buffer becomes approximately the voltage level of the ground reference voltage and the output of the inverter buffer becomes activated to the second logical state.

9. The comparison circuit of claim 4 wherein when the compare voltage at the gate of the flipped gate transistor becomes less than the threshold voltage of the flipped gate transistor, the first input voltage and the second input voltage are at a voltage difference that the compare voltage will turn off the flipped gate transistor and the input to the inverter buffer becomes approximately the voltage level of the power supply voltage and the output of the inverter buffer becomes deactivated to a first logical state.

10. The comparison circuit of claim 3 further comprising a hysteresis controller configured for adjusting the compare voltage such that if the first input voltage is less than the second input voltage, the voltage difference between the first input voltage and the second input is at a first input voltage level to make the compare voltage at the voltage level of the fixed threshold voltage and configured for adjusting the compare voltage such that if the first input voltage is greater than the second input voltage, the voltage difference between the first input voltage and the second input is at a second voltage level to make the compare voltage at the voltage level of the fixed threshold voltage to establish hysteresis between the first input voltage level and the second voltage level.

11. The comparison circuit of claim 10 wherein a hysteresis controller comprises: a third resistor that is placed between the second resistor and the power supply voltage such that a first terminal of the third resistor is connected to the power supply voltage and a second terminal of the third resistor is connected to the first terminal of the second resistor; a hysteresis control transistor comprising: a source connected to the power supply voltage, a drain connected to the junction of the connection between the third resistor and the second resistor, and a gate of the hysteresis control transistor connected to the junction of the reference current source and the drain of the flipped gate transistor, wherein when the flipped gate transistor is turned off, indicating that the first input voltage is less than the second input voltage, the hysteresis control transistor is also turned off and the first input voltage and the second input voltage are at a voltage difference for indicating that the first input voltage is less than the second input voltage and the output of the inverter buffer is set to the first logical state, wherein when the flipped gate transistor is turned on, the hysteresis control transistor is also turned on, effectively shorting out the third resistor for changing the threshold and the first input voltage and the second input voltage are at a voltage difference for indicating that the first input voltage is greater than the second input voltage and the output of the inverter buffer is set to the second logical state.

12. An under-voltage lockout (UVLO) circuit configured for enabling and disabling an electronic device, if a power supply voltage is at a voltage level that permits the operation of the electronic devices, wherein the UVLO circuit comprises: a non-differential comparator configured to have a fixed threshold voltage at an input such that when a signal developed from the power supply voltage and a reference voltage is greater than the fixed threshold voltage, an output of the non-differential comparator is placed at a first voltage level and when the signal developed from the power supply voltage and the reference voltage is less than the fixed threshold voltage, an output of the non-differential comparator is placed at a second voltage level, wherein the first and second voltage levels define a comparison output signal; a voltage divider having a first terminal connected to the power supply voltage and a second terminal connected to receive the reference voltage and configured for dividing a difference in the power supply voltage and the reference voltage such that a compare voltage is applied to the input of the non-differential comparator for comparison with the fixed threshold voltage; and a hysteresis controller configured for adjusting the compare voltage such that if the power supply voltage is less than a falling threshold voltage, the voltage difference between the power supply voltage and the reference voltage is at a first voltage level to make the compare voltage at the voltage level of the fixed threshold voltage and configured for adjusting the compare voltage such that if the power supply voltage is greater than a rising voltage, to make the compare voltage at the voltage level of the fixed threshold voltage to establish hysteresis between the first voltage level and the second voltage level.

13. The UVLO circuit of claim 12 wherein the non-differential comparator comprises: a flipped gate transistor comprising: a gate configured to receive the signal developed from the power supply voltage and the reference voltage, a source connected to a ground reference voltage, a drain configured for providing the first and second voltage levels at the output of the comparison circuit; and wherein the flipped gate transistor is configured such that a gate-to-source threshold voltage is the fixed threshold voltage; and a reference current source having a first terminal connected to the drain of the flipped gate transistor and a second terminal connected to a power terminal of the power supply voltage and configured for providing a reference current for the flipped gate transistor for developing the first and second voltage levels.

14. The UVLO circuit of claim 12 wherein the voltage divider comprises: a first resistor with a first terminal connected to receive the power supply voltage and a second terminal; a second resistor with a first terminal connected to the second terminal of the first resistor and a second terminal connected to a gate of the flipped gate transistor; a voltage to current converter connected for receiving the reference voltage, connected to the junction of the connection between the second terminal of the second resistor and the gate of the flipped gate transistor, and configured for providing a conversion current to the first and second resistors that is proportional to an amplitude of the reference voltage; wherein, the resistance of the first and second resistors, an amplitude of the power supply voltage, an amplitude of the reference voltage determine the compare voltage applied to the gate of the flipped gate transistor for determining a voltage difference at which the flipped gate transistor will change from the level of the power supply voltage to the level of the reference voltage.

15. The UVLO circuit of claim 14 the voltage to current converter comprises: a normally gated transistor comprising: a drain connected to the gate of the flipped gate transistor and the second terminal of the first resistor, a gate connected to reference voltage, and a source; and a third resistor having a first terminal connected to the source of the normally gated transistor and a second terminal connected to the ground reference voltage.

16. The UVLO circuit of claim 14 further comprising: an inverter buffer having an input connected to the output of the non-differential comparator and an output connected to circuitry of an electronic device, and configured for receiving the first voltage level and the second voltage level from the non-differential comparator for inverting and buffering the comparison output signal to create the output signal of the UVLO circuit for transfer to the external circuitry indicating that the electronic device is turned on or turned off.

17. The UVLO circuit of claim 16 wherein the inverter buffer comprises: an inverter has a transistor of the first conductivity comprising: a source connected to the power supply voltage, a drain connected to the external circuitry, and a gate connected to the output of the non-differential comparator; and a transistor of the second conductivity, a source connected to the ground reference voltage, a drain connected to the drain of the transistor of the first conductivity and to the external circuitry, and a gate connected to the output of the non-differential comparator and to the gate of the transistor of the first conductivity.

18. The UVLO circuit of claim 15 wherein the current flowing through the third resistor flows through the first and second resistors to establish the compare voltage at the gate of the flipped gate transistor.

19. The UVLO circuit of claim 15 wherein when the compare voltage at the gate of the flipped gate transistor is greater than the gate to source threshold voltage of the flipped gate transistor, the power supply voltage the rising threshold voltage such that the compare voltage will turn on the flipped gate transistor and the input to the inverter buffer becomes approximately the voltage level of the ground reference voltage and the output of the inverter buffer becomes activated to the second logical state.

20. The UVLO circuit of claim 15 wherein when the compare voltage at the gate of the flipped gate transistor becomes is less than the gate to source threshold voltage of the flipped gate transistor, the power supply voltage is less than the falling threshold voltage such that the compare voltage will turn off the flipped gate transistor and the input to the inverter buffer becomes approximately the voltage level of the power supply voltage and the output of the inverter buffer becomes deactivated to a first logical state.

21. The UVLO circuit of claim 12 wherein the hysteresis controller comprises: the third resistor that is placed between the second resistor and the power supply voltage; a hysteresis control transistor comprising: a source connected to the power supply voltage, a drain connected to the junction of the connection between the third resistor and the second resistor, and a gate of the hysteresis control transistor connected to the junction of the reference current source and the drain of the flipped gate transistor, wherein when the flipped gate transistor is turned off, the hysteresis control transistor is also turned off and the power supply voltage has the falling threshold voltage, wherein when the flipped gate transistor is turned on, the hysteresis control transistor is also turned on, effectively shorting out the third resistor for changing the power supply voltage to have the rising threshold.

22. The UVLO circuit of claim 14 wherein when the compare voltage at the gate of the flipped gate transistor is greater than the gate to source threshold voltage of the flipped gate transistor, the amplitude of the power supply voltage is greater than the rising threshold and the flipped gate transistor turns on such that the comparison output signal is at the voltage level of the ground reference voltage and the output of the inverter buffer becomes activated to the second logical state, and the electrical device is activated to be fully functional.

23. The UVLO circuit of claim 14 wherein when the compare voltage at the gate of the flipped gate transistor becomes is less than the threshold voltage of the flipped gate transistor, the voltage level of the power supply voltage is less than the falling threshold voltage and the flipped gate transistor turns off such that the comparison output signal becomes approximately the voltage level of the power supply voltage and the output of the inverter buffer becomes deactivated to the first logical state, and the electrical device is deactivated to be turned off.

24. The UVLO circuit of claim 14 wherein the second resistor comprises by a plurality of serially connected resistors, wherein a first terminal of a first resistor of the multiple serially connected resistors is connected to the second terminal of the first resistor and a second terminal of a last resistor of the multiple serially connected resistors is connected to the junction of the gate of the flipped gate transistor and the drain of the normally gated transistor.

25. The UVLO circuit of claim 24 wherein when each junction of each of the terminals of the multiple serially connected resistors is connected to one switch of a plurality of single pole switches.

26. The UVLO circuit of claim 25 further comprising a threshold adjusting current source configured for generating a threshold adjusting current and connected to the plurality of single pole switches for transferring the adjusting current through one selected switch of the plurality of switches for adjusting the threshold of the power supply voltage source for activating the electronic device and the threshold for deactivating the electronic device can be modified dependent upon the region of the amplitude of the voltage level of the power supply voltage that provides full functionality for the electronic device.

27. The UVLO circuit of claim 26 further comprising a switch selector in communication with a control terminal for each of the plurality of switches for selecting one of the switches for activation for transferring the adjusting current through one selected switch of the plurality of switches for adjusting the threshold of the power supply voltage source for activating the electronic device and the threshold for deactivating the electronic device.

28. An electronic device comprising: an under-voltage lockout (UVLO) circuit configured for enabling and disabling an electronic device, if a power supply voltage is at a voltage level that permits the operation of the electronic devices, wherein the UVLO circuit comprises: a non-differential comparator configured to have a fixed threshold voltage at an input such that when a signal developed from the power supply voltage and a reference voltage is greater than the fixed threshold voltage, an output of the non-differential comparator is placed at a first voltage level and when the signal developed from the power supply voltage and the reference voltage is less than the fixed threshold voltage, an output of the non-differential comparator is placed at a second voltage level, wherein the first and second voltage levels define a comparison output signal; a voltage divider having a first terminal connected to the power supply voltage and a second terminal connected to receive the reference voltage and configured for dividing a difference in the power supply voltage and the reference voltage such that a compare voltage is applied to the input of the non-differential comparator for comparison with the fixed threshold voltage; and a hysteresis controller configured for adjusting the compare voltage such that if the power supply voltage is less than a falling threshold voltage, the voltage difference between the power supply voltage and the reference voltage is at a first voltage level to make the compare voltage at the voltage level of the fixed threshold voltage and configured for adjusting the compare voltage such that if the power supply voltage is greater than a rising voltage, to make the compare voltage at the voltage level of the fixed threshold voltage to establish hysteresis between the first voltage level and the second voltage level.

29. The electronic device of claim 28 wherein the non-differential comparator comprises: a flipped gate transistor comprising: a gate configured to receive the signal developed from the power supply voltage and the reference voltage, a source connected to a ground reference voltage, a drain configured for providing the first and second voltage levels at the output of the comparison circuit; and wherein the flipped gate transistor is configured such that a gate-to-source threshold voltage is the fixed threshold voltage; and a reference current source having a first terminal connected to the drain of the flipped gate transistor and a second terminal connected to a power terminal of the power supply voltage and configured for providing a reference current for the flipped gate transistor for developing the first and second voltage levels.

30. The electronic device of claim 28 wherein the voltage divider comprises: a first resistor with a first terminal connected to receive the power supply voltage and a second terminal; a second resistor with a first terminal connected to the second terminal of the first resistor and a second terminal connected to a gate of the flipped gate transistor; a voltage to current converter connected for receiving the reference voltage, connected to the junction of the connection between the second terminal of the second resistor and the gate of the flipped gate transistor, and configured for providing a conversion current to the first and second resistors that is proportional to an amplitude of the reference voltage; wherein, the resistance of the first and second resistors, an amplitude of the power supply voltage, an amplitude of the reference voltage determine the compare voltage applied to the gate of the flipped gate transistor for determining a voltage difference at which the flipped gate transistor will change from the level of the power supply voltage to the level of the reference voltage.

31. The electronic device of claim 30 the voltage to current converter comprises: a normally gated transistor comprising: a drain connected to the gate of the flipped gate transistor and the second terminal of the first resistor, a gate connected to reference voltage, and a source; and a third resistor having a first terminal connected to the source of the normally gated transistor and a second terminal connected to the ground reference voltage.

32. The electronic device of claim 30 wherein the UVLO circuit further comprises: an inverter buffer having an input connected to the output of the non-differential comparator and an output connected to circuitry of an electronic device, and configured for receiving the first voltage level and the second voltage level from the non-differential comparator for inverting and buffering the comparison output signal to create the output signal of the UVLO circuit for transfer to the external circuitry indicating that the electronic device is turned on or turned off.

33. The electronic device of claim 32 wherein the inverter buffer comprises: has a transistor of the first conductivity comprising: a source connected to the power supply voltage, a drain connected to the external circuitry, and a gate connected to the output of the non-differential comparator; and a transistor of the second conductivity, comprising: a source connected to the ground reference voltage, a drain connected to the drain of the transistor of the first conductivity and to the external circuitry, and a gate connected to the output of the non-differential comparator and to the gate of the transistor of the first conductivity.

34. The electronic device of claim 33 wherein the conversion current flows through the first and second resistors to establish the compare voltage at the gate of the flipped gate transistor.

35. The electronic device of claim 32 wherein when the compare voltage at the gate of the flipped gate transistor is greater than the gate to source threshold voltage of the flipped gate transistor, the power supply voltage and the reference voltage are at a voltage difference that the compare voltage will turn on the flipped gate transistor and the input to the inverter buffer becomes approximately the voltage level of the ground reference voltage and the output of the inverter buffer becomes activated to the second logical state.

36. The electronic device of claim 33 wherein when the compare voltage at the gate of the flipped gate transistor becomes is less than the threshold voltage of the flipped gate transistor, the power supply voltage is less than the falling threshold voltage such that the compare voltage will turn off the flipped gate transistor and the input to the inverter buffer becomes approximately the voltage level of the power supply voltage and the output of the inverter buffer becomes deactivated to a first logical state.

37. The electronic device of claim 28 wherein the hysteresis controller comprises: the third resistor that is placed between the second resistor and the power supply voltage; a hysteresis control transistor comprising: a source connected to the power supply voltage, a drain connected to the junction of the connection between the third resistor and the second resistor, and a gate of the hysteresis control transistor connected to the junction of the reference current source and the drain of the flipped gate transistor, wherein when the flipped gate transistor is turned off, the hysteresis control transistor is also turned off and the power supply voltage has the falling threshold voltage, wherein when the flipped gate transistor is turned on, the hysteresis control transistor is also turned on, effectively shorting out the third resistor for changing the power supply voltage to have the rising threshold.

38. The electronic device of claim 30 wherein when the compare voltage at the gate of the flipped gate transistor is greater than the gate to source threshold voltage of the flipped gate transistor, the amplitude of the power supply voltage is greater than the rising threshold voltage and the flipped gate transistor turns on such that the input to the inverter buffer becomes approximately the voltage level of the ground reference voltage and the output of the inverter buffer becomes activated to the second logical state, and the electrical device is activated to be fully functional.

39. The electronic device of claim 31 wherein when the compare voltage at the gate of the flipped gate transistor becomes is less than the threshold voltage of the flipped gate transistor, the voltage level of the power supply voltage is less than the falling threshold voltage and the flipped gate transistor turns off such that the input to the inverter buffer becomes approximately the voltage level of the power supply voltage and the output of the inverter buffer becomes deactivated to the first logical state, and the electrical device is deactivated to be turned off.

40. The electronic device of claim 30 wherein the second resistor comprises a plurality of serially connected resistors, wherein a first terminal of a first resistor of the multiple serially connected resistors is connected to the second terminal of the first resistor and a second terminal of a last resistor of the multiple serially connected resistors is connected to the junction of the gate of the flipped gate transistor and the drain of the normally gated transistor.

41. The electronic device of claim 40 wherein when each junction of each of the terminals of the multiple serially connected resistors is connected to one switch of a plurality of single pole switches.

42. The electronic device of claim 41 further comprising a threshold adjusting current source configured for generating an threshold adjusting current and connected to the plurality of single pole switches for transferring the adjusting current through one selected switch of the plurality of switches for adjusting the threshold of the power supply voltage source for activating the electronic device and the threshold for deactivating the electronic device can be modified dependent upon the region of the amplitude of the voltage level of the power supply voltage that provides full functionality for the electronic device.

43. The electronic device of claim 42 further comprising a switch selector in communication with a control terminal for each of the plurality of switches for selecting one of the switches for activation for transferring the adjusting current through one selected switch of the plurality of switches for adjusting the threshold of the power supply voltage source for activating the electronic device and the threshold for deactivating the electronic device.

44. A method for operating an under-voltage lockout (UVLO) circuit of an electronic device comprising the steps of: providing a non-differential comparator with a fixed threshold within the UVLO circuit; when the electronic device is turned off, setting an output of the UVLO circuit to a first logical state; turning off the electronic device; setting a threshold of a power supply voltage to a rising threshold voltage; dividing the power supply voltage such that as the power supply voltage increases from an unpowered voltage level to the rising threshold voltage, the output of the UVLO circuit is at the first logical state; when the power supply reaches and exceeds the rising threshold level at an input of the non-differential comparator, the non-differential comparator switches output voltage state such that the output of the UVLO circuit switches to a second logic state for turning on the electronic device; setting the threshold of the power supply voltage to a falling threshold voltage dividing the power supply voltage such that when the power supply voltage decreases from a fully powered voltage level to the falling threshold voltage, the output of the UVLO circuit is at the second logical state; when the power supply is less than the falling threshold level at the input of the non-differential comparator, the non-differential comparator switches output voltage state such that the output of the UVLO circuit switches to the first logic state for turning off the electronic device; and setting the threshold of the power supply voltage to the rising threshold voltage.

45. The method claim 44 wherein the non-differential comparator is configured to have a fixed threshold voltage at an input such that when a signal developed from the power supply voltage and a reference voltage is greater than the fixed threshold voltage, an output of the non-differential comparator is placed at a first voltage level and when the signal developed from the power supply voltage and the reference voltage is less than the fixed threshold voltage, an output of the non-differential comparator is placed at a second voltage level.

46. The method of claim 44 wherein the non-differential comparator comprises: a flipped gate transistor comprising: a gate configured to receive the signal developed from the power supply voltage and the reference voltage, a source connected to a ground reference voltage, a drain configured for providing the first and second voltage levels at the output of the comparison circuit; and wherein the flipped gate transistor is configured such that a gate-to-source threshold voltage is the fixed threshold voltage; and a reference current source having a first terminal connected to the drain of the flipped gate transistor and a second terminal connected to a power terminal of the power supply voltage and configured for providing a reference current for the flipped gate transistor for developing the first and second voltage levels.

47. The method of claim 44 wherein dividing the power supply voltage comprises the step of providing a voltage divider, wherein the voltage divider comprises: a first resistor with a first terminal connected to receive the power supply voltage and a second terminal; a second resistor with a first terminal connected to the second terminal of the first resistor and a second terminal connected to a gate of the flipped gate transistor; and a voltage to current converter connected for receiving the reference voltage, connected to the junction of the connection between the second terminal of the second resistor and the gate of the flipped gate transistor, and configured for providing a conversion current to the first and second resistors that is proportional to an amplitude of the reference voltage; wherein, the resistance of the first and second resistors, an amplitude of the power supply voltage, an amplitude of the reference voltage determine the compare voltage applied to the gate of the flipped gate transistor for determining a voltage difference at which the flipped gate transistor will change from the level of the power supply voltage to the level of the ground reference voltage.

48. The method circuit of claim 47 wherein the voltage to current converter comprises: a normally gated transistor comprising: a drain connected to the gate of the flipped gate transistor and the second terminal of the first resistor, a gate connected to a biasing reference voltage, and a source; and a third resistor having a first terminal connected to the source of the normally gated transistor and a second terminal connected to the ground reference voltage.

49. The method of claim 48 wherein the conversion current flowing through the third resistor flows through the first and second resistors to establish the compare voltage at the gate of the flipped gate transistor.

50. The method of claim 49 wherein when the compare voltage at the gate of the flipped gate transistor is greater than the fixed threshold voltage of the flipped gate transistor, the power supply voltage is at the rising threshold voltage such that the compare voltage will turn on the flipped gate transistor and the output of the UVLO circuit becomes activated to the second logical state.

51. The method circuit of claim 49 wherein when the compare voltage at the gate of the flipped gate transistor becomes is less than the threshold voltage of the flipped gate transistor, the power supply voltage is at the falling threshold voltage such that the compare voltage will turn off the flipped gate transistor and output of the UVLO circuit becomes deactivated to a first logical state.

52. The method circuit of claim 49 wherein setting the rising threshold voltage and setting the falling threshold voltage each include providing a hysteresis controller configured for adjusting the compare voltage such that when the power supply voltage is less than the rising threshold voltage, the compare voltage is less than the fixed threshold voltage and when the power supply voltage is greater than the falling threshold voltage the compare voltage is greater than the fixed threshold voltage to establish hysteresis between the compare voltage when the power supply voltage is increasing and the compare voltage when the power supply is decreasing.

53. The method circuit of claim 49 wherein the hysteresis controller comprises: the first resistor that is placed between the second resistor and the power supply voltage; a hysteresis control transistor comprising: a source connected to the power supply voltage, a drain connected to the junction of the connection between the third resistor and the second resistor, and a gate of the hysteresis control transistor connected to the junction of the reference current source and the drain of the flipped gate transistor, wherein when the flipped gate transistor is turned off, indicating that the first voltage is less than the second voltage, the hysteresis control transistor is also turned off and the power supply voltage is set at the rising threshold voltage for indicating that the power supply voltage is less than the rising threshold voltage, wherein when the flipped gate transistor is turned on, the hysteresis control transistor is also turned on, effectively shorting out the first resistor for setting the power supply voltage at the falling indicating that the power supply voltage is greater than the falling threshold voltage.

54. The method of claim 49 wherein when the compare voltage at the gate of the flipped gate transistor is greater than the fixed threshold voltage of the flipped gate transistor, the amplitude of the power supply voltage is greater than the rising voltage and the flipped gate transistor turns on such that output of the UVLO circuit is activated to the second logical state, and the electrical device is activated to be fully functional.

55. The method circuit of claim 49 wherein when the compare voltage at the gate of the flipped gate transistor becomes is less than the fixed threshold voltage of the flipped gate transistor, the voltage level of the power supply voltage is less than the rising threshold voltage and the flipped gate transistor turns off such that output of the UVLO becomes deactivated to the first logical state, and the electrical device is deactivated to be turned off.

56. The method of claim 48 wherein the second resistor comprises by a plurality of serially connected resistors, wherein a first terminal of a first resistor of the multiple serially connected resistors is connected to the second terminal of the first resistor and a second terminal of a last resistor of the multiple serially connected resistors is connected to the junction of the gate of the flipped gate transistor and the drain of the normally gated transistor.

57. The method of claim 27 wherein the UVLO circuit further comprises a switch selector in communication with a control terminal for each of the plurality of switches for selecting one of the switches for activation for transferring the adjusting current through one selected switch of the plurality of switches for adjusting the threshold of the power supply voltage for activating the electronic device and the threshold for deactivating the electronic device.

58. The method of claim 57 wherein the UVLO circuit further comprises a threshold adjusting current source configured for generating an threshold adjusting current and connected to the plurality of single pole switches for transferring the adjusting current through one selected switch of the plurality of switches for adjusting the threshold of the power supply voltage at which the electronic device is activated and the threshold at which the electronic device is deactivated can be modified dependent upon the region of the amplitude of the voltage level of the power supply voltage that provides full functionality for the electronic device.

59. The method circuit of claim 58 wherein when each junction of each of the terminals of the multiple serially connected resistors is connected to one switch of a plurality of single pole switches.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a graphical representation of the different power supply modes that a low power device typically encounters.

(2) FIG. 2a is a schematic drawing of a UVLO circuit of prior art.

(3) FIG. 2b is a plot of the output voltage of the UVLO circuit of prior art versus the voltage level of a power supply voltage source.

(4) FIG. 3a is a cross sectional diagram of a normal MOS transistor of the related art.

(5) FIG. 3b is a cross sectional diagram of a Flipped-Gate MOS transistor of the related art.

(6) FIGS. 4a and 4b are schematic drawings of comparison circuits embodying the principles of the present disclosure.

(7) FIG. 5 is a schematic drawing of an implementation of a UVLO circuit embodying the principles of the present disclosure.

(8) FIG. 6a is a schematic drawing of a second implementation of a UVLO circuit embodying the principles of the present disclosure.

(9) FIG. 6b is a plot of the output voltage of the UVLO circuit FIG. 6a versus the voltage level of a power supply voltage source.

(10) FIG. 7 is a schematic drawing of a third implementation of a UVLO circuit embodying the principles of the present disclosure.

(11) FIG. 8 is a plot of simulations of the third implementation of a UVLO circuit of FIG. 7 showing the output voltage of the UVLO circuit of FIG. 7 versus the voltage level of the power supply voltage for nine different threshold voltage level settings.

(12) FIG. 9 is a plot of simulations of the third implementation of a UVLO circuit of FIG. 7 showing the transient response of the UVLO circuit of FIG. 7 over time.

(13) FIG. 10 is a flow chart illustrating the operation of UVLO embodying the principles of the present disclosure.

DETAILED DESCRIPTION

(14) The UVLO circuit of this disclosure has a non-differential comparator that uses the threshold voltage of a flipped gate transistor for determining if a voltage level of a power supply voltage source of an electronic device is sufficient for allowing fully functional operation. A voltage divider uses a reference voltage for establishing when the threshold voltage level of the power supply voltage source is at it functional voltage level. The voltage divider is connected to the gate of the flipped gate transistor and configured such that the threshold voltage level of the power supply voltage source is applied at the input of the UVLO circuit to provide the threshold voltage of the flipped gate transistor to turn on the flipped gate transistor. The voltage divider is structured such that the comparator function is defined by two different threshold voltages that differ by the bandgap of the semiconductor material from which the transistors are manufactured. To achieve the differences in the threshold levels, one transistor is a normal transistor as described in FIG. 3a and is manufactured using present materials and fabrication techniques and the second transistor is a flipped gate transistor as described in FIG. 3b.

(15) FIGS. 3a and 3b are a cross sectional diagrams respectively of a MOS transistor and a flipped-gate MOS transistor of the related art. In the related art as shown in FIGS. 3a and 3b, a flipped-gate transistor (FIG. 3b) has a threshold voltage that is greater than the threshold voltage of a normal transistor. The normal transistor is defined is one that employs the standard processing currently in practice and is similar to that shown in FIG. 3a. MOS voltage reference based on polysilicon gate work function difference, Oguey, et al., IEEE Journal of Solid-State Circuits, vol. 15, no. 3, pp. 264-269, June 1980 as reproduced in FIGS. 3a and 3b. Quoting from Oguey et al., FIG. 3a shows a standard n-channel transistor 5 with an n-type gate 20 and FIG. 3b modified n-channel transistor 10 with a p-type gate 25 fabricated with a technology that uses doped oxides as diffusion sources. In the standard transistor 5, gate 20, drain 35, and source 40 are surrounded by a phosphorus-doped oxide 15. Source 40 and drain 35 are self-aligned with the gate 20. Effective channel length Leff is gate length minus two lateral diffusion lengths. In the modified transistor, the center part of the gate 25 is p-doped by leaving above it a region of boron-doped oxide 30. This structure behaves like a higher threshold transistor of channel length Leff in series with two short-channel low-threshold transistors. The additional transistors 50 produce a negligible effect in weak inversion, but contribute to a larger change in gate threshold voltage at higher current levels.

(16) FIGS. 4a and 4b are schematic drawings of comparison circuits embodying the principles of the present disclosure. In FIG. 4a, a comparison circuit is configured for comparing two input voltages V1 and V2 and determining if a first input voltage V1 is greater than or lesser than threshold voltage V.sub.TH between the first input voltage V1 and a second input voltage V2. A bandgap voltage V.sub.BANDGAP given by a threshold voltage difference between a normally gated transistor M.sub.NGD and a flipped gate transistor M.sub.FGD. Therefore, the threshold voltage V.sub.TH can be realized accurately with a voltage divider/current converter VIC having resistors R.sub.1 and R.sub.2 with almost same value. To be more accurate, a ratio R.sub.1/R.sub.2 of the resistors R.sub.1 and R.sub.2 can be chosen to compensate any non-idealities of the process and the temperature coefficient of the flipped gate transistor M.sub.FGD.

(17) The comparison circuit has a non-differential comparator NDC that includes the flipped gate transistor M.sub.FGD and a reference current source I.sub.REF. The reference current source I.sub.REF has a first terminal connected to a power supply voltage source V.sub.dd and a second terminal connected to a drain of the flipped gate transistor M.sub.FGD. The source of the flipped gate transistor M.sub.FGD is connected to a ground reference voltage source V.sub.ss.

(18) The comparison circuit includes the voltage divider/current converter VIC that is connected to the gate of the flipped gate transistor. The gate of the flipped gate transistor is connected to a drain of the normally gated transistor M.sub.NGD. The gate of the normally gated transistor M.sub.NGD is connected to receive the second input voltage V.sub.2. The source of the normally gated transistor M.sub.NGD is connected to a first terminal of a first resistor R.sub.1 and a second terminal of the second resistor R.sub.1 is connected to the ground reference voltage source V.sub.ss. The normally gated transistor M.sub.NGD and the second resistor R.sub.1 thus form a voltage to current converter where a conversion current I.sub.1 flows through the voltage to current converter and is proportional to the second input voltage V.sub.2.

(19) The voltage divider/current converter VIC has a second resistor R.sub.2 with a first terminal connected for receiving the first input voltage V.sub.1. A second terminal of the second resistor R.sub.2 is connected to the gate of the flipped gate transistor M.sub.FGD.

(20) The comparison circuit further has an inverter buffer INV1 having an input connected to the common connection of the drain of the flipped gate transistor M.sub.FGD and the second terminal of the reference current source I.sub.REF. The output of the inverter buffer INV1 is connected to circuitry within the electronic device. The inverter has a PMOS transistor M.sub.P! and NMOS transistor M.sub.N1. The source of the PMOS transistor M.sub.P1 is connected to the power supply voltage source V.sub.dd. The drain of the PMOS transistor M.sub.P1 is connected to the drain of the NMOS transistor M.sub.N1 and to the output DOUT of the inverter buffer INV1. The source of the NMOS transistor M.sub.N1 is connected to the ground reference voltage source V.sub.ss. The gates of the PMOS transistor M.sub.P1 and NMOS transistor M.sub.N1 are connected and connected to the input of the inverter buffer INV1 that is connected to common connection of the drain of the flipped gate transistor M.sub.FGD and the second terminal of the reference current source I.sub.REF.

(21) The conversion current flows through the second resistor R.sub.2 to establish a compare voltage V.sub.CMP at the gate of the flipped gate transistor M.sub.FGD. When the compare voltage V.sub.CMP at the gate of the flipped gate transistor is greater than the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD, the first input voltage V.sub.1 is greater than the second input voltage V.sub.2 and the flipped gate transistor M.sub.FGD turns on. The input to the inverter buffer INV1 becomes approximately the voltage level of the ground reference voltage source V.sub.ss and the output DOUT of the inverter buffer INV1 becomes activated to a logical 1. When the compare voltage compare voltage V.sub.CMP at the gate of the flipped gate transistor becomes is less than the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD, the first input voltage V.sub.1 is less than the second input voltage V.sub.2 and the flipped gate transistor M.sub.FGD turns off. The input to the inverter buffer INV1 becomes approximately the voltage level of the power supply voltage source V.sub.dd and the output of the inverter buffer INV1 becomes deactivated to a logical 0.

(22) The threshold voltage V.sub.TH is the voltage level of the first input voltage V.sub.1 at which the flipped gate transistor M.sub.FGD is turned on or turned on indicating the relative amplitudes of the first input voltage V.sub.1 and the second input V.sub.2. The voltage level of the threshold voltage V.sub.TH is determined according to the equation (3) as:

(23) $\begin{array}{cc}{V}_{\mathrm{TH}}=\left(\frac{R_2}{R_1}\right)\left(V_2-V_{\mathrm{GSF}}\right)+V_{\mathrm{GSN}}& \left(3\right)\end{array}$ Where: V.sub.TH is the voltage at which the first input voltage V.sub.1 is set to cause the comparison with the second input voltage V.sub.2 to switch the comparison circuit to state; R.sub.1 is the value of the resistance of the resistor R.sub.1 to set the conversion current I.sub.1; R.sub.2 is the value of the resistance of the resistor R.sub.2 for scaling the first input voltage V.sub.1 to be scaled to the bandgap voltage.sub.; V.sub.GSF is the gate to source voltage of the flipped gate transistor M.sub.FGD; V.sub.GSN is the gate to source voltage of the normally gated transistor M.sub.FGN.

(24) In FIG. 4b, the comparison circuit is structured as shown above for FIG. 4a with the addition of a hysteresis controller HYC. The hysteresis controller HYC has a third resistor R.sub.3 that is placed between the second resistor R.sub.2 and the first input voltage V.sub.1 such that a first terminal of the third resistor R.sub.3 is connected to the first input voltage V.sub.1 and a second terminal of the third resistor is connected to the first terminal of the second resistor R.sub.2. The hysteresis controller HYC has a hysteresis control PMOS transistor M.sub.P2 with a source connected to the power supply voltage source V.sub.dd and drain connected to the junction of the connection between third resistor R.sub.3 and the second resistor R.sub.2. The gate of the hysteresis control PMOS transistor M.sub.P2 is connected to the junction of the reference current source I.sub.REF and the drain of the flipped gate transistor M.sub.FGD. When the flipped gate transistor M.sub.FGD is turned off, indicating that the first input voltage V.sub.1 is less than the second input voltage V.sub.2 and the output of the inverter buffer INV1 is set to the logical 0. The hysteresis control transistor M.sub.P2 is also turned off. The threshold voltage V.sub.TH is the voltage level of the first input voltage V.sub.1 at which the flipped gate transistor M.sub.FGD is turned on or turned on indicating the relative amplitudes of the first input voltage V.sub.1 and the second input voltage V.sub.2. The voltage level of the threshold voltage V.sub.TH is determined according to the equation (4) as:

(25) $\begin{array}{cc}{V}_{\mathrm{TH}}=\left(\frac{R_2+R_3}{R_1}\right)\left(V_2-V_{\mathrm{GSF}}\right)+V_{\mathrm{GSN}}& \left(4\right)\end{array}$ Where: V.sub.TH is the voltage at which the voltage V.sub.1 set to cause the comparison with the voltage V.sub.2 to switch the comparison circuit to state; R.sub.1 is the value of the resistance of the resistor R.sub.1 to set the current I.sub.1; R.sub.2 is the value of the resistance of the resistor R.sub.2 for scaling the first input voltage V.sub.1 to be scaled to the bandgap voltage; R.sub.3 is the value of the resistance of the resistor R.sub.3 for scaling the first input voltage V.sub.1 to be scaled to the bandgap voltage; V.sub.GSF is the gate to source voltage of the flipped gate transistor M.sub.FGD; V.sub.GSN is the gate to source voltage of the normally gated transistor M.sub.FGN.

(26) When the flipped gate transistor M.sub.FGD is turned on, indicating that the first input voltage V.sub.1 is greater than the second input voltage V.sub.2 and the output of the inverter buffer INV1 is set to the logical 1. The hysteresis control transistor M.sub.P2 is turned on to short out the resistor R.sub.3. The threshold voltage V.sub.TH is then modified such that the voltage level of the first input voltage V.sub.1 and the second input voltage V.sub.2 at which the flipped gate transistor M.sub.FGD is turned on or turned off is modified as desired. The voltage level of the threshold voltage V.sub.TH is determined according to the equation (3) since the resistor R.sub.3 is essentially removed from the circuit. In this case, the sum of the resistances of the second resistor R.sub.2 and the third resistor R.sub.3 is equal to the resistance of the resistor R.sub.1 making the threshold voltage V.sub.TH more negative.

(27) FIG. 5 is a schematic drawing of a basic implementation of an under-voltage lock out circuit UVLO embodying the principles of the present disclosure. The UVLO circuit is configured for enabling an electronic device, when a power supply voltage source V.sub.dd is at a voltage level that permits the operation of the electronic device, or disabling the electronic device, when the power supply voltage source is at a voltage level that prevents the operation of the electronic device. The UVLO circuit has a non-differential comparator NDC that includes a flipped gate transistor M.sub.FGD and a reference current source I.sub.REF. The reference current source I.sub.REF has a first terminal connected to a power supply voltage source V.sub.dd and a second terminal connected to a drain of the flipped gate transistor M.sub.FGD. The source of the flipped gate transistor M.sub.FGD is connected to a ground reference voltage source V.sub.ss.

(28) The UVLO Circuit has a voltage divider/converter VIC that is connected to the non-differential comparator NDC. The voltage divider/converter VIC has a normally gated transistor M.sub.NGD where the gate of the flipped gate transistor M.sub.FGD is connected to a drain of a normally gated transistor M.sub.NGD. The voltage divider/converter VIC has a first resistor R1.sub.2 and a second resistor R.sub.2. A first terminal of the first resistor R.sub.1 is connected to the power supply voltage source V.sub.dd. The second terminal of the first resistor R.sub.1 is connected to the first terminal of the second resistor R.sub.2. The second terminal of the second resistor R.sub.2 is connected to a gate of the flipped gate transistor M.sub.FGD and to the drain of the normally gated transistor M.sub.NGD. The gate of the normally gated transistor M.sub.NGD is connected to receive a reference voltage V.sub.REF. The source of the normally gated transistor M.sub.NGD is connected to a first terminal of a first resistor and a second terminal of the first resistor is connected to the ground reference voltage source V.sub.SS. A voltage to current converter is formed by the normally gated transistor M.sub.NGD and the first resistor R.sub.1. The voltage to current converter creates a conversion current I.sub.1 that is proportional to the reference voltage V.sub.REF.

(29) The UVLO Circuit further has an inverter buffer INV1 having an input connected to common connection of the drain of the flipped gate transistor M.sub.FGD and the second terminal of the reference current source I.sub.REF. The output of the inverter buffer INV1 is connected to external circuitry for enabling and disabling the electronic device. The inverter buffer INV1 has a PMOS transistor M.sub.P1 and NMOS transistor M.sub.N1. The source of the PMOS transistor PMOS transistor M.sub.P1 is connected to the power supply voltage source V.sub.dd. The drain of the PMOS transistor M.sub.P1 is connected to the drain of the NMOS transistor M.sub.N1 and to the output DOUT of the inverter buffer INV1. The source of the NMOS transistor M.sub.N1 is connected to the ground reference voltage source V.sub.SS. The gates of the PMOS transistor M.sub.P1 and NMOS transistor M.sub.N1 are connected and connected to the input of the inverter buffer INV1.

(30) The conversion current I.sub.1 flows through the second and third resistors R.sub.2 and R.sub.3 to establish a compare voltage V.sub.CMP at the gate of the flipped gate transistor M.sub.FGD. When the compare voltage V.sub.CMP at the gate of the flipped gate transistor M.sub.FGD is greater than the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD, the amplitude of the power supply voltage source V.sub.dd is greater than the raising threshold voltage V.sub.THR and the flipped gate transistor M.sub.FGD turns on. The input to the inverter buffer INV1 becomes approximately the voltage level of the ground reference voltage source V.sub.SS and the output of the inverter buffer INV1 becomes activated to a logical 1. The electrical device is activated to be fully functional. When the compare voltage V.sub.CMP at the gate of the flipped gate transistor M.sub.FGD becomes is less than the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD, the voltage level of the power supply voltage source V.sub.dd is less than the falling threshold V.sub.THF and the flipped gate transistor M.sub.FGD turns off. The input to the inverter buffer INV1 becomes approximately the voltage level of the power supply voltage source V.sub.dd and the output of the inverter buffer INV1 becomes deactivated to a logical 0. The electrical device is deactivated to be turned off.

(31) The UVLO Circuit has a hysteresis controller HYC that includes the third resistor R.sub.3 and a hysteresis control PMOS transistor M.sub.P2. A source of the hysteresis control PMOS transistor M.sub.P2 is connected to the power supply voltage source V.sub.dd and a drain of the hysteresis control PMOS transistor M.sub.P2 is connected to the junction of the connection between third resistor R.sub.3 and the second resistor R.sub.3. The gate of the hysteresis control PMOS transistor M.sub.P2 is connected to the junction of the reference current source I.sub.REF and the drain of the flipped gate transistor M.sub.FGD. When the flipped gate transistor M.sub.FGD is turned off, indicating that the voltage level of the power supply voltage source V.sub.dd is less than the rising threshold voltage level V.sub.THR, the hysteresis control transistor M.sub.P2 is also turned off and the compare voltage V.sub.CMP for indicating that the amplitude of the power supply voltage source V.sub.dd is less than the rising threshold voltage level V.sub.THR and the output of the inverter buffer INV1 is set to the logical 0 and the electronic device is turned off.

(32) When the voltage level of the power supply voltage source V.sub.dd is greater than the rising threshold voltage level V.sub.THR, the flipped gate transistor M.sub.FGD is turned on, output of the inverter buffer INV1 is activated to a logical 1 and the electronic device is turned on. At the same time, the hysteresis control transistor M.sub.P2 is also turned on. This effectively shorts out the third resistor R.sub.3 and changes the threshold voltage level of the power supply voltage source V.sub.dd to be the falling threshold voltage level V.sub.THF. Thus, when the power supply voltage source V.sub.dd is less than the falling threshold voltage level V.sub.THF, the flipped gate transistor M.sub.FGD is turned off to set the output of the inverter buffer to a logical 0 for turning off the electronic device. When the flipped gate transistor M.sub.FGD turns off, the hysteresis control transistor M.sub.P2 is also turns off. The third resistor is restored to the voltage divider and the rising threshold voltage V.sub.THR is restored. As long as the voltage level of the power supply voltage source V.sub.dd is less than the rising threshold voltage V.sub.THR, the flipped gate transistor M.sub.FGD is turned off, the output DOUT of the inverter buffer INV1 is at the logical 0, and the electronic device is turned off. When the voltage level of the power supply voltage source V.sub.dd is greater than the rising threshold voltage V.sub.THR, the flipped gate transistor M.sub.FGD is turned on, the output DOUT of the inverter buffer INV1 is at the logical 1, and the electronic device is turned on. The cycle of operation is completed.

(33) FIG. 6a is a schematic drawing of a second implementation of a UVLO circuit embodying the principles of the present disclosure having selectable rising threshold voltages V.sub.THR1 and V.sub.THR2 and falling threshold voltages V.sub.THF1 and V.sub.THF2. FIG. 6b is a plot of the output voltage of the UVLO circuit FIG. 6a versus the voltage level of a power supply voltage source V.sub.dd. The basic structure of the second implementation of the UVLO circuit is the same as the implementation of the UVLO circuit of FIG. 5. The voltage divider/current converter VIC, the non-differential comparator NDC, and the inverter buffer INV1 are configured identically. The addition of the selector circuit HSEL is added to the UVLO circuit of FIG. 5 provide for selecting one of two threshold pairs V.sub.THR1 and V.sub.THF1 and V.sub.THR2 and V.sub.THF2. The selector circuit includes the switches SW.sub.0 and SW.sub.1 and the biasing current source I.sub.2. The switch SW.sub.0 has a first pole connected to the junction of the resistor R.sub.2 and the resistor R.sub.3 and a second pole connected to a first terminal of the biasing current source I.sub.2. The switch SW.sub.1 has a first pole connected to the junction of the resistor R.sub.2, the gate of the flipped gate transistor M.sub.FGD, and the drain of the normally gated transistor M.sub.NGD and a second pole connected to a first terminal of the biasing current source I.sub.2. The switches SW.sub.0 and SW.sub.1 each have a control terminal that is connected to a control circuit (not shown) that selects to activate one of the switches SW.sub.0 and SW.sub.1 at any given time or what is commonly called a one-hot operation.

(34) The current consumed by the UVLO circuit of this implementation is increased by the amplitude of the biasing current source I.sub.2. Refer now to FIG. 6b. When the UVLO circuit is initially activated the switch SW.sub.0 is closed and SW.sub.1 is normally open. The voltage drop across the resistor R.sub.3 is determined by resistance of the resistor R.sub.3 multiplied by the sum of the conversion current I.sub.1 and the current I.sub.2 (I.sub.1+I.sub.2). The thresholds are then set to the rising threshold voltage V.sub.THR1 and falling threshold voltages V.sub.THF1. When the switch SW.sub.0 is opened and SW.sub.1 is closed, the voltage drop across the resistor R.sub.3 and the resistor R.sub.2 is sum of the resistances of the resistors R.sub.2 and R.sub.3 (R.sub.2+R.sub.3) multiplied by the sum of the conversion current I.sub.1 and the current I.sub.2 (I.sub.1+I.sub.2). The thresholds are then set to the rising threshold voltage V.sub.THR2 and falling threshold voltages V.sub.THF2.

(35) The hysteresis shift of the rising threshold voltages V.sub.THR1 and V.sub.THR2 to the falling threshold voltages V.sub.THF1 and V.sub.THF2 is controlled, as described above, by the activation and deactivation of the hysteresis control PMOS transistor M.sub.P2. The voltage shift in the threshold voltage from the first threshold voltage pair V.sub.THR1 and V.sub.THF1 to the second threshold voltage pair V.sub.THR2 and V.sub.THF2 is determined by the resistance of the resistor R.sub.2 multiplied by the current I.sub.2 (R.sub.2*I.sub.2).

(36) FIG. 7 is a schematic drawing of a third implementation of a UVLO circuit embodying the principles of the present disclosure. It will be apparent to those skilled in the art, that the functionality of FIG. 6a will be improved by adding more switches and taps on resistor R.sub.2 to give fine step selection of the threshold values of the power supply voltage source V.sub.dd at which the UVLO circuit is triggered while maintaining the same current consumption. Referring to FIG. 7, the non-differential comparator NDC, and the inverter buffer INV1 are configured identically to those of FIG. 5. The capacitor C is placed such that the first terminal of the capacitor C is connected to power supply voltage source V.sub.dd and the common connection of the second terminal of the reference current source I.sub.REF, the drain of the flipped gate transistor M.sub.FGD, and the input of the inverter buffer INV1. The purpose of the capacitor C is added such that the output DOUT of the inverter buffer INV1 is held at a the logical 0 for guaranteeing a proper reset period when the electronic device is connected to the power supply voltage source.

(37) The voltage divider/current converter VIC is essentially identical to the voltage divider/current converter VIC of FIG. 6a except the resistor R.sub.2 is composed of multiple serially connected resistors R.sub.21, . . . , R.sub.2n. The connection between each of the multiple serially connected resistors R.sub.21, . . . , R.sub.2n is the tap of the resistor R.sub.2 that connects to the multiple switch transistors M.sub.S0, . . . , M.sub.S7, and M.sub.S8 for providing the fine step selection of the threshold values of the power supply voltage source V.sub.dd at which the UVLO circuit is triggered. As described in FIG. 6a, the first switch transistor M.sub.S0 has a source connected to the junction of the resistor R.sub.21 and the resistor R.sub.3. The source of last select transistor M.sub.S8 is connected to the junction of the last resistor R.sub.2n, the gate of the flipped gate transistor M.sub.FGD, and the drain of the normally gated transistor M.sub.NGD. The remaining select transistors as illustrated by the select transistor M.sub.S7 have their sources connected to the junctions of the serially connected resistors.

(38) The drains of the multiple switch transistors M.sub.S0, . . . , M.sub.S7, and M.sub.S8 are connected together and to the drain of the native transistor M.sub.NT. As is known in the art, the native transistor M.sub.NT is a MOS field-effect transistor that functions between enhancement and depletion modes. The native transistor M.sub.NT is formed using the only natural thin oxide film formed over the silicon substrate during processing of other layers and has a threshold voltage V.sub.GSNT that is nearly zero volts.

(39) The source of the native transistor M.sub.NT is connected to a first terminal of an trimmable resistor R.sub.4. The second terminal of an trimmable resistor R.sub.4 is connected to the ground reference voltage source V.sub.SS. The reference voltage V.sub.REF terminal is connected to the low pass filter LPF. The output of the low pass filter LPF is a filtered reference voltage V.sub.REF that is transferred to the gate of the native transistor M.sub.NT. The native transistor M.sub.NT and the trimmable resistor R.sub.4 form a constant biasing current source that sources the biasing current I.sub.2. The biasing current I.sub.2 is determined by the equation:
I.sub.2=(V.sub.REFV.sub.GSNT)R.sub.4 Where: V.sub.GSNT is the gate to source voltage of the native transistor M.sub.NT.
As noted the above, the gate to source voltage of the native transistor M.sub.NT is approximately zero volts. Thus, the biasing current I.sub.2 is approximately equal to the product of the reference voltage V.sub.REF and the biasing resistor R.sub.4.

(40) In operation, one of the multiple switch transistors M.sub.S0, . . . , M.sub.S7, and M.sub.S8 is turned on to set the falling threshold voltage level V.sub.THF where output of the inverter buffer INV1 toggles between the logical 0 to the logical 1. The hysteresis control circuit HYS determines the width of the hysteresis voltage V.sub.HYS (as shown in FIG. 6a) by the activation and deactivation of the hysteresis control PMOS transistor M.sub.P2. The hysteresis control PMOS transistor M.sub.P2 has a source connected to the power supply voltage source V.sub.dd and drain connected to the junction of the connection between third resistor R.sub.3 and the second resistor R.sub.2. The gate of the hysteresis control PMOS transistor M.sub.P2 is connected to the junction of the reference current source I.sub.REF and the drain of the flipped gate transistor M.sub.FGD. When the flipped gate transistor M.sub.FGD is turned off, indicating that the power supply voltage source V.sub.dd is less than the falling threshold voltage V.sub.THF and the output of the inverter buffer INV1 is set to the logical 0. The hysteresis control transistor M.sub.P2 is also turned off and the resistor R.sub.3 is in series with the multiple serially connected resistors R.sub.21, . . . , R.sub.2n that form the resistor R.sub.2. When the flipped gate transistor M.sub.FGD is turned on, indicating that the power supply voltage source V.sub.dd is greater than raising threshold voltage V.sub.THR and the output of the inverter buffer INV1 is set to the logical 1. The hysteresis control transistor M.sub.P2 is also turned on and the resistor R.sub.3 is essentially out from being in series with the multiple serially connected resistors R.sub.21, . . . , R.sub.2n that form the resistor R.sub.2.

(41) The selection of which of the multiple serially connected resistors R.sub.21, . . . , R.sub.2n that current I.sub.2 flows as determined by activation of the one of the multiple switch transistors M.sub.S0, . . . , M.sub.S7, and M.sub.S8 determines the location of the falling threshold voltage level V.sub.THF and the voltage at which the power supply voltage source V.sub.dd is sufficient for turning on or turning off the electronic device. During operations, the sum of the resistances of the resistors R.sub.2 and R.sub.3 is equal the resistance of the resistor R.sub.1. The bandgap voltage V.sub.BANDGAP is determined as the difference of the gate-to-source threshold voltages V.sub.GSF and V.sub.GSN of the flipped gate transistor M.sub.FGD and to the drain of the normally gated transistor M.sub.NGD as shown by the equations:
R.sub.1=R.sub.3+R.sub.2
V.sub.BANDGAP=V.sub.GSFV.sub.GSN.

(42) The selection of the switches is determined by the following:
M.sub.S0 is ON: V.sub.thr=Vref+Vbandgap+I.sub.2*R3.
M.sub.S1 is ON: V.sub.thr=Vref+Vbandgap+I.sub.2*(R.sub.3+R.sub.21)
M.sub.S2 is ON: V.sub.thr=Vref+Vbandgap+I.sub.2*(R.sub.3+R.sub.21+R.sub.22)
. . .
M.sub.S8 is ON: V.sub.thr=Vref+Vbandgap+I.sub.2*(R.sub.3+R.sub.21+ . . . +R.sub.28)
M.sub.SX is ON: V.sub.thf=V.sub.thrV.sub.HYS
V.sub.HYS=R.sub.3*(I.sub.2+(V.sub.REFV.sub.GSN)/R.sub.1) Where: M.sub.S0, . . . , M.sub.S7, and M.sub.S are the multiple switch transistors; V.sub.THR is the rising threshold voltage level setting; V.sub.THF is the falling threshold voltage level setting; V.sub.REF is the reference voltage; VGSN is the gate-to-source threshold voltage.

(43) FIG. 8 is a plot of simulations of the third implementation of a UVLO circuit of FIG. 7 showing the output voltage of the UVLO circuit of FIG. 7 versus the voltage level of the power supply voltage source V.sub.dd for nine different falling threshold voltage level settings V.sub.THF0, . . . , V.sub.THF0. Each gate of the multiple switch transistors M.sub.S0, . . . , M.sub.S7, and M.sub.S8 is connected to the output y0, . . . , y7, and y8 of the decoder circuit DCDR. The decoder circuit DCDR receives the decode select word DSEL that determines which output y0, . . . , y7, and y8 of the decoder circuit DCDR is activated to turn on one of the multiple switch transistors M.sub.S0, . . . , M.sub.S7, and M.sub.S8 for determining one of the falling threshold voltage level settings V.sub.THF0, . . . , V.sub.THF0. The settings y0, . . . , y7, and y8 of the decoder circuit DCDR activate one of the multiple serially connected resistors R.sub.21, . . . , R.sub.2n that form the resistor R.sub.2 to establish the path through the resistor R.sub.3 and the multiple serially connected resistors R.sub.21, . . . , R.sub.2n that determine the deactivation level of the falling threshold voltage level settings V.sub.THF0, . . . , V.sub.THF0 and the activation level of the raising threshold voltage level settings V.sub.THR0, . . . , V.sub.THr0 for turning off the electronic device or turning on the electronic device.

(44) FIG. 9 is a plot of simulations of the third implementation of a UVLO circuit of FIG. 6a showing the transient response of the UVLO circuit of FIG. 6a over time. The power supply voltage source V.sub.dd raises from a 0V level at the time 0.0 ms to the voltage level of raising threshold voltage level V.sub.THR at the time 2.8 ms. At that time, the voltage at the gate of the flipped gate transistor M.sub.FGD reaches the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD. The flipped gate transistor M.sub.FGD is turned on and the output DOUT of the inverter INV1 changes from the logical 0 to the logical 1 and the voltage V.sub.DOUT raises to the voltage of approximately 2.6V or approximately the voltage level of the power supply voltage source V.sub.dd. With the output of the output DOUT of the inverter INV1 being at the logical 1, the electronic device is activated.

(45) At the time 5.0 ms, the power supply voltage source V.sub.dd begins to fall from its maximum voltage of 4.75V to the voltage level of falling threshold voltage level V.sub.THF at the time 7.5 ms. At that time, the voltage at the gate of the flipped gate transistor M.sub.FGD reaches the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD. The flipped gate transistor M.sub.FGD is turned off and the output DOUT of the inverter INV1 changes from the logical 1 to the logical 0 and the voltage V.sub.DOUT falls to the voltage of approximately 0V or approximately the voltage level of the ground reference voltage source V.sub.ss. With the output of the output DOUT of the inverter INV1 being at the logical 0, the electronic device is deactivated. The power supply voltage source V.sub.dd continues to fall until the power supply voltage source V.sub.dd is at the 0V level.

(46) FIG. 10 is a flow chart illustrating the operation of UVLO embodying the principles of the present disclosure. Referring to FIGS. 5 and 10, when an electronic device is totally deactivated, the power supply voltage source V.sub.dd is at the 0V level and the UVLO circuit is not functional. Once the power supply voltage source V.sub.dd begins to power up from the 0V level the electronic device will be turned off. Alternately, if the electronic device is turned on, the power supply voltage source V.sub.dd is activated and the electronic device is turned on. In the method of operation, the state of the electronic device is determined (Box 200). If the electronic device is not activated or turned off, the power supply voltage source V.sub.dd, the UVLO circuit is also deactivated and the output of the inverter buffer INV1 set (Box 205) to the logical 0 and the electronic device is (Box 210) turned off. The threshold voltage level of the power supply voltage source V.sub.dd is set (Box 215) to the raising threshold voltage level V.sub.THR. The raising threshold voltage level V.sub.THR is the voltage level of the power supply voltage source V.sub.dd at the input of the UVLO circuit. The voltage divider/current converter VIC is configured such that the voltage at the gate of the flipped gate transistor M.sub.FGD is the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD when the voltage level of the power supply voltage source V.sub.dd is at the raising threshold voltage level V.sub.THR. The voltage level of the power supply voltage source V.sub.dd is compared (Box 220) with the raising threshold voltage level V.sub.THR. If the voltage level of the power supply voltage source V.sub.dd is less than the raising threshold voltage level V.sub.THR, the comparison (Box 220) continues.

(47) When the power supply voltage source V.sub.dd is becomes greater than the raising threshold voltage level V.sub.THR, the voltage level at the gate of the flipped gate transistor M.sub.FGD is greater than its threshold voltage level V.sub.GSF and the flipped gate transistor M.sub.FGD is turned on and the output of the inverter buffer INV1 is activated (Box 225) to the logical 1 and the electronic device is turned on (Box 230). The threshold voltage level of the power supply voltage source V.sub.dd is set (Box 235) to the falling threshold voltage level V.sub.THF. The falling threshold voltage level V.sub.THF is the voltage level of the power supply voltage source V.sub.dd at the input of the UVLO circuit. The voltage divider/current converter VIC is configured such that the voltage at the gate of the flipped gate transistor M.sub.FGD is the threshold voltage V.sub.GSF of the flipped gate transistor M.sub.FGD when the voltage level of the power supply voltage source V.sub.dd is at the falling threshold voltage level V.sub.THF.

(48) The voltage level of the power supply voltage source V.sub.dd is compared (Box 240) with the falling threshold voltage level V.sub.THFR. If the voltage level of the power supply voltage source V.sub.dd is greater than the falling threshold voltage level V.sub.THF, the comparison (Box 240) continues.

(49) When the power supply voltage source V.sub.dd is becomes less than the falling threshold voltage level V.sub.THF, the voltage level at the gate of the flipped gate transistor M.sub.FGD is less than its threshold voltage level V.sub.GSF and the flipped gate transistor M.sub.FGD is turned off and the output of the inverter buffer INV1 is deactivated (Box 205) to the logical 0 and the electronic device is turned on (Box 210). The process then continues until the power supply voltage source V.sub.dd is totally deactivated and there is 0V and the whole electronic device is turned off.

(50) While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.