Device and method for generating random numbers

Abstract

The invention relates to a device for generating random numbers, comprising a pair of memristors. The pair of memristors comprises a first and a second memristor, each memristor of the pair in turn comprises a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode. Each memristor is operatively connected to an output terminal by means of its bottom electrode. A control logic is connected to the memristors for applying suitable voltages necessary to determine a change of resistance in at least one memristor of the pair.

Claims

1. A device for generating random numbers, comprising: a pair of memristors comprising a first and a second memristor, each memristor of the pair comprising a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode; an output terminal operatively connected to said pair of memristors; and a control logic adapted to apply a transition voltage at the ends of each memristor in order to cause a change of resistance in the memristor; wherein each memristor is operatively connected to the output terminal by means of its bottom electrode; and and wherein the control logic is configured to: fix the voltage of the output terminal to a predetermined value and apply said transition voltage to cause a change of resistance in at least one memristor of the pair, leave the voltage at said output terminal floating and apply to the top electrodes of said first and second memristor two read voltages having opposite sign and amplitude lower than said transition voltage.

2. A device according to claim 1, wherein the transition voltage is a SET voltage such to cause a transition from high resistance to low resistance in said at least one memristor of the pair, and wherein the control logic is further configured to apply a RESET voltage to said pair of memristors such to cause a transition from low to high resistance in both the memristors of the pair, the control logic being adapted to apply said SET voltage after said RESET voltage.

3. A device according to claim 1, wherein the transition voltage is a RESET voltage such to cause a transition from low resistance to high resistance in both the memristors of the pair, and wherein the control logic is further configured to apply a SET voltage to said pair of memristors such to cause a transition from high to low resistance in at least one memristor of the pair, said SET voltage being applied before said RESET voltage.

4. A device according to claim 1, further comprising a comparator circuit comprising a first and a second input terminal, wherein the first input terminal is connected to the output terminal and wherein the second input terminal is grounded.

5. A device according to claim 1, wherein the first and the second memristor are comprised in a respective cell of a RRAM, said respective cell comprising a memristor whose bottom electrode is connected to the drain of a cell transistor, said cell transistor comprising a source electrode connected to the output terminal.

6. A device according to claim 1, further comprising a pilot transistor whose source electrode is grounded and whose drain electrode is connected to the output terminal, the control logic being operatively connected to the gate of the pilot transistor to command its switch on and/or switch off.

7. A method for generating random numbers, wherein a random number is generated by using a statistical variation of an electric resistance of at least one memristor of a pair of memristors, said pair of memristors comprising a first and a second memristor, each memristor of the pair comprising a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode, the method comprising: causing a change of resistance in at least one memristor of the pair by applying to said at least one memristor a transition voltage; reading a voltage value at an output terminal operatively connected to said pair of memristors; and associating a number to the voltage value of the output terminal; wherein each memristor of the pair is operatively connected to the output terminal by means of its bottom electrode; and further comprising: fixing the voltage of the output terminal to a predetermined value and applying said transition voltage to cause a change of resistance in at least one memristor of the pair; and leaving the voltage at said output terminal floating and apply to the top electrodes of said first and second memristor two read voltages having opposite sign and amplitude lower than said transition voltage.

8. A method according to claim 7, wherein the transition voltage is a SET voltage such to cause a transition from high resistance to low resistance in said at least one memristor of the pair, and wherein the method further comprises the step of applying a RESET voltage to said pair of memristors such to cause a transition from low to high resistance in both the memristors of the pair, said SET voltage being applied after said RESET voltage.

9. A method according to claim 7, wherein the transition voltage is a RESET voltage such to cause a transition from low resistance to high resistance in both the memristors of the pair, and wherein the method further comprises the step of applying a SET voltage to said pair of memristors such to cause a transition from high to low resistance in at least one memristor of the pair, said SET voltage being applied before said RESET voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be described here below with reference to not limitative examples, provided by way of example and not as a limitation in the annexed drawings. These drawings show different aspects and embodiments of the present invention and, where appropriate, reference numerals showing like structures, components, materials and/or elements in different figures are denoted by like reference numerals.

(2) FIG. 1 is a device for generating random numbers (RNG) and the sequence of voltage pulses that have to be applied for RNG.

(3) FIG. 2 is a memristor and its voltage-current characteristics.

(4) FIG. 3 is a flow chart of a RNG method.

(5) FIG. 4 is a variant of the device of FIG. 1 and the sequence of voltage pulses that have to be applied for RNG.

(6) FIG. 5 schematically is a cell of a RRAM.

(7) FIG. 6 is the experimental results obtained by a RNG cycle implemented by the device of FIG. 4.

(8) FIG. 7 is a sequence of voltage pulses that, once applied to the device of FIG. 4, allow a different RNG method to be implemented.

(9) FIG. 8 is the experimental results obtained by a RNG cycle implemented by the device of FIG. 4 and the method of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

(10) While the invention is susceptible of various modifications and alternative constructions, some disclosed embodiments are shown in the drawings and will be described in details herein below. It should be understood, however, that there is no intention to limit the invention to the specific disclosed embodiment but, on the contrary, the invention intends to cover all the modifications, alternative constructions and equivalents that fall within the scope of the invention as defined in the claims.

(11) The use of for example, etc., or denotes non-exclusive alternatives without limitation, unless otherwise noted. The use of comprises means comprises, but not limited to, unless otherwise noted.

(12) FIG. 1(a) shows a device 1 for generating random numbers, comprising a generating section 10 and a control logic 11 (for example a microprocessor or a FPGA) generating the necessary signals for controlling the generating section 10.

(13) The generating section comprises two memristors (P and Q) connected in parallel to the input terminal of a comparator 12 whose other input terminal is grounded.

(14) The word memristor means a variable resistance device whose resistance value can be changed by applying a suitable voltage at its ends.

(15) An example of a memristor is shown in FIG. 2(a), it comprises a switching layer (SL) of HfO.sub.2 (or another oxide) with a TiN bottom electrode (BE) and a Ti top electrode (TE), that acts as oxygen exchange layer for generating defects at TE side.

(16) Such as shown in FIG. 2b, the application of a positive voltage (that is from BE to TE) V.sub.set at the ends of the memristor, causes SET transition, where switching occurs from high resistance state (HRS) to low resistance state (LRS), while the application of a negative voltage V.sub.reset causes RESET transition from LRS to HRS. Each memristor P and Q therefore has a variable resistance that can be programmed by causing a SET or RESET transition.

(17) In the example described here, the memristors have a SET voltage V.sub.SET=1.5V and a RESET voltage V.sub.RESET=0.9V for a typical ramp rate of 10.sup.3 V/s. A compliance current (limitation) IC=50 A was used during the SET transition by applying a relatively low gate voltage. A maximum negative voltage V.sub.stop of 1.5V is applied during the reset sweep.

(18) With reference again to the device of FIG. 1(a), for random number generation, the control logic 11 applies voltage signals to the inputs of the generating section 10 according to a method providing three steps that are cyclically repeated and are shown herein below with reference to FIG. 1b and FIG. 3.

(19) Firstly the method provides to apply (301) a positive voltage to the top electrode (TE) of P and Q to cause SET transition. In the example of FIG. 1 the control logic 11 keeps to ground the voltage V.sub.out measured at the positive input terminal of the comparator 12 and applies to the ends of the memristors P and Q a triangular voltage pulse (V.sub.P, V.sub.Q) of 1 ms in duration and amplitude higher than V.sub.SET.

(20) Then, step 302, a negative voltage V.sub.RESET is applied to top electrodes of P and Q to cause the RESET transition in both the variable resistances R.sub.P and R.sub.Q. Also in this case, for the reset voltage a triangular pulse is applied of 1 ms in duration and an amplitude higher than (in absolute value) V.sub.RESET.

(21) Finally, step 303, the step reading the random bit is performed. In this step the control logic 11 is disconnected from the input terminal of the comparator to which memristors P and Q are connected and applies to the top electrode TE of the transistor P a voltage V.sub.P=+V.sub.Read and, to the electrode TE of Q a voltage V.sub.Q=V.sub.Read, where 2V.sub.Read<V.sub.Set. V.sub.Read can be for example equal to 0.3 V, therefore it is not enough for causing a change of resistance in the memristors. In the example of FIG. 1(b), also for the reading a triangular pulse is applied with 1 ms in duration and amplitude V.sub.read.

(22) Now the input node of the comparator 12 has a voltage that will be slightly positive or negative depending on whether the resistance of P is smaller or greater than the resistance of Q, respectively. Therefore it is possible to assign a logic value of 1 or 0 to the value of the measured voltage of V.sub.OUT.

(23) This method uses the characteristic of memristors that, statistically, are never with the same HRS resistance after SET and RESET process. As a result of the relatively high statistical variation of HRS resistance, V.sub.out randomly changes from one to another reading cycle, thus acting as an output bit value in the RNG method. In this arrangement, the variation in HRS resistance acts as entropy source for the RNG method.

(24) The output of the analog comparator (12) is used to digitally regenerate V.sub.out.

(25) FIG. 4(a) shows a variant of the circuit of FIG. 1, that uses two cells 13 and 14 of a RRAM with 1T1R structure.

(26) Each cell, shown in FIG. 4(b), comprises a memristor of the type described above with reference to FIG. 2(a), connected to the drain of a cell transistor 20, for example a MOSFET.

(27) The source of the cell transistor 20 is connected to the positive input of the comparator 12, thus by applying a sufficiently high gate voltage V.sub.G2 it is possible to short circuit the transistor and to connect the positive input of the comparator 12 to the bottom electrode BE of each memristor P, Q.

(28) In the device of FIG. 4, the generating section 10 comprises a transistor 15, particularly a MOSFET, whose drain is connected to the positive electrode of the comparator 12 and whose source is grounded.

(29) In order to implement the method of FIG. 3, the control logic 11 controls voltages V.sub.P, V.sub.Q, V.sub.G1 and V.sub.G2 such as shown in FIG. 4(b).

(30) During SET phase, V.sub.G1 is kept high (for example equal to the power voltage of the circuit V.sub.DD) in order to ground the voltage V.sub.OUT. Cell transistors 20 are switched on by applying a voltage V.sub.G2 just above threshold, while to the top electrodes TE of P and Q a positive voltage equal to or higher than voltage V.sub.SET is applied. In the example shown here V.sub.P and V.sub.Q are brought to the power voltage VDD, higher than threshold one. Both the memristors therefore perform a SET transition and switch to low resistance value (LRS). In the example described herein triangular voltage pulses of 1 ms in duration are applied to the electrodes TE of P and Q, however it is possible to use different waveforms (e.g. rectangular or parabolic) and of different duration.

(31) Then during the reset phase the transistor 15 is short circuited, meaning that V.sub.G1 is kept high (for example equal to the power voltage of the circuit V.sub.DD) in order to ground the voltage V.sub.OUT. A similar control is performed on V.sub.G2 to be sure that the drain source voltage of the transistor is as near as possible to zero and that all the voltage V.sub.P and V.sub.Q (negative and equal, or in higher modulus, to V.sub.RESET) drops at the ends of the respective memristor P and Q, that therefore switches to high resistance state (HRS).

(32) During reading, the transistor 15 is switched off (V.sub.G1=0), such to leave its drain voltage as floating. On the contrary V.sub.G2 is kept high, to be sure that substantially all voltages V.sub.P and V.sub.Q applied to positive electrodes of P and Q are between such electrodes and the positive input of the comparator 12. As said above with reference to FIG. 3, in this step the voltages V.sub.P and V.sub.Q are of equal modulus and opposite sign: V.sub.P=Vread and V.sub.Q=Vread. The voltage V.sub.OUT therefore will take a positive or negative sign depending on the value of the resistances of P and Q; the corresponding voltage V.sub.OUT2 therefore will be equal to the power voltage VDD or to ground voltage, thus determining a bit with a logic value 1 or 0.

(33) In order to demonstrate the efficiency of the device and of the RNG method described above, FIG. 6 shows the results of some tests performed with the circuit of FIG. 4(a).

(34) FIG. 6(a) shows the cumulative distribution of resistance R.sub.P of P and of resistance R.sub.Q of Q, measured after SET and RESET transitions.

(35) RNG method was tested during 1000 cycles, this provides a sufficient statistical accuracy with a negligible degradation of the device.

(36) Distributions R.sub.P and R.sub.Q are almost identical both in LRS and HRS, which is the key to reach an unbiased RNG of true random numbers.

(37) FIG. 6(b) shows experimental and calculated distributions of V.sub.out obtained during reading. The measured distribution of V.sub.out follows a bimodal form with probability transition of 50%.

(38) As it can be observed still in FIG. 6(b), the bimodal distribution was improved by introducing in the circuit of FIG. 4(a) an analog comparator (12), that allows a V.sub.out2 to be equally distributed on values +V.sub.max (corresponding to a logic 1) and V.sub.max (corresponding to a logic 0).

(39) The comparator 12 can be replaced by one or more integrated CMOS inverters in an integrated circuit to reduce the area occupied on the chip.

(40) FIG. 6(c) shows voltages V.sub.out and V.sub.out2 measured during 1000 cycles of the RNG method, while FIG. 6(d) shows the corresponding probability density function (PDF) of V.sub.out and V.sub.out2.

(41) FIG. 7 shows a sequence of voltage pulses alternative to the sequence of FIG. 4, that allows, by the same circuit of FIG. 4(a), a RNG method alternative to that of FIG. 3 to be implemented.

(42) According to this method, a triangular voltage pulse of 1 ms in duration and with a value higher than (in absolute value) V.sub.Reset is initially applied to top electrodes (TE) of P and Q. During such step the transistors 15 and 20 are kept switched on with a gate voltage high enough to short circuit drain and source (e.g. V.sub.G1=V.sub.G2=V.sub.DD>>V.sub.DS), such to bring V.sub.out substantially to ground and to cause all the voltage V.sub.P and V.sub.Q to fall on memristors P and Q which therefore switch to HRS.

(43) Then a voltage higher than V.sub.SET (for example VDD) is applied to memristors P and Q which causes a random transition of P or Q to the LRS. In this step the transistor 15 is kept switched on, but with a gate voltage V.sub.G1 slightly higher than threshold, such to operate as a resistance to ground for P and Q. Transistors 20 on the contrary are kept switched on with V.sub.G2 equal to VDD, such to be short circuited. During this step, one of the two transistors switches to LRS; when this happens the potential of its bottom electrode BE and therefore also of V.sub.OUT, follows and gets near VDD, reducing voltage at the ends of both the memristors and thus preventing the other memristor from performing SET transition and from switching to LRS. Thus only one of the two memristors carries out the transition to LRS, the one of the two memristors that due to statistical fluctuations has the smallest transition voltage Vset.

(44) Finally the RNG cycle provides to switch off the transistor 15 (V.sub.G1=0) and to read output voltage V.sub.OUT (or V.sub.OUT2) as shown above for the device of FIG. 1(a), that is by applying a differential voltage (equal to 2V.sub.READ in this embodiment) between the electrodes TE of P and Q. The voltage V.sub.out will have a positive or negative value depending on which of the two memristors has carried out the SET transition.

(45) Since SET transition in P and Q is random, there is no need for any probability tracking circuit, since SET transition is naturally present in a single memristor at each cycle.

(46) FIG. 8(a) shows the bimodal distribution of resistance R resulting for P and Q, which exhibits a bimodal distribution with a HRS/LRS transition at 50%. Calculations were carried out by randomly moving 50% of the samples from the HRS distribution to LRS distribution. FIG. 8(b) shows the correlation plot of R.sub.Q as a function of R.sub.P, indicating complementary states, that is P is always in HRS if Q is in LRS and vice versa. FIG. 8(c) shows the cumulative distribution of V.sub.out and V.sub.out2, the latter being the regenerated output of the CMP. Nice bimodal distributions are noted with smooth and abrupt transitions for V.sub.out and V.sub.out2 respectively. FIGS. 8(d) and 8(e) show V.sub.out and V.sub.out2 as a function of the RNG cycle (d) and the corresponding probability density function PDF (e). Calculations were performed for FIGS. 8(c) and (e), showing a good agreement with data.

(47) In the light of the above mentioned examples it is clear how the invention allows the above objects to be achieved.

(48) It is also clear that the person skilled in the art can make changes to the above examples without for this reason departing from the scope of protection as it results from the annexed claims.

(49) For example, voltage pulses applied to top electrodes (TE) of P and Q can have any shape and duration, for example can have a rectangular or parabolic shape.

(50) Still, the division of the device in the two blocks composed of the generating section 10 and the control logic 11, has to be intended by way of example and not as a limitation. For example the transistor 15 of FIGS. 4 and 7 can be a part of the circuit of the control logic 11.

(51) It has to be noted that teaching of the invention can be applied also to all methods intended to increase entropy of the sequence of random numbers produced by the device 1 of FIGS. 1 and 4. An entropy increase method is any post-processing of raw data, for example a selection of bits according to the Von Neumann algorithm, or any other algorithm intended to modify the sequence or to mix it with another entropy source.

(52) Moreover teaching of the invention can be also applied to all methods intended to pre-condition random number generation devices such to obtain a better functionality (for example a higher cycling life) or for a better generation of random numbers.

(53) It has also to be noted that the memristors that can be used in the device 1 can be of different types; for example all memristors able to change their resistance as a response to the application of pulses are suitable. In the type of usable memristors for example we have: Phase change memory devices (Phase Change Memory, PCM); Unipolar resistive switching devices (unipolar RRAM); Magnetic tunnel junction devices (Magneto-Tunnel Junction, MTJ), such as for example spin-transfer torque memories (STT-RAM) and spin-orbit torque memories (SOT-RAM); Ferromagnetic tunnel junction memories (Ferroelectric Tunnel Junction, FTJ).

(54) According to another embodiment, memristors P and Q of the device 1 can be of different types, such as the case when, for example, one of the two memristors is a bipolar RRAM and the other memristor is a unipolar RRAM.

(55) With reference to the memristors of the device, 1, memristor devices wherein resistance is modified for a limited time can be also used, such as for example threshold switching devices where LRS spontaneously switches to HRS after SET transition. Such devices for example can contain materials such as: insulator-metal transition metal oxides, such as vanadium oxide and niobium oxide; amorphous chalcogenides, such as for example some alloys of the group TeAsGeSi; insulators such as silicon oxide, or silicon nitride, combined or doped with metals, such as Ag, that exhibit spontaneous transitions from LRS to HRS after set operation.