Voltage detector and voltage detector system

Abstract

A voltage detector comprising: a first voltage reference generator for generating a first voltage reference signal; a second voltage reference generator for generating a second voltage reference signal, wherein the second voltage reference signal is higher than the first voltage reference signal; a trigger, powered by an input signal to the voltage detector, and having an input for receiving either the first or second voltage reference signal and an output for generating a detection signal; and a switch for selectively, connecting the input of the trigger to the first or second voltage reference signal, wherein the switch is operative to connect the input of the trigger to the first voltage reference signal when the detection signal output by the voltage detector is low and is operative to connect the input of the trigger to the second voltage reference signal when the detection signal output by the voltage detector is high, and a voltage detector system for monitoring an input signal and outputting a detection signal when a voltage of the input signal meets a first threshold, the voltage detector system comprising: a first voltage detector having an input for receiving the input signal and an output for outputting a detection signal, wherein the first voltage detector is configured to output the detection signal when the voltage of the input signal meets a first rising input voltage threshold; a second voltage detector having an input for receiving the input signal and an output for outputting a detection signal, wherein the second voltage detector is configured to output the detection signal when the voltage of the input signal meets a second rising input voltage threshold which is higher than the first threshold, wherein the output of the second voltage detector controls a connection between the input signal and the input of the first voltage detector such that when the voltage the input signal meets the second rising input voltage threshold the connection between the input and the input of the first voltage detector is inhibited or disconnected.

Claims

1. A voltage detector comprising: a first voltage reference generator generating a first voltage reference signal; a second voltage reference generator for generating a second voltage reference signal, wherein the first voltage reference signal is higher than the second voltage reference signal; a trigger, powered by an input signal to the voltage detector, and having an input for receiving either the first or second voltage reference signal and an output for generating a detection signal; and a switch for selectively connecting the input of the trigger to the first or second voltage reference signal, wherein: the switch is operative to connect the input of the trigger to the first voltage reference signal when the detection signal output by the trigger is low and is operative to connect the input of the trigger to the second voltage reference signal when the detection signal output by the trigger is high; and the first and second voltage reference generators of the voltage detector each comprise a first transistor, arranged to have a zero gate-source voltage, and a second transistor, connected as a diode, connected in series between the input signal and a common reference, wherein the first transistor has a lower gate threshold than the second transistor; and the voltage detector comprises a third voltage reference generator for generating a third voltage reference signal, wherein the third voltage reference generator is configured to output the third voltage reference signal to the first and second voltage reference generators and the third voltage reference signal sets the body bias of the first transistor of each of the first and second reference generators.

2. A voltage detector according to claim 1, wherein the trigger comprises a PMOS transistor and an NMOS transistor connected so as to form an inverter.

3. A voltage detector according to claim 2 wherein the first and second reference voltage signals produced by the first and second voltage reference generators circuits are low enough to ensure that the inverter is in subthreshold mode when it switches.

4. A voltage detector according to claim 1 wherein the common reference is ground.

5. A voltage detector according to claim 1 comprising one or more buffers between the trigger and the output.

6. A voltage detector system for monitoring an input signal and outputting a detection signal when the voltage of the input signal meets a threshold, the voltage detector system comprising: a first voltage detector having an input for receiving the input signal and an output for outputting a detection signal, wherein the first voltage detector is configured to output the detection signal when the voltage of the input signal meets a first rising input voltage threshold; a second voltage detector having an input for receiving the input signal and an output for outputting a detection signal, wherein the second voltage detector is configured to output the detection signal when the voltage of the input signal meets a second rising input voltage threshold which is higher than the first threshold, wherein the first and/or second voltage detector comprises: a first voltage reference generator for generating a first voltage reference signal; a second voltage reference generator for generating a second voltage reference signal, wherein the first voltage reference signal is higher than the second voltage reference signal; a trigger, powered by an input signal to the voltage detector, and having an input for receiving either the first or second voltage reference signal and an output for generating a detection signal; and a switch for selectively connecting the input of the trigger to the first or second voltage reference signal, wherein: the switch is operative to connect the input of the trigger to the first voltage reference signal when the detection signal output by the trigger is low and is operative to connect the input of the trigger to the second voltage reference signal when the detection signal output by the trigger is high, and wherein the output of the second voltage detector controls a connection between the input signal and the input of the first voltage detector such that when the voltage of the input signal meets the second rising input voltage threshold the connection between the input signal and the input of the first voltage detector is inhibited or disconnected.

7. A voltage detector system according to claim 6 further comprising: a third voltage detector having an input for receiving the input signal and an output for outputting a detection signal, wherein the third voltage detector is configured to output a detection signal when the voltage of the input signal meets a third rising input voltage threshold which is higher than both the first threshold and the second threshold, wherein the output of the third voltage detector controls a connection between the input signal and the input of the second voltage detector such that when the voltage of the input signal meets the third rising input voltage threshold the connection between the input signal and the input of the second voltage detector is inhibited or disconnected.

8. A voltage detector system as claimed in claim 7 wherein the third voltage detector comprises: a first voltage reference generator for generating a first voltage reference signal; a second voltage reference generator for generating a second voltage reference signal, wherein the first voltage reference signal is higher than the second voltage reference signal; a trigger, powered by an input signal to the voltage detector, and having an input for receiving either the first or second voltage reference signal and an output for generating a detection signal, and a switch for selectively connecting the input of the trigger to the first or second voltage reference signal, wherein: the switch is operative to connect the input of the trigger to the first voltage reference signal when the detection signal output by the trigger is low and is operative to connect the input of the trigger to the second voltage reference signal when the detection signal output by the trigger is high.

9. A voltage detection system according to claim 6, wherein the first voltage detector is configured to cease outputting a detection signal when the voltage of the input signal meets a first falling input voltage threshold, wherein the first falling input voltage threshold is lower than the first rising input voltage threshold.

10. A voltage detection system according to claim 6, wherein the second voltage detector is configured to cease outputting a detection signal when the voltage of the input signal meets a second falling input voltage threshold, wherein the second falling input voltage threshold is lower than the second rising input voltage threshold.

11. A voltage detection system according to claim 7, wherein the third voltage detector is configured to cease outputting a detection signal when the voltage of the input signal meets a third falling input voltage threshold, wherein the third falling input voltage threshold is lower than the third rising input voltage threshold.

12. A voltage detection system according to claim 6 further comprising an open drain output stage, the output stage comprising a plurality of MOSFET devices, each MOSFET device having: a gate terminal connected to an output of a respective one of the voltage detectors; a source terminal connected to a common reference; and a drain terminal connected to an output terminal of the output stage.

13. A voltage detection system according to claim 9 further comprising an open drain output stage, the output stage comprising a plurality of MOSFET devices, each MOSFET device having: a gate terminal connected to an output of a respective one of the voltage detectors; a source terminal connected to a common reference; and a drain terminal connected to an output terminal of the output stage.

14. A voltage detection system according to claim 13, wherein a gate threshold of each MOSFET device is lower than the rising input threshold and the falling input threshold of the respective voltage detector to which the MOSFET device is connected.

15. A voltage detection system according to claim 10 further comprising an open drain output stage, the output stage comprising a plurality of MOSFET devices, each MOSFET device having: a gate terminal connected to an output of a respective one of the voltage detectors; a source terminal connected to a common reference; and a drain terminal connected to an output terminal of the output stage.

16. A voltage detection system according to claim 15, wherein a gate threshold of each MOSFET device is lower than the rising input threshold and the falling input threshold of the respective voltage detector to which the MOSFET device is connected.

17. A voltage detection system according to claim 11 further comprising an open drain output stage, the output stage comprising a plurality of MOSFET devices, each MOSFET device having: a gate terminal connected to an output of a respective one of the voltage detectors; a source terminal connected to a common reference; and a drain terminal connected to an output terminal of the output stage.

18. A voltage detection system according to claim 17, wherein a gate threshold of each MOSFET device is lower than the rising input threshold and the falling input threshold of the respective voltage detector to which the MOSFET device is connected.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will now be described, strictly by way of example only, with reference to the accompanying drawings, of which:

(2) FIG. 1 is a schematic representation of a sensor system that is powered by intermittent sources;

(3) FIG. 2 illustrates the operation of a commercially available voltage detector as used in the circuit of FIG. 1;

(4) FIG. 3 illustrates the operation of a basic power on reset (POR) pulse generator circuit;

(5) FIG. 4 illustrates the ideal behaviour of a POR circuit;

(6) FIG. 5 is a schematic representation of a system architecture of a system incorporating a plurality of voltage detectors;

(7) FIG. 6 is a timing diagram illustrating the operation of the system of FIG. 5;

(8) FIG. 7 is a schematic representation of a voltage detector for use in the system of FIG. 5;

(9) FIG. 8 is a timing diagram illustrating the operation of the voltage detector of FIG. 6;

(10) FIG. 9 is a schematic representation of a circuit for implementing voltage reference circuits in the voltage detector circuit of FIG. 6;

(11) FIG. 10 is a graph illustrating start-up behaviour of the circuit of FIG. 6;

(12) FIG. 11 is a schematic representation of conventional low power body biasing schemes;

(13) FIG. 12 is a schematic representation of the circuit of FIG. 9, with an additional body-bias generator;

(14) FIG. 13 is a schematic diagram showing a body-bias circuit; and

(15) FIG. 14 is a schematic representation of a power-gating circuit suitable for use in the architecture of FIG. 5.

DESCRIPTION OF THE EMBODIMENTS

(16) FIG. 5 illustrates a voltage detection system which combines all the desired properties of voltage detectors, namely high maximum input voltage, a low voltage detection threshold and low quiescent power consumption. The system, shown generally at 100 in FIG. 1, includes a power gating stage 120, a voltage detection stage 140 and an output stage 160.

(17) The voltage detection stage 140 includes a first voltage detector 142 which is configured to detect input voltages in a high voltage range (e.g. in the range 2.8 volts to 20 volts), a second voltage detector 144 which is configured to detect input voltages in a medium voltage range (e.g. 0.6 volts to 2.8 volts) and a third voltage detector 146 which is configured to detect input voltages in a low voltage range (e.g. 0.45 volts to 0.6 volts). This arrangement of three voltage detectors ensures that the voltage detection system 100 is able to operate in a wide input voltage range, therefore facilitating the capture of energy from pulses with a wide power range.

(18) The power gating stage 120 is configured to prevent potentially damaging input voltages from reaching the second and third voltage detectors 144, 146, and is arranged such that the first voltage detector 142 gates the second and third voltage detectors 144, 146 and the second voltage detector 144 gates the third voltage detector 146. As can be seen in FIG. 5, the voltage input V.sub.IN of the system 100 is connected to an input V.sub.IN(H) of the first voltage detector 142. An output V.sub.OUT(H) of the first voltage detector 142 is connected to the gate terminal of a first P-channel MOSFET 122. The source terminal of the first P-channel MOSFET is connected to the voltage input V.sub.IN and the drain terminal of the first P-channel MOSFET 122 is connected to an input V.sub.IN(M) of the second voltage detector 144, and, via a second P-channel MOSFET 124, to an input V.sub.IN(L) of the third voltage detector 146.

(19) When the first voltage detector 142 detects an input voltage in the high voltage range, its output V.sub.OUT(H) goes high, causing the first P-channel MOSFET 122 to switch off, thereby restricting or preventing the input voltage from reaching the second voltage detector 144 or the third voltage detector 146.

(20) Similarly, the gate terminal of the second P-channel MOSFET 124 is connected to an output V.sub.OUT(m) of the second voltage detector 144, such that when the second voltage detector 144 detects an input voltage in the medium voltage range, its output V.sub.OUT(M) goes high, causing the second P-channel MOSFET 124 to switch off, thereby restricting or preventing the input voltage from reaching the third voltage detector 146.

(21) The output stage 160 of the voltage detection system 100 includes (in the illustrated example) first, second and third N-channel MOSFETS 162, 164, 166. The gate terminal of the first N-channel MOSFET 162 is connected to the output V.sub.OUT(H) of the first voltage detector 142, whilst the gate terminal of the second N-channel MOSFET 164 is connected to the output V.sub.OUT(M) of the second voltage detector 144 and the output of the third N-channel MOSFET 166 is connected to the output V.sub.OUT(L) of the third voltage detector 146. The drain terminals of the first, second and third N-channel MOSFETs 162, 164, 166 are all connected to an open-drain output terminal V.sub.OD of the output stage 160, whilst the source terminals of the first, second and third N-channel MOSFETs 162, 164, 166 are all connected to ground. Accordingly, if any one of the first, second or third voltage detectors 142, 144, 146 is triggered, the open drain output V.sub.OD of the output stage 160 will be activated.

(22) FIG. 6 is a timing diagram illustrating the operation of the circuit of FIG. 5. The input voltage V.sub.IN is shown as a trapezoidal pulse. As the rising edge of this pulse reaches the voltage detection threshold of the third (low voltage range) voltage detector 146, the third voltage detector 146 turns the third N-channel MOSFET 166 on, activating the system's output V.sub.OD. When the input voltage V.sub.IN reaches the voltage detection threshold of the second (medium voltage range) voltage detector 144, the second voltage detector 144 switches on the second N-channel MOSFET 164, and power-gates off the third voltage detector 146, thus protecting it from a further rise in V.sub.IN, and causing the third N-channel MOSFET 166 to be switched off. As V.sub.IN reaches the voltage detection threshold of the first (high voltage range) voltage detector 142, the first N-channel MOSFET 162 is switched on, and both the second and third voltage detectors 144, 146 are disconnected from the input (or at least the connection restricted), resulting in the turning off of the second N-channel MOSFET 164. The first voltage detector 142 remains active until the input voltage drops below its voltage detection threshold, which leads to the second voltage detector 144 being powered on. A further fall in the input voltage activates the third voltage detector 146.

(23) The thresholds at which the voltage detectors 142, 144, 146 switch on in response to a rising input voltage may be different from (higher than) the thresholds at which the voltage detectors 142, 144, 146 switch off in response to a falling input voltage, in order to provide hysteresis and thus avoid system oscillation. The overall result is a continuous activation of the open-drain output V.sub.OD for the duration of the input pulse. To ensure seamless operation of the voltage detection system 100, the threshold voltage of each MOSFET device 162, 164, 166 should be lower than the detection thresholds at which the respective voltage detectors 142, 144, 146 switch on in response to a rising input voltage and the thresholds at which the respective voltage detectors 142, 144, 146 switch off in response to a falling input voltage.

(24) This illustrates the reason for using an open-drain output. When activated, the voltage outputs V.sub.OUT(H), V.sub.OUT(M) and V.sub.OUT(L) of the voltage detectors 142, 144, 146 are at the same potential as their corresponding inputs V.sub.IN(H), V.sub.IN(M) and V.sub.IN(L). Since the voltage detector system 100 will interface to other CMOS devices with much lower maximum allowable voltages, V.sub.OUT(H) and V.sub.OUT(M) cannot be used as the output of the overall system. The open drain output stage allows the voltage detector system 100 to output a signal that is usable by, and not damaging to, an external device.

(25) FIG. 6 also illustrates the profile of the total quiescent current I.sub.IN of the voltage detector system 100. I.sub.IN is zero when the input voltage V.sub.IN is zero, and on a rising input voltage the current increases from 42 pA at 0.2V (below the voltage detection threshold of the third voltage detector 146) to 83 pA at V.sub.IN=1 V (above the detection threshold of the second voltage detector 144), and to around 236 pA at V.sub.IN=5V (above the detection threshold of the first voltage detector 142), with current surges occurring at the activation points of each of the three voltage detectors 142, 144, 146. The measured total energy loss per transition caused by static current when an input voltage rises from 0 to 2.8V, a voltage slightly higher than the high detection threshold (2.8V) with two typical gradients of 1V/s and 100V/s respectively are 788 pJ and 7.9 pJ respectively. This is lower than prior art voltage detection circuits, which contain circuits that, for a given rail voltage, continuously consume quiescent current. An alternative version of the voltage detector system 100 in which the third voltage detector 144 is disabled draws 1.2 pA at 0.2V, around 6 pA at 1V and 111 pA at 5V. Its total energy consumption at 1V/s and 100V/s transition from 0 to 2.8V of the input voltage is 229 pJ and 23 pJ respectively.

(26) FIG. 7 is a schematic diagram illustrating a voltage detector for use in the voltage detector system 100 shown in FIG. 5, to form the first, second and/or third voltage detector 142, 144, 146 used in the voltage detector system 100.

(27) The voltage detector, shown generally at 300 in FIG. 7, provides a programmable trigger threshold that is not fixed by the process technology chosen. The detection threshold and hysteresis can be set, at the time of circuit design, to a desired value. This is desirable for under-voltage-lockout circuits that activate other circuits in a specific input voltage band.

(28) The voltage detector 300 has a trigger stage 310 which is powered by the input signal V.sub.IN. The trigger stage 310 comprises an inverter formed by a transistor pair consisting of a PMOS transistor 312 (labelled MP1 in FIG. 7) and an NMOS transistor 314 (labelled MN1 in FIG. 7), followed by two inverter buffer stages 320, 330, which drive an open-drain output switch 340. The voltage detector 300 also includes a first ultra-low-power voltage reference circuit 350 and a second ultra-low-power voltage reference circuit 360, which generate, respectively, a fixed higher reference voltage V.sub.ref_H and a lower voltage V.sub.ref_L. The body terminal voltages V.sub.ref_BB of the first and second ultra-low-power voltage reference circuits 350, 360 are shown in FIG. 7 to be controlled by another voltage reference. This other voltage reference may be, for example, a further reference generator block 370 with output V.sub.ref_BB. Alternatively, two reference generator blocks could be provided, one for each of the first and second ultra-low-power voltage reference circuits 350, 360. As a further alternative, the V.sub.ref_BB inputs to the high and low voltage reference blocks could be provided by nodes internal to these blocks themselves (self-biased blocks). The self-biased version will now be discussed.

(29) Depending on the rise and fall of the input voltage YIN, V.sub.ref_H and V.sub.ref_L are multiplexed by a switch 380 to a single reference input V.sub.ref to the gate of the trigger stage 310. As shown in FIG. 7, when the output signal V.sub.OUT of the voltage detector 300 is low, the switch 380 connects the output of the first ultra-low-power voltage reference circuit 350 (i.e. the higher reference voltage V.sub.ref_H) to the input of the trigger stage 310, whilst when the output signal V.sub.OUT of the voltage detector 300 is high, the switch 380 connects the output of the second ultra-low-power voltage reference circuit 360 (i.e. the lower reference voltage V.sub.ref_L) to the input of the trigger stage 310.

(30) The two reference voltages V.sub.ref_H and V.sub.ref_L, along with the relative sizing of the PMOS and NMOS transistors 312, 314 which make up the trigger stage 310, determine the different rise and fall detection thresholds (V.sub.th_rise and V.sub.th_fall) of the voltage detector 300, to provide detection hysteresis. The detection (trigger) thresholds are determined by equating the current I.sub.trigger through the PMOS transistor 312 and through the NMOS transistor 314, when the input V.sub.IN rises to V.sub.th_rise and falls to V.sub.th_fall (given that the two transistors 312 and 314 operate in subthreshold and in saturation):

(31) $\begin{array}{cc}{I}_{\mathrm{trigger}\left(\mathrm{rise}\right)}=K_p\left(n-1\right)V_T^2{\exp }^{\left(\frac{V_{\mathrm{th}\_\mathrm{rise}}-V_{\mathrm{ref}\_H}-.Math.V_{\mathrm{THp}}.Math.}{{\mathrm{nV}}_T}\right)}=K_n\left(n-1\right)V_T^2{\exp }^{\left(\frac{V_{\mathrm{ref}\_H}-V_{\mathrm{THn}}}{{\mathrm{nV}}_T}\right)}& \mathrm{Equation}\left(1\right)\\ I_{\mathrm{trigger}\left(\mathrm{fall}\right)}=K_p\left(n-1\right)V_T^2{\exp }^{\left(\frac{V_{\mathrm{th}\_\mathrm{fall}}-V_{\mathrm{ref}\_L}-.Math.V_{\mathrm{THp}}.Math.}{{\mathrm{nV}}_T}\right)}=K_n\left(n-1\right)V_T^2{\exp }^{\left(\frac{V_{\mathrm{ref}\_L}-V_{\mathrm{THn}}}{{\mathrm{nV}}_T}\right)}& \mathrm{Equation}\left(2\right)\end{array}$

(32) where V.sub.THp and V.sub.THn are respectively the gate thresholds of the PMOS transistor 312 and the NMOS transistor 314 of the trigger 310 in FIG. 7. K.sub.p=.sub.pC.sub.ox.Math.(W.sub.1/L.sub.1) and K.sub.n=.sub.nC.sub.ox.Math.(W.sub.2/L.sub.2) are their gain factors ( is mobility, C.sub.ox is gate oxide capacitance per unit area, and W is transistor width and L is transistor length); n is the subthreshold slope factor (n=1+C.sub.d/C.sub.ox where C.sub.d is depletion capacitance, and assuming the n difference between PMOS and NMOS is small); V.sub.T is thermal voltage (26 mV). The detection hysteresis is V.sub.th_riseV.sub.th_fall=2(V.sub.ref_HV.sub.ref_L).

(33) From (1) and (2), analytical solutions for V.sub.th_rise and V.sub.th_fall are
V.sub.th_rise=(|V.sub.THp|V.sub.THn)n.Math.V.sub.T ln(K.sub.p/K.sub.n)+2V.sub.ref_HEquation (3)
V.sub.th_fall=(|V.sub.THp|V.sub.THn)n.Math.V.sub.T ln(K.sub.p/K.sub.n)+2V.sub.ref_LEquation (4)

(34) By selecting width (W) and length (L) of the PMOS transistor 312 and the NMOS transistor 314 appropriately, the first and second terms in (3) and (4) can be set to cancel out and achieve V.sub.th_rise=2V.sub.ref_H and V.sub.th_rise=2V.sub.ref_L. Therefore, controlling the detector thresholds and hysteresis only requires the changing of the two reference voltages V.sub.ref_H and V.sub.ref_L.

(35) The operation of the voltage detector 300 is illustrated in FIG. 8. Initially, the two reference voltages V.sub.ref_H and V.sub.ref_L and the output V.sub.ref_BB of a third reference generator (which, as explained above, may be the further reference generator block 370) rise as V.sub.IN increases, and then settle to three different steady-state levels.

(36) During the settling time (to), V.sub.OUT stays low so that V.sub.ref follows V.sub.ref_H via the multiplexer 380. When V.sub.IN rises to V.sub.th_rise (=2V.sub.ref_H) at t.sub.1, the PMOS transistor 312 is turned on, and V.sub.OUT is thus pulled up to V.sub.IN. Meanwhile, the multiplexer 380 switches V.sub.ref from V.sub.ref_H to V.sub.ref_L until V.sub.IN drops to V.sub.th_fall (=2V.sub.ref_L). Then V.sub.OUT goes low and V.sub.ref switches back to V.sub.ref_H for the next incoming input pulse.

(37) FIG. 9 is a schematic representation of a circuit for implementing the first and second voltage reference circuits 350, 360 of FIG. 8. The circuit, shown generally at 400 consists of two stacked transistors 410, 420 with different gate thresholds V.sub.TH. A first one 410 of the stacked transistors has a lower V.sub.TH and zero gate-source voltage, whilst a second one 420 of the stacked transistors has higher V.sub.TH and is configured as a diode-connected transistor. At steady-state the circuit consumes only pico-amperes of current.

(38) A shortcoming of the circuit 400 is that it is relatively slow to reach a steady-state output during a rising input voltage V.sub.IN. For fast rises of V.sub.IN, this leads to the reference voltages not having been established by the time the input voltage reaches the desired detection threshold voltage. The circuit 400 therefore triggers too soon. The reason for the long start-up time is the circuit's extremely low current that is charging parasitic capacitors.

(39) It is possible to increase the speed with which the circuit 400 reaches a steady state output. This involves increasing the current through the low V.sub.TH transistor 410 relative to that flowing in the high V.sub.TH transistor 420 of FIG. 9. The difference in the currents, the output current (shown as LOUT in FIG. 9), determines how fast the output parasitic capacitor is charged. However, this is done by changing transistor sizes, which, in turn, changes the output parasitic capacitance (affecting the start-up) and generated reference voltage. This makes it very difficult to achieve both desired fast start-up and reference voltages at the same time.

(40) It is possible largely to decouple the setting of reference voltages and speed-up of the reference voltage generators 350, 360, and this leads to a wider allowable range of input voltage gradients.

(41) Returning to FIG. 15, consider the system 300 the reference generator 370, which provides a reference output V.sub.ref_BB, which sets the body bias of the low V.sub.TH transistor 410. The reference generator 370 speeds up the reference generation, as illustrated in the graph of FIG. 10, thus setting up the detection threshold sooner and allowing higher input voltage gradients.

(42) This requires a body-biasing method. Again, commonly-used bandgap reference circuits use too much power. Known lower power body bias schemes are shown in FIG. 11. For standard CMOS process technology, the body terminal (B) of NMOS transistors is connected to the lowest potential in the circuits, e.g. V.sub.COM, a common reference (which may be ground), as shown in the left-hand circuit of FIG. 11. This results in a negative body-source voltage i.e. V.sub.BS=V.sub.ref, which strongly constrains the current level through the low-V.sub.TB transistor and hence that charging the output parasitic capacitor. Flexibility is provided in isolated CMOS process technology, which allows shorting body and source terminals, as shown in the right-hand circuit of FIG. 11.

(43) FIG. 12 is a schematic representation of the circuit of FIG. 9, with an additional body-bias generator, whilst FIG. 13 is a schematic diagram showing a body-bias circuit 500 which introduces an additional body-bias generator.

(44) The body-bias circuit 500 of FIG. 13 sets the parameter V.sub.ref_BB to be higher than V.sub.ref so that V.sub.BS becomes positive. This further increases the charging current and makes the current controllable, which in turn speeds up the start-up. The V.sub.ref_BB value can be customised for different V.sub.IN gradients to ensure that V.sub.ref has settled before V.sub.IN reaches the desired detection threshold. For instance, setting a higher V.sub.ref_BB allows for a steeper V.sub.IN gradient.

(45) The transistor sizes of the body-bias generator should be chosen in such a way that V.sub.ref_BB has a steeper gradient than V.sub.ref when V.sub.IN rises. This ensures a positive body-source voltage during the start-up.

(46) FIG. 14 is a schematic representation of a power-gating circuit 120 suitable for use in the voltage detection system 100 of FIG. 5. The power-gating transistor 122 (labelled MP2 in FIGS. 5 and 22) should be a medium-gate-oxide (5.5 V breakdown) PMOS transistor because its source-gate voltage can be as high as 2.8 V (corresponding to the threshold of the first voltage detector 142) before its gate-drive signal goes high. By contrast, the power-gating transistor 124 (labelled MP1 in FIGS. 5 and 22) can be a thin-gate-oxide PMOS transistor because its source-gate voltage does not exceed 0.6 V (corresponding to the threshold of the second voltage detector 144) and its low gate-threshold voltage helps the third (low voltage range) detector 146 start to operate at a low input voltage.

(47) Ideally, the input voltage V.sub.IN(L) of the third detector 146 will drop after the transistor 122 (MP2) is switched off for protecting this detector. However, in some thin-gate-oxide CMOS process technologies, the leakage current through the transistor 124 (MP1) (when OFF) can be sufficiently high so that V.sub.IN(L) can continue to rise and follow the input voltage V.sub.IN(M) of the second (medium voltage range) detector 144. This may cause overvoltage damage to the third detector 146 especially when V.sub.IN(M) has a slow voltage gradient. A simple but efficient protection solution is to add a route to ground (or a common reference) for the leakage current. In the power gating circuit 120 of FIG. 14, this is implemented with a diode-connected NMOS transistor 126 (labelled MN0), which is a thick-gate-oxide (high gate-threshold) transistor. When the second voltage detector 144 output V.sub.OUT(M) goes high, which switches off the transistor 124 (MP1) (zero gate-source voltage), the two transistors 124 (MP1) and 126 (MN0) are configured as the ultra-low-power two-transistor voltage reference illustrated in FIG. 9. The reference circuit clamps V.sub.IN(L) to a fixed voltage while consuming pico-amperes current only, and by adjusting the W/L ratios of transistors 124 and 126 (MP1 and MN0), V.sub.IN(L) can be set at a safe voltage for the third voltage detector 146. Before transistor 124 (MP1) is switched off and while the third voltage detector 146 is operating normally, transistor 126 (MN0) draws negligible current from the input V.sub.IN(L) because its gate-threshold is much higher than V.sub.IN(L) and thus this transistor operates in its deep subthreshold region.

(48) The voltage detector system described herein combines ultra-low power consumption, low detection threshold and wide operating range. It is useful for a wide variety of applications including high- and low-side signal monitoring and power-gating, but also for low power control components such as oscillators, gate-drives, and switching devices in low-power converters. For example, due to the voltage detector system's low quiescent input current, capacitive or resistive divider circuits using 100-1000 M resistors can be used to adjust the detection threshold, for example to operate a load only over a desired rail voltage band, commonly referred to as Under-Voltage Lockout. Similarly, high value M pull-up resistors can be used to convert the output into a 2-level output, for example for use in ring oscillators, timers, clocks, wake-up circuits, and pulse generating circuits. This ability to use high-impedance (capacitive or resistive) peripheral components leads to control circuits that use only a few nA of current, which is important for the miniaturisation of wireless sensor nodes, wearable medical health sensors, and internet of things devices.

(49) The above embodiments are described by way of example only. Many variations are possible without departing from the invention as defined by the appended claims.