A METHOD AND AN APPARATUS FOR REDUCING THE EFFECT OF LOCAL PROCESS VARIATIONS OF A DIGITAL CIRCUIT ON A HARDWARE PERFORMANCE MONITOR

Abstract

A method and an apparatus for reducing the effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values c.sub.n of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value c.sub.mean of the measured performance values c.sub.n, as an approximation of an ideal performance value c.sub.0, selecting one performance value c.sub.j of the set of performance values c.sub.n by a signal converter, comparing the performance value c.sub.j with a reference value c.sub.ref by a controller, resulting in a deviation value c, and controlling an actuator by using the deviation c for regulating the local global process variations to the approximation c.sub.mean of the ideal performance value c.sub.0.

Claims

1. A method for reducing the effect of local process variations of a digital circuit on a hardware performance monitor, the method comprising the following steps: measuring a set of performance values c.sub.n of the digital circuit by n identical hardware performance monitors, whereas n is a natural number greater than 1; determining an average value c.sub.mean of the measured performance values c.sub.n, as an approximation of an ideal performance value c.sub.0; selecting one performance value c.sub.j of the set of performance values c.sub.n by a signal converter; comparing the performance value c.sub.j with a reference value c.sub.ref by a controller, resulting in a deviation value c; and controlling an actuator by using the deviation c for regulating the local process variations to the approximation c.sub.mean of the ideal performance value c.sub.0.

2. The method according to claim 1, wherein the average value c.sub.mean is determined by adding the performance values c.sub.n of the n hardware performance monitors and dividing the sum by n.

3. The method according to claim 2, wherein the selected performance value c.sub.j is used for determining a mismatch scaling factor g by g=c.sub.mean/c.sub.j, whereas the scaling factor g is used for updating the reference value c.sub.ref to c.sub.ref=c.sub.ref/g before controlling the actuator.

4. The method according to claim 3, wherein the actuator is controlled by the deviation c=c.sub.refc.sub.j.

5. The method according to claim 2, wherein the performance value c.sub.j is selected by a criterion therein that said performance value c.sub.j is closest to c.sub.mean.

6. The method according to claim 3, wherein the actuator is adjusted until c.sub.ref=c.sub.mean before the selected performance value c.sub.j is used for updating the reference value c.sub.ref to c.sub.ref=c.sub.j and before continuing the controlling of the actuator with only the one selected performance value c.sub.j of the one hardware performance monitor j.

7. The method according to claim 1, wherein a low-pass integral loop filter is used as a controller which uses only one performance value c.sub.j of the set of performance values of n identical hardware performance monitors in one regulation step of the actuator, the control loop is continuously performed until all performance values c.sub.n has been used consecutively, and a deviation of (c.sub.meanc.sub.ref) determined in each regulation step is averaged and stored in an integrator register of the integral loop filter.

8. The method according to claim 1, wherein a low-pass integral loop filter as a controller is used, which uses only one performance value c.sub.j of the set of performance values c of n identical hardware performance monitors in one regulation step of the actuator, the control loop is continuously performed until all performance values c.sub.n has been non-deterministic selected and used, and an average deviation of (c.sub.meanc.sub.ref) determined in each regulation step is averaged and stored in an integrator register of the integral loop filter.

9. The method according to claim 8, wherein one or more hardware performance monitors are excluded from being selected.

10. The method according to claim 9, wherein a mismatch of the hardware performance monitors are additionally considered during a timing and power characterization process of digital components, by means of calculating a deviation of the bias voltages V from a previously simulated standard deviation of the hardware performance monitor results and considering this as a pessimism for a library characterization.

11. An apparatus for reducing the effect of local process variations of an integrated circuit on hardware performance monitors performing the method according to claim 1, the apparatus comprising a digital circuit, a control unit, an actuator and a set of n identical hardware performance monitors monitoring performance values of the digital circuit, whereas the control unit, the actuator, the digital circuit and the set of hardware performance monitors forming a closed control loop, and whereas the control unit comprises a signal converter and a controller for selecting and performing the control signals for the actuator.

12. The apparatus according to claim 11, wherein the controller is linear, especially a proportional-integral filter or comprises non-linear elements.

13. The apparatus according to claim 11, wherein the actuator is a body bias generator or a supply voltage generator controlled adaptively for the digital circuit.

14. The apparatus according to claim 11, wherein the apparatus comprises two hardware performance monitors, more preferred three hardware performance monitors, especially preferred four hardware performance monitors.

15. The method according to claim 1, wherein the actuator is controlled by the deviation c=c.sub.refc.sub.j.

16. The method according to claim 1, wherein one or more hardware performance monitors are excluded from being selected.

17. The method according to claim 1, wherein a mismatch of the hardware performance monitors are additionally considered during a timing and power characterization process of digital components, by means of calculating a deviation of the bias voltages V from a previously simulated standard deviation of the hardware performance monitor results and considering this as a pessimism for a library characterization.

18. The method according to claim 2, wherein the actuator is adjusted until c.sub.ref=c.sub.mean before a selected performance value c.sub.j is used for updating the reference value c.sub.ref to c.sub.ref=c.sub.j and before continuing the controlling of the actuator with only the one selected performance value c.sub.j of the one hardware performance monitor j.

Description

[0038] The appended drawings show

[0039] FIG. 1 Block diagram of the closed loop system for adaptive bias regulation with multiple hardware performance monitors;

[0040] FIG. 2 Illustration of a) the random distribution of the hardware performance monitor read-out results c and b) the narrowed distribution of the mean value c.sub.mean of a number of n sensor values.

[0041] In a first embodiment of the inventive method, multiple hardware performance values c.sub.1, c.sub.2, . . . , c.sub.n are read out, forming an initial mismatch calibration step. Afterwards these read-out values are used to determine an average value c.sub.mean (FIG. 2) by adding all c.sub.j in consecutive read-outs and dividing the sum by n. The division can be realized as digital binary shift operation in case n is a power of 2. Then one hardware performance value c.sub.j out of the n hardware performance monitor values is picked. With this value c.sub.j a mismatch scaling factor g by g=c.sub.mean/c.sub.j is determined, which is the correction factor of the individual HPM value to the mean value. The stored reference value c.sub.ref is updated to c.sub.ref=c.sub.ref/g=c.sub.ref/c.sub.mean.Math.c.sub.j. This requires the arithmetic operation of a division. At last the regulation is run with the selected hardware performance monitor j 2.

[0042] In a second embodiment of the inventive method, multiple hardware performance values c.sub.1, c.sub.2, . . . , c.sub.n are read out, forming an initial mismatch calibration step. Afterwards these read-out values are used to determine an average value c.sub.mean by adding all c.sub.j in consecutive read-outs and dividing the sum by n. The division can be realized as digital binary shift operation in case n is a power of 2. Then one hardware performance value c.sub.j whose read-out value c.sub.j is closest to c.sub.mean is picked. At last, the regulation is run with the selected hardware performance monitor j 2.

[0043] In a third embodiment, for each regulation step all n hardware performance values c.sub.1, c.sub.2, . . . , c.sub.n are read out, and these read-out values are used to determine an average value c.sub.mean by adding all c.sub.j in consecutive read-outs and dividing the sum by n. The mean value c.sub.mean is compared to c.sub.ref and the actuator is adjusted. After the loop has settled, which means that c.sub.mean=c.sub.ref one hardware performance value c.sub.j out of the n hardware performance monitor values is picked. The value c.sub.j is read out. Afterwards, the stored reference value c.sub.ref is updated to c.sub.ref=c.sub.j. As advantage, this does not require the arithmetic operation of a division. At last, the regulation is run with only a selected hardware performance monitor j 2.

[0044] In a fourth embodiment and in case a loop filter with low-pass integral characteristics is used, the regulation is performed using multiple HPMs. In each regulation step, only one HPM is read. In consecutive regulation steps the next HPM from the set is read. Therefore, the closed loop regulation continuously cycles through the HPMs. The integrator register of the digital low pass filter is used for averaging, i.e. storing the average deviation (cmeancref). No additional arithmetic circuits are required. In case a PI controller is used, the proportional gain should be low to suppress the error of successive read-outs of hardware performance monitors with a mismatch from cmean.

[0045] In a fifth embodiment and in case a loop filter with low-pass integral characteristics is used, the regulation is performed using multiple HPMs. In each regulation step, only one HPM 2 is read. In consecutive regulation steps another HPM 2 from the set is read. The HPM 2 to be read next is selected by an algorithm, including deterministic pseudo random selection, and also including non-deterministic random selection. The integrator register of the digital low pass filter is used for averaging, i.e. storing the average deviation (cmeancref). No additional arithmetic circuits are required. In case a PI controller is used, the proportional gain should be low to suppress the error of successive read-outs of hardware performance monitors with mismatch from cmean.

[0046] The mismatch of the hardware performance monitors has to be considered during modelling of the closed loop bias regulations. Especially when the resulting bias voltages (e.g. N-Well and P-Well voltages) are required as parameter for timing and power characterization of digital circuit components (e.g. standard cells, memory macros), which are operated in the regulated digital design domain. The mismatch of the hardware performance monitor can be considered by means of safety margins (pessimisms) for the bias voltages.

[0047] The determination of body bias pessimism or also called safety margins for consideration of variability in these voltages can be addressed as follows: If a single bias voltage V1 is considered (e.g. bias VDD in adaptive voltage scaling, single well adaptive body biasing) a linearized sensitivity k1 between the bias voltage V1 and a hardware performance monitor count value c can be determined with k1=dc/dV1, by means of circuit simulations or measurements; then a standard deviation c of the hardware performance monitor result c from Monte Carlo simulations or statistical measurements is determined. Afterward, a safety margin V1 for p-sigma pessimism (e.g. p=3) by V1=n.Math.c/k1 is determined. This safety margin V1 is optionally and additionally considered for characterization of standard cell in an integrated circuit.

[0048] In another case, if two bias voltages [V1, V2] are considered (e.g. adaptive body bias with n-well and p-well voltages), and two hardware performance monitors with results c1 and c2 are used in the regulation loop. For this setup selective, linearized sensitivities are determined, organized as matrix A=[k.sub.11,k.sub.12; k.sub.21,k.sub.22] with [0049] k.sub.11=dc.sub.1/dV.sub.1 [0050] k.sub.12=dc.sub.1/dV.sub.2 [0051] k.sub.21=dc.sub.2/dV.sub.1 [0052] k.sub.22=dc.sub.2/dV.sub.2.
A standard deviation vector b=[.sub.c1, .sub.c2] of the hardware performance monitor result c.sub.1 and c.sub.2 from Monte Carlo simulations or statistical measurements is determined. Therewith, a vector of safety margins v=[V.sub.1, V.sub.2] by v=A.sup.1.Math.b (the inverse of matrix A multiplied with the vector b) is calculated. These safety margins .sub.V1 and V.sub.2 can be optionally and additionally considered for characterization of standard cell in an integrated circuit.

[0053] In another case, if n (n>2) bias voltages and n PVT hardware performance monitors are used, the previous explained procedure can be applied, but with generalizes a n-by-n matrix A and vectors b and v of length n.

[0054] The safety margins V are considered in the characterization process of standard integrated circuits by: [0055] Slow timing: Addition or subtraction of V such that the resulting pessimism leads to slower timing [0056] Typical timing: No addition or subtraction of V [0057] Fast timing: Addition or subtraction of V such that the resulting pessimism leads to faster timing.

[0058] The library characterization of the circuit blocks in the regulated domain is performed with these margins considered.

[0059] The pessimism or safety margins of the bias voltages will be illustrated by two examples.

Example 1

[0060] One regulated supply voltage VDD for adaptive voltage scaling is considered: V.sub.1=VDD (supply voltage), with V.sub.1=VDD>0, the safety margin is added to the nominal values of VDD.sub.0 as described: [0061] Slow timing: (VDD)=(VDD.sub.0VDD) [0062] Typical timing: (VDD)=(VDD.sub.0) [0063] Fast timing: (VDD)=(VDD.sub.0+VDD)

Example 2

[0064] Two bias voltages for adaptive body biasing are considered: V.sub.1=VPW.sub.j (p-well voltage pessimism for hardware performance monitor j) V.sub.2=VNW.sub.j (n-well voltage for hardware performance monitor j), with .sub.V1>0 and V.sub.2>0 based on the inventive method for characterization of a standard cell, the safety margins VNWs and VPWs, representing the hardware performance monitor mismatch, are added to the nominal values of VNW.sub.c0 and VPW.sub.c0, additionally to the VNW.sub.a and VPW.sub.a actuator pessimism, which considers static and dynamic mismatch of the bias voltage actuators (e.g. charge pumps): [0065] Forward Body Biasing (FBB): [0066] Slow timing: (VPW.sub.c,VNW.sub.c)=(VNW.sub.c0VNW.sub.aVNW.sub.s,VPW.sub.c0+VPW.sub.a+VPW.sub.s) [0067] Typical timing: (VPW.sub.c,VNW.sub.c)=(VNW.sub.c0,VPW.sub.c0) [0068] Fast timing: (VPW.sub.c,VNW.sub.c)=(VNW.sub.c0+VNW.sub.a+VNW.sub.j,VPW.sub.c0VPW.sub.aVPW.sub.j) [0069] Reverse Body Biasing (RBB): [0070] Slow timing: (VPW.sub.c,VNW.sub.c)=(VNW.sub.c0+VNW.sub.a+VNW.sub.s,VPW.sub.c0VPW.sub.aVPWs) [0071] Typical timing: (VPW.sub.c,VNW.sub.c)=(VNW.sub.c0,VPW.sub.c0) [0072] Fast timing: (VPW.sub.c,VNW.sub.c)=(VNW.sub.c0VNW.sub.aVNW.sub.s,VPW.sub.c0+VPW.sub.a+VPW.sub.s),
whereas s stands for the mismatch sensitivity. This term describes the additional safety margin due to mismatch of the hardware performance monitors.

[0073] The invention allows to consider the adaptive bias voltages, e.g. VNW and VPW which are present in the operation of the circuit, e.g. when operated in a closed loop biasing scheme with hardware performance monitor, during cell characterization and implementation. Thereby, pessimisms are reduced and better power performance and area results can be obtained.

[0074] In the following, the invention will be illustrated by two concrete embodiments, on the one hand using a single hardware performance monitor as state of the art and on the other hand using four performance monitors according to the invention:

[0075] Using a single hardware performance monitor, its nominal output c (period_mean, period) and standard deviation .sub.c (period_std) is determined. Afterwards the sensitivities k are determined, and .sub.V1=VPW.sub.s (dVPW) and .sub.V1=VNW.sub.s (dVNW) are calculated by means of the second embodiment as described above (with p=3 sigma). This is repeated for different corner settings of a standard cell. E.g. this results in dVPW=111 mW and dVNW=100 mV (at corner worst case: VDD=0.36V T=40 C.) pessimism which has to be considered during characterization.

[0076] Using four hardware performance monitors 2 and average their results by means of the invention, its nominal output c (period_mean, period) and standard deviation ac (period_std) of the averaged result c.sub.mean is determined. Afterwards, the sensitivities k are determined, and V.sub.1=VPW.sub.s (dVPW) and V.sub.1=VNW.sub.s (dVNW) are calculated by means of the second embodiment as described above (with p=3 sigma). This is repeated for different corner settings of a standard cell. E.g. this results in dVPW=54 mW and dVNW=51 mV (at corner worst case VDD=0.36V T=40 C.) pessimism which has to be considered during characterization.

[0077] By means of the invention the variability of the hardware performance monitor(s) in the regulation loop and thereby the required pessimism for characterization is reduced by approx. factor 2 when using four hardware performance monitors.

LIST OF REFERENCE SIGNS

[0078] 1 integrated circuit [0079] 2 hardware performance monitor [0080] 3 digital circuit [0081] 4 control unit [0082] 5 signal converter [0083] 6 controller [0084] 7 actuator [0085] 8 reference value register [0086] 9 closed control loop [0087] 10 reference value [0088] 11 reference clock signal